- handle parsing of assembler constraints in backends. Provide functions for

[libfirm] / ir / be / ia32 / ia32_x87.c

diff --git a/ir/be/ia32/ia32_x87.c b/ir/be/ia32/ia32_x87.c
index 94740b4..c724764 100644 (file)
--- a/ir/be/ia32/ia32_x87.c
+++ b/ir/be/ia32/ia32_x87.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 1995-2007 University of Karlsruhe.  All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe.  All right reserved.
  *
  * This file is part of libFirm.
  *
@@ -1213,8 +1213,9 @@ static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
                        Solution:
                                - stack not full: push value and fstp
                                - stack full: fstp value and load again
+                       Note that we cannot test on mode_E, because floats might be 96bit ...
                */
-               if (mode == mode_E || mode == mode_Ls) {
+               if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) {
                        if (depth < N_x87_REGS) {
                                /* ok, we have a free register: push + fstp */
                                x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
@@ -1330,6 +1331,58 @@ GEN_LOAD(fld1)
 GEN_STORE(fst)
 GEN_STORE(fist)
 
+/**
+* Simulate a virtual fisttp.
+*
+* @param state  the x87 state
+* @param n      the node that should be simulated (and patched)
+*/
+static int sim_fisttp(x87_state *state, ir_node *n) {
+       x87_simulator         *sim = state->sim;
+       ir_node               *val = get_irn_n(n, n_ia32_vfst_val);
+       const arch_register_t *op2 = x87_get_irn_register(sim, val);
+       int                   insn = NO_NODE_ADDED;
+       ia32_x87_attr_t *attr;
+       int op2_reg_idx, op2_idx, depth;
+
+       op2_reg_idx = arch_register_get_index(op2);
+       if (op2_reg_idx == REG_VFP_UKNWN) {
+               /* just take any value from stack */
+               if (state->depth > 0) {
+                       op2_idx = 0;
+                       DEBUG_ONLY(op2 = NULL);
+               } else {
+                       /* produce a new value which we will consume immediately */
+                       x87_create_fldz(state, n, op2_reg_idx);
+                       op2_idx = x87_on_stack(state, op2_reg_idx);
+                       assert(op2_idx >= 0);
+               }
+       } else {
+               op2_idx = x87_on_stack(state, op2_reg_idx);
+               DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
+               assert(op2_idx >= 0);
+       }
+
+       depth = x87_get_depth(state);
+
+       /* Note: although the value is still live here, it is destroyed because
+          of the pop. The register allocator is aware of that and introduced a copy
+          if the value must be alive. */
+
+       /* we can only store the tos to memory */
+       if (op2_idx != 0)
+               x87_create_fxch(state, n, op2_idx);
+
+       x87_pop(state);
+       x87_patch_insn(n, op_ia32_fisttp);
+
+       attr = get_ia32_x87_attr(n);
+       attr->x87[1] = op2 = &ia32_st_regs[0];
+       DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
+
+       return insn;
+}  /* sim_fisttp */
+
 static int sim_FtstFnstsw(x87_state *state, ir_node *n) {
        x87_simulator         *sim         = state->sim;
        ia32_x87_attr_t       *attr        = get_ia32_x87_attr(n);
@@ -1543,7 +1596,7 @@ static int sim_Fucom(x87_state *state, ir_node *n) {
        }
 
        /* patch the operation */
-       if(is_ia32_vFucomFnstsw(n)) {
+       if (is_ia32_vFucomFnstsw(n)) {
                int i;
 
                switch(pops) {
@@ -1742,14 +1795,14 @@ static int sim_Copy(x87_state *state, ir_node *n) {
        ir_node                     *pred;
        const arch_register_t       *out;
        const arch_register_t       *op1;
-       const arch_register_class_t *class;
+       const arch_register_class_t *cls;
        ir_node                     *node, *next;
        ia32_x87_attr_t             *attr;
        int                         op1_idx, out_idx;
        unsigned                    live;
 
-       class = arch_get_irn_reg_class(sim->arch_env, n, -1);
-       if (class->regs != ia32_vfp_regs)
+       cls = arch_get_irn_reg_class(sim->arch_env, n, -1);
+       if (cls->regs != ia32_vfp_regs)
                return 0;
 
        pred = get_irn_n(n, 0);
@@ -2293,7 +2346,6 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
        sim->arch_env   = arch_env;
        sim->n_idx      = get_irg_last_idx(irg);
        sim->live       = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
-       sim->isa        = (ia32_isa_t *)arch_env->isa;
 
        DB((dbg, LEVEL_1, "--------------------------------\n"
                "x87 Simulator started for %+F\n", irg));
@@ -2313,6 +2365,7 @@ static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
        register_sim(op_ia32_vfabs,        sim_fabs);
        register_sim(op_ia32_vfchs,        sim_fchs);
        register_sim(op_ia32_vfist,        sim_fist);
+       register_sim(op_ia32_vfisttp,      sim_fisttp);
        register_sim(op_ia32_vfst,         sim_fst);
        register_sim(op_ia32_vFtstFnstsw,  sim_FtstFnstsw);
        register_sim(op_ia32_vFucomFnstsw, sim_Fucom);