#include "gen_ia32_regalloc_if.h"
#include "ia32_x87.h"
-#ifndef NDEBUG
-#define DEBUG_ONLY(x) x
-#else /* NDEBUG */
-#define DEBUG_ONLY(x)
-#endif /* NDEBUG */
-
#define N_x87_REGS 8
/* first and second binop index */
#define MASK_TOS(x) ((x) & (N_x87_REGS - 1))
/** the debug handle */
-static firm_dbg_module_t *dbg = NULL;
+DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
/**
* An exchange template.
/**
* Simulate a virtual Store
*/
-static void sim_fst(x87_state *state, ir_node *n, const arch_env_t *env) {
+static void sim_store(x87_state *state, ir_node *n, const arch_env_t *env, ir_op *op, ir_op *op_p) {
int op2_idx;
const arch_register_t *op2 = arch_get_irn_register(env, get_irn_n(n, STORE_VAL_IDX));
ia32_attr_t *attr;
x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
if (is_vfp_live(op2, live))
- x87_patch_insn(n, op_ia32_fst);
+ x87_patch_insn(n, op);
else {
x87_pop(state);
- x87_patch_insn(n, op_ia32_fstp);
+ x87_patch_insn(n, op_p);
}
attr = get_ia32_attr(n);
sim_unop(state, n, env, op_ia32_##op); \
}
+#define GEN_STORE(op) \
+static void sim_##op(x87_state *state, ir_node *n, const arch_env_t *env) { \
+ sim_store(state, n, env, op_ia32_##op, op_ia32_##op##p); \
+}
+
/* all stubs */
GEN_BINOP(fadd)
GEN_BINOPR(fsub)
GEN_BINOP(fmul)
GEN_BINOPR(fdiv)
-GEN_LOAD(fld)
-GEN_LOAD(fldz)
-GEN_LOAD(fld1)
-GEN_LOAD2(fConst, fldConst)
-
GEN_UNOP(fabs)
GEN_UNOP(fchs)
GEN_UNOP(fsin)
GEN_UNOP(fcos)
GEN_UNOP(fsqrt)
+GEN_LOAD(fld)
+GEN_LOAD(fild)
+GEN_LOAD(fldz)
+GEN_LOAD(fld1)
+GEN_LOAD2(fConst, fldConst)
+
+GEN_STORE(fst)
+GEN_STORE(fist)
+
+
/**
* Simulate a be_Copy.
*/
sim->blk_states = pmap_create();
sim->env = env;
- FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
+ FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
firm_dbg_set_mask(dbg, SET_LEVEL_2);
DB((dbg, LEVEL_1, "--------------------------------\n"
#define ASSOC_BE(op) (op_be_ ## op)->ops.generic = (op_func)(sim_##op)
ASSOC_IA32(fConst);
ASSOC_IA32(fld);
+ ASSOC_IA32(fild);
ASSOC_IA32(fld1);
ASSOC_IA32(fldz);
ASSOC_IA32(fadd);
ASSOC_IA32(fsin);
ASSOC_IA32(fcos);
ASSOC_IA32(fsqrt);
+ ASSOC_IA32(fist);
ASSOC_IA32(fst);
ASSOC_BE(Copy);
ASSOC_BE(Call);
x87_simulator sim;
int i;
- /* we need liveness info for the current graph */
+ /* we need liveness info for the current graph */
be_liveness(irg);
- /* create the simulator */
+ /* create the simulator */
x87_init_simulator(&sim, irg, env);
start_block = get_irg_start_block(irg);
}
} while (! pdeq_empty(worklist));
- /* kill it */
+ /* kill it */
x87_destroy_simulator(&sim);
}