#include "error.h"
#include "../belive_t.h"
-#include "../besched_t.h"
-#include "../benode_t.h"
+#include "../besched.h"
+#include "../benode.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_new_nodes.h"
static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
static x87_state *empty = (x87_state *)&_empty;
+/**
+ * Return values of the instruction simulator functions.
+ */
enum {
- NO_NODE_ADDED = 0, /**< No node was added. */
- NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */
+ NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
+ NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
+ in the schedule AFTER the current node. */
};
/**
* @param state the x87 state
* @param n the node to be simulated
*
- * @return NODE_ADDED if a node was added AFTER n in schedule,
- * NO_NODE_ADDED else
+ * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
+ * simulated further
+ * NO_NODE_ADDED otherwise
*/
typedef int (*sim_func)(x87_state *state, ir_node *n);
{
x87_state *res = x87_alloc_state(sim);
- memcpy(res, src, sizeof(*res));
+ *res = *src;
return res;
} /* x87_clone_state */
mode = get_irn_mode(proj);
if (mode_is_float(mode)) {
res = proj;
- set_irn_mode(proj, mode_E);
+ set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
}
}
}
} else if (mode_is_float(mode))
- set_irn_mode(n, mode_E);
+ set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
return res;
} /* x87_patch_insn */
/**
* Wrap the arch_* function here so we can check for errors.
*/
-static INLINE const arch_register_t *x87_get_irn_register(const ir_node *irn)
+static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
{
const arch_register_t *res = arch_get_irn_register(irn);
return res;
} /* x87_get_irn_register */
+static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
+ int pos)
+{
+ const arch_register_t *res = arch_irn_get_register(irn, pos);
+
+ assert(res->reg_class->regs == ia32_vfp_regs);
+ return res;
+} /* x87_irn_get_register */
+
/* -------------- x87 perm --------------- */
/**
ir_node *fxch;
ia32_x87_attr_t *attr;
- fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block);
+ fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
{
ir_node *fxch;
ia32_x87_attr_t *attr;
- ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
x87_fxch(state, pos);
- fxch = new_rd_ia32_fxch(NULL, irg, block);
+ fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
x87_push_dbl(state, arch_register_get_index(out), pred);
- fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpush);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
while (num > 0) {
x87_pop(state);
if (ia32_cg_config.use_ffreep)
- fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
else
- fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpop);
attr->x87[0] = &ia32_st_regs[0];
attr->x87[1] = &ia32_st_regs[0];
*/
static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx)
{
- ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
ir_node *fldz;
- fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
+ fldz = new_bd_ia32_fldz(NULL, block, ia32_reg_classes[CLASS_ia32_st].mode);
sched_add_before(n, fldz);
DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
/* --------------------------------- simulators ---------------------------------------- */
-#define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0)
-
-/* Pseudocode:
-
-
-
-
-
-
-*/
-
/**
* Simulate a virtual binop.
*
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
const arch_register_t *op1_reg = x87_get_irn_register(op1);
const arch_register_t *op2_reg = x87_get_irn_register(op2);
- const arch_register_t *out = x87_get_irn_register(n);
+ const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
*
* @return NO_NODE_ADDED
*/
-static int sim_load(x87_state *state, ir_node *n, ir_op *op)
+static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
{
- const arch_register_t *out = x87_get_irn_register(n);
+ const arch_register_t *out = x87_irn_get_register(n, res_pos);
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
- assert(out == x87_get_irn_register(n));
+ assert(out == x87_irn_get_register(n, res_pos));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
if (live_after_node) {
/*
- Problem: fst doesn't support mode_E (spills), only fstp does
+ Problem: fst doesn't support 96bit modes (spills), only fstp does
+ fist doesn't support 64bit mode, only fistp
Solution:
- stack not full: push value and fstp
- stack full: fstp value and load again
Note that we cannot test on mode_E, because floats might be 96bit ...
*/
- if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) {
+ if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
if (depth < N_x87_REGS) {
/* ok, we have a free register: push + fstp */
x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
x87_patch_insn(n, op_p);
block = get_nodes_block(n);
- irg = get_irn_irg(n);
- vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
+ vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), new_NoMem(), get_ia32_ls_mode(n));
/* copy all attributes */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
- rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
- mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
+ rproj = new_r_Proj(block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
+ mproj = new_r_Proj(block, vfld, mode_M, pn_ia32_vfld_M);
mem = get_irn_Proj_for_mode(n, mode_M);
assert(mem && "Store memory not found");
arch_set_irn_register(rproj, op2);
/* reroute all former users of the store memory to the load memory */
+ irg = get_irn_irg(n);
edges_reroute(mem, mproj, irg);
/* set the memory input of the load to the store memory */
set_irn_n(vfld, n_ia32_vfld_mem, mem);
if (op2_idx != 0)
x87_create_fxch(state, n, op2_idx);
- /* mode != mode_E -> use normal fst */
+ /* mode size 64 or smaller -> use normal fst */
x87_patch_insn(n, op);
}
} else {
#define GEN_BINOP(op) _GEN_BINOP(op, op)
#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
-#define GEN_LOAD2(op, nop) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_load(state, n, op_ia32_##nop); \
+#define GEN_LOAD(op) \
+static int sim_##op(x87_state *state, ir_node *n) { \
+ return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
}
-#define GEN_LOAD(op) GEN_LOAD2(op, op)
-
#define GEN_UNOP(op) \
static int sim_##op(x87_state *state, ir_node *n) { \
return sim_unop(state, n, op_ia32_##op); \
GEN_STORE(fist)
/**
-* Simulate a virtual fisttp.
-*
-* @param state the x87 state
-* @param n the node that should be simulated (and patched)
-*/
+ * Simulate a virtual fisttp.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_fisttp(x87_state *state, ir_node *n)
{
ir_node *val = get_irn_n(n, n_ia32_vfst_val);
const arch_register_t *op2 = x87_get_irn_register(val);
- int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
attr->x87[1] = op2 = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
- return insn;
+ return NO_NODE_ADDED;
} /* sim_fisttp */
+/**
+ * Simulate a virtual FtstFnstsw.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_FtstFnstsw(x87_state *state, ir_node *n)
{
x87_simulator *sim = state->sim;
attr->x87[1] = NULL;
attr->x87[2] = NULL;
- if (!is_vfp_live(reg_index_1, live)) {
+ if (!is_vfp_live(reg_index_1, live))
x87_create_fpop(state, sched_next(n), 1);
- return NODE_ADDED;
- }
return NO_NODE_ADDED;
-}
+} /* sim_FtstFnstsw */
/**
+ * Simulate a Fucom
+ *
* @param state the x87 state
* @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Fucom(x87_state *state, ir_node *n)
{
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
unsigned live = vfp_live_args_after(sim, n, 0);
- int permuted = attr->attr.data.ins_permuted;
- int xchg = 0;
- int pops = 0;
- int node_added = NO_NODE_ADDED;
+ bool permuted = attr->attr.data.ins_permuted;
+ bool xchg = false;
+ int pops = 0;
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
arch_register_get_name(op1), arch_register_get_name(op2)));
} else if (op2_idx == 0) {
/* res = op X tos */
permuted = !permuted;
- xchg = 1;
+ xchg = true;
} else {
/* bring the first one to tos */
x87_create_fxch(state, n, op1_idx);
op2_idx = 0;
}
/* res = op X tos, pop */
- pops = 1;
+ pops = 1;
permuted = !permuted;
- xchg = 1;
+ xchg = true;
} else {
/* both operands are dead here, check first for identity. */
if (op1_idx == op2_idx) {
}
/* res = op X tos, pop, pop */
permuted = !permuted;
- xchg = 1;
- pops = 2;
+ xchg = true;
+ pops = 2;
} else {
/* if one is already the TOS, we need two fxch */
if (op1_idx == 0) {
x87_create_fxch(state, n, op2_idx);
op2_idx = 0;
/* res = op X tos, pop, pop */
- pops = 2;
+ pops = 2;
permuted = !permuted;
- xchg = 1;
+ xchg = true;
} else if (op2_idx == 0) {
/* second one is TOS, move to st(1) */
x87_create_fxch(state, n, 1);
dst = op_ia32_Fucompi;
x87_pop(state);
x87_create_fpop(state, sched_next(n), 1);
- node_added = NODE_ADDED;
break;
default: panic("invalid popcount in sim_Fucom");
}
arch_register_get_name(op1)));
}
- return node_added;
-}
+ return NO_NODE_ADDED;
+} /* sim_Fucom */
+/**
+ * Simulate a Keep.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_Keep(x87_state *state, ir_node *node)
{
const ir_node *op;
int op_stack_idx;
unsigned live;
int i, arity;
- int node_added = NO_NODE_ADDED;
DB((dbg, LEVEL_1, ">>> %+F\n", node));
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
- if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
+ if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
x87_create_fpop(state, sched_next(node), 1);
- node_added = NODE_ADDED;
- }
}
DB((dbg, LEVEL_1, "Stack after: "));
DEBUG_ONLY(x87_dump_stack(state));
- return node_added;
-}
+ return NO_NODE_ADDED;
+} /* sim_Keep */
+/**
+ * Keep the given node alive by adding a be_Keep.
+ *
+ * @param node the node to kept alive
+ */
static void keep_float_node_alive(ir_node *node)
{
- ir_graph *irg;
- ir_node *block;
- ir_node *in[1];
- ir_node *keep;
- const arch_register_class_t *cls;
-
- irg = get_irn_irg(node);
- block = get_nodes_block(node);
- cls = arch_get_irn_reg_class(node, -1);
- in[0] = node;
- keep = be_new_Keep(cls, irg, block, 1, in);
+ ir_node *block = get_nodes_block(node);
+ ir_node *keep = be_new_Keep(block, 1, &node);
assert(sched_is_scheduled(node));
sched_add_after(node, keep);
*/
static ir_node *create_Copy(x87_state *state, ir_node *n)
{
- ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
ir_mode *mode = get_irn_mode(n);
ir_node *block = get_nodes_block(n);
ir_node *pred = get_irn_n(n, 0);
- ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
+ ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
ir_node *res;
const arch_register_t *out;
const arch_register_t *op1;
switch (get_ia32_irn_opcode(pred)) {
case iro_ia32_Unknown_VFP:
case iro_ia32_fldz:
- cnstr = new_rd_ia32_fldz;
+ cnstr = new_bd_ia32_fldz;
break;
case iro_ia32_fld1:
- cnstr = new_rd_ia32_fld1;
+ cnstr = new_bd_ia32_fld1;
break;
case iro_ia32_fldpi:
- cnstr = new_rd_ia32_fldpi;
+ cnstr = new_bd_ia32_fldpi;
break;
case iro_ia32_fldl2e:
- cnstr = new_rd_ia32_fldl2e;
+ cnstr = new_bd_ia32_fldl2e;
break;
case iro_ia32_fldl2t:
- cnstr = new_rd_ia32_fldl2t;
+ cnstr = new_bd_ia32_fldl2t;
break;
case iro_ia32_fldlg2:
- cnstr = new_rd_ia32_fldlg2;
+ cnstr = new_bd_ia32_fldlg2;
break;
case iro_ia32_fldln2:
- cnstr = new_rd_ia32_fldln2;
+ cnstr = new_bd_ia32_fldln2;
break;
default:
break;
if (cnstr != NULL) {
/* copy a constant */
- res = (*cnstr)(n_dbg, irg, block, mode);
+ res = (*cnstr)(n_dbg, block, mode);
x87_push(state, arch_register_get_index(out), res);
} else {
int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
- res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
+ res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
x87_push(state, arch_register_get_index(out), res);
int op1_idx, out_idx;
unsigned live;
- cls = arch_get_irn_reg_class(n, -1);
+ cls = arch_get_irn_reg_class_out(n);
if (cls->regs != ia32_vfp_regs)
return 0;
} /* sim_Copy */
/**
- * Returns the result proj of the call
+ * Returns the vf0 result Proj of a Call.
+ *
+ * @para call the Call node
*/
static ir_node *get_call_result_proj(ir_node *call)
{
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
- if (pn == pn_ia32_Call_vf0) {
+ if (pn == pn_ia32_Call_vf0)
return proj;
- }
}
return NULL;
* Simulate a ia32_Call.
*
* @param state the x87 state
- * @param n the node that should be simulated
+ * @param n the node that should be simulated (and patched)
*
* @return NO_NODE_ADDED
*/
*/
static int sim_Spill(x87_state *state, ir_node *n)
{
- assert(0 && "Spill not lowered");
+ panic("Spill not lowered before x87 simulator run");
return sim_fst(state, n);
} /* sim_Spill */
*/
static int sim_Reload(x87_state *state, ir_node *n)
{
- assert(0 && "Reload not lowered");
+ panic("Reload not lowered before x87 simulator run");
return sim_fld(state, n);
} /* sim_Reload */
return NO_NODE_ADDED;
} /* sim_Perm */
+/**
+ * Simulate the Barrier to generate Unknowns.
+ * We must push something on the stack for its value.
+ *
+ * @param state the x87 state
+ * @param irn the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_Barrier(x87_state *state, ir_node *node)
{
int i, arity;
/* create a zero */
block = get_nodes_block(node);
- zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E);
+ zero = new_bd_ia32_fldz(NULL, block, ia32_reg_classes[CLASS_ia32_st].mode);
x87_push(state, arch_register_get_index(reg), zero);
attr = get_ia32_x87_attr(zero);
}
return NO_NODE_ADDED;
-}
-
+} /* sim_Barrier */
/**
* Kill any dead registers at block start by popping them from the stack.
if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
if (ia32_cg_config.use_femms) {
/* use FEMMS on AMD processors to clear all */
- keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block);
+ keep = new_bd_ia32_femms(NULL, block);
} else {
/* use EMMS to clear all */
- keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block);
+ keep = new_bd_ia32_emms(NULL, block);
}
sched_add_before(first_insn, keep);
keep_alive(keep);
} /* x87_kill_deads */
/**
- * If we have PhiEs with unknown operands then we have to make sure that some
- * value is actually put onto the stack.
+ * If we have PhiEs with unknown operands in a block
+ * we have to make sure that some value is actually put onto the stack.
+ *
+ * @param state the x87 state
+ * @param block the block that should be checked
+ * @param pred_block check inputs from this predecessor block
+ * @param pos index of pred_block
*/
static void fix_unknown_phis(x87_state *state, ir_node *block,
ir_node *pred_block, int pos)
{
- ir_node *node, *op;
+ ir_node *phi, *op;
- sched_foreach(block, node) {
+ sched_foreach_Phi(block, phi) {
ir_node *zero;
const arch_register_t *reg;
ia32_x87_attr_t *attr;
- if (!is_Phi(node))
- break;
-
- op = get_Phi_pred(node, pos);
+ op = get_Phi_pred(phi, pos);
if (!is_ia32_Unknown_VFP(op))
continue;
- reg = arch_get_irn_register(node);
+ reg = arch_get_irn_register(phi);
/* create a zero at end of pred block */
- zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
+ zero = new_bd_ia32_fldz(NULL, pred_block, ia32_reg_classes[CLASS_ia32_st].mode);
x87_push(state, arch_register_get_index(reg), zero);
attr = get_ia32_x87_attr(zero);
assert(is_ia32_fldz(zero));
sched_add_before(sched_last(pred_block), zero);
- set_Phi_pred(node, pos, zero);
+ set_Phi_pred(phi, pos, zero);
}
-}
+} /* fix_unknown_phis */
/**
* Run a simulation and fix all virtual instructions for a block.
sim_func func;
ir_op *op = get_irn_op(n);
+ /*
+ * get the next node to be simulated here.
+ * n might be completely removed from the schedule-
+ */
next = sched_next(n);
- if (op->ops.generic == NULL)
- continue;
+ if (op->ops.generic != NULL) {
+ func = (sim_func)op->ops.generic;
- func = (sim_func)op->ops.generic;
+ /* simulate it */
+ node_inserted = (*func)(state, n);
- /* simulate it */
- node_inserted = (*func)(state, n);
-
- /*
- sim_func might have added an additional node after n,
- so update next node
- beware: n must not be changed by sim_func
- (i.e. removed from schedule) in this case
- */
- if (node_inserted != NO_NODE_ADDED)
- next = sched_next(n);
+ /*
+ * sim_func might have added an additional node after n,
+ * so update next node
+ * beware: n must not be changed by sim_func
+ * (i.e. removed from schedule) in this case
+ */
+ if (node_inserted != NO_NODE_ADDED)
+ next = sched_next(n);
+ }
}
start_block = get_irg_start_block(get_irn_irg(block));
bl_state->end = state;
} /* x87_simulate_block */
+/**
+ * Register a simulator function.
+ *
+ * @param op the opcode to simulate
+ * @param func the simulator function for the opcode
+ */
static void register_sim(ir_op *op, sim_func func)
{
assert(op->ops.generic == NULL);
op->ops.generic = (op_func) func;
-}
+} /* register_sim */
/**
* Create a new x87 simulator.
update_liveness(sim, block);
} /* update_liveness_walker */
+/*
+ * Run a simulation and fix all virtual instructions for a graph.
+ * Replaces all virtual floating point instructions and registers
+ * by real ones.
+ */
void x87_simulate_graph(be_irg_t *birg)
{
+ /* TODO improve code quality (less executed fxch) by using execfreqs */
+
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
be_assure_liveness(birg);
sim.lv = be_get_birg_liveness(birg);
-// sim.lv = be_liveness(be_get_birg_irg(birg));
be_liveness_assure_sets(sim.lv);
/* Calculate the liveness for all nodes. We must precalculate this info,
x87_destroy_simulator(&sim);
} /* x87_simulate_graph */
+/* Initializes the x87 simulator. */
void ia32_init_x87(void)
{
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
projects / libfirm / blobdiff