/*
- * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
* @brief This file implements the x87 support and virtual to stack
* register translation for the ia32 backend.
* @author Michael Beck
- * @version $Id$
*/
#include "config.h"
#include "debug.h"
#include "error.h"
-#include "../belive_t.h"
-#include "../besched.h"
-#include "../benode.h"
+#include "belive_t.h"
+#include "besched.h"
+#include "benode.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_new_nodes.h"
#include "ia32_x87.h"
#include "ia32_architecture.h"
-#define N_x87_REGS 8
-
-/* the unop index */
-#define UNOP_IDX 0
-
-#define MASK_TOS(x) ((x) & (N_x87_REGS - 1))
+#define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1))
/** the debug handle */
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
* The x87 state.
*/
typedef struct x87_state {
- st_entry st[N_x87_REGS]; /**< the register stack */
- int depth; /**< the current stack depth */
- int tos; /**< position of the tos */
- x87_simulator *sim; /**< The simulator. */
+ st_entry st[N_ia32_st_REGS]; /**< the register stack */
+ int depth; /**< the current stack depth */
+ int tos; /**< position of the tos */
+ x87_simulator *sim; /**< The simulator. */
} x87_state;
/** An empty state, used for blocks without fp instructions. */
x87_state *end; /**< state at the end or NULL if not assigned */
} blk_state;
-#define PTR_TO_BLKSTATE(p) ((blk_state *)(p))
-
/** liveness bitset for vfp registers. */
typedef unsigned char vfp_liveness;
vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
waitq *worklist; /**< Worklist of blocks that must be processed. */
- ia32_isa_t *isa; /**< the ISA object */
};
/**
static int x87_get_depth(const x87_state *state)
{
return state->depth;
-} /* x87_get_depth */
+}
+
+static st_entry *x87_get_entry(x87_state *const state, int const pos)
+{
+ assert(0 <= pos && pos < state->depth);
+ return &state->st[MASK_TOS(state->tos + pos)];
+}
/**
* Return the virtual register index at st(pos).
*/
static int x87_get_st_reg(const x87_state *state, int pos)
{
- assert(pos < state->depth);
- return state->st[MASK_TOS(state->tos + pos)].reg_idx;
-} /* x87_get_st_reg */
+ return x87_get_entry((x87_state*)state, pos)->reg_idx;
+}
#ifdef DEBUG_libfirm
-/**
- * Return the node at st(pos).
- *
- * @param state the x87 state
- * @param pos a stack position
- *
- * @return the IR node that produced the value at st(pos)
- */
-static ir_node *x87_get_st_node(const x87_state *state, int pos)
-{
- assert(pos < state->depth);
- return state->st[MASK_TOS(state->tos + pos)].node;
-} /* x87_get_st_node */
-
/**
* Dump the stack for debugging.
*
*/
static void x87_dump_stack(const x87_state *state)
{
- int i;
-
- for (i = state->depth - 1; i >= 0; --i) {
- DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
- x87_get_st_node(state, i)));
+ for (int i = state->depth; i-- != 0;) {
+ st_entry const *const entry = x87_get_entry((x87_state*)state, i);
+ DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
}
DB((dbg, LEVEL_2, "<-- TOS\n"));
-} /* x87_dump_stack */
+}
#endif /* DEBUG_libfirm */
/**
*/
static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
{
- assert(0 < state->depth);
- state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
- state->st[MASK_TOS(state->tos + pos)].node = node;
+ st_entry *const entry = x87_get_entry(state, pos);
+ entry->reg_idx = reg_idx;
+ entry->node = node;
DB((dbg, LEVEL_2, "After SET_REG: "));
- DEBUG_ONLY(x87_dump_stack(state));
-} /* x87_set_st */
+ DEBUG_ONLY(x87_dump_stack(state);)
+}
/**
* Set the tos virtual register.
static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
{
x87_set_st(state, reg_idx, node, 0);
-} /* x87_set_tos */
+}
/**
* Swap st(0) with st(pos).
*/
static void x87_fxch(x87_state *state, int pos)
{
- st_entry entry;
- assert(pos < state->depth);
-
- entry = state->st[MASK_TOS(state->tos + pos)];
- state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
- state->st[MASK_TOS(state->tos)] = entry;
-
- DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state));
-} /* x87_fxch */
+ st_entry *const a = x87_get_entry(state, pos);
+ st_entry *const b = x87_get_entry(state, 0);
+ st_entry const t = *a;
+ *a = *b;
+ *b = t;
+
+ DB((dbg, LEVEL_2, "After FXCH: "));
+ DEBUG_ONLY(x87_dump_stack(state);)
+}
/**
* Convert a virtual register to the stack index.
*/
static int x87_on_stack(const x87_state *state, int reg_idx)
{
- int i, tos = state->tos;
-
- for (i = 0; i < state->depth; ++i)
- if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
+ for (int i = 0; i < state->depth; ++i) {
+ if (x87_get_st_reg(state, i) == reg_idx)
return i;
+ }
return -1;
-} /* x87_on_stack */
+}
/**
* Push a virtual Register onto the stack, double pushed allowed.
*/
static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
{
- assert(state->depth < N_x87_REGS && "stack overrun");
+ assert(state->depth < N_ia32_st_REGS && "stack overrun");
++state->depth;
state->tos = MASK_TOS(state->tos - 1);
- state->st[state->tos].reg_idx = reg_idx;
- state->st[state->tos].node = node;
+ st_entry *const entry = x87_get_entry(state, 0);
+ entry->reg_idx = reg_idx;
+ entry->node = node;
- DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state));
-} /* x87_push_dbl */
+ DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
+}
/**
* Push a virtual Register onto the stack, double pushes are NOT allowed.
* @param state the x87 state
* @param reg_idx the register vfp index
* @param node the node that produces the value of the vfp register
- * @param dbl_push if != 0 double pushes are allowed
*/
static void x87_push(x87_state *state, int reg_idx, ir_node *node)
{
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
x87_push_dbl(state, reg_idx, node);
-} /* x87_push */
+}
/**
* Pop a virtual Register from the stack.
--state->depth;
state->tos = MASK_TOS(state->tos + 1);
- DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state));
-} /* x87_pop */
+ DB((dbg, LEVEL_2, "After POP: ")); DEBUG_ONLY(x87_dump_stack(state);)
+}
/**
* Empty the fpu stack
*/
static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
{
- pmap_entry *entry = pmap_find(sim->blk_states, block);
+ blk_state *res = pmap_get(blk_state, sim->blk_states, block);
- if (! entry) {
- blk_state *bl_state = obstack_alloc(&sim->obst, sizeof(*bl_state));
- bl_state->begin = NULL;
- bl_state->end = NULL;
+ if (res == NULL) {
+ res = OALLOC(&sim->obst, blk_state);
+ res->begin = NULL;
+ res->end = NULL;
- pmap_insert(sim->blk_states, block, bl_state);
- return bl_state;
+ pmap_insert(sim->blk_states, block, res);
}
- return PTR_TO_BLKSTATE(entry->value);
-} /* x87_get_bl_state */
+ return res;
+}
/**
* Creates a new x87 state.
*/
static x87_state *x87_alloc_state(x87_simulator *sim)
{
- x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
+ x87_state *res = OALLOC(&sim->obst, x87_state);
res->sim = sim;
return res;
-} /* x87_alloc_state */
+}
/**
* Clone a x87 state.
*res = *src;
return res;
-} /* x87_clone_state */
+}
/**
* Patch a virtual instruction into a x87 one and return
if (mode == mode_T) {
/* patch all Proj's */
- const ir_edge_t *edge;
-
foreach_out_edge(n, edge) {
ir_node *proj = get_edge_src_irn(edge);
if (is_Proj(proj)) {
} else if (mode_is_float(mode))
set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
return res;
-} /* x87_patch_insn */
+}
/**
* Returns the first Proj of a mode_T node having a given mode.
*/
static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
{
- const ir_edge_t *edge;
-
assert(get_irn_mode(n) == mode_T && "Need mode_T node");
foreach_out_edge(n, edge) {
}
return NULL;
-} /* get_irn_Proj_for_mode */
+}
/**
* Wrap the arch_* function here so we can check for errors.
{
const arch_register_t *res = arch_get_irn_register(irn);
- assert(res->reg_class->regs == ia32_vfp_regs);
+ assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
return res;
-} /* x87_get_irn_register */
+}
static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
int pos)
{
- const arch_register_t *res = arch_irn_get_register(irn, pos);
+ const arch_register_t *res = arch_get_irn_register_out(irn, pos);
- assert(res->reg_class->regs == ia32_vfp_regs);
+ assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
return res;
-} /* x87_irn_get_register */
+}
+
+static inline const arch_register_t *get_st_reg(int index)
+{
+ return &ia32_registers[REG_ST0 + index];
+}
/* -------------- x87 perm --------------- */
fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
- attr->x87[0] = &ia32_st_regs[pos];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(pos);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fxch);
x87_fxch(state, pos);
return fxch;
-} /* x87_fxch_shuffle */
+}
/**
* Calculate the necessary permutations to reach dst_state.
* Note that critical edges are removed here, so we need only
* a shuffle if the current block has only one successor.
*
- * @param sim the simulator handle
* @param block the current block
* @param state the current x87 stack state, might be modified
- * @param dst_block the destination block
* @param dst_state destination state
*
* @return state
*/
-static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
- x87_state *state, ir_node *dst_block,
- const x87_state *dst_state)
+static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
{
int i, n_cycles, k, ri;
unsigned cycles[4], all_mask;
char cycle_idx[4][8];
ir_node *fxch, *before, *after;
- (void) sim;
- (void) dst_block;
assert(state->depth == dst_state->depth);
/* Hmm: permutation needed */
DB((dbg, LEVEL_2, "\n%+F needs permutation: from\n", block));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
DB((dbg, LEVEL_2, " to\n"));
- DEBUG_ONLY(x87_dump_stack(dst_state));
+ DEBUG_ONLY(x87_dump_stack(dst_state);)
#ifdef DEBUG_libfirm
}
}
return state;
-} /* x87_shuffle */
+}
/**
* Create a fxch node before another node.
fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
- attr->x87[0] = &ia32_st_regs[pos];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(pos);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fxch);
sched_add_before(n, fxch);
DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fxch), attr->x87[0]->name, attr->x87[2]->name));
return fxch;
-} /* x87_create_fxch */
+}
/**
* Create a fpush before node n.
fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpush);
- attr->x87[0] = &ia32_st_regs[pos];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(pos);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fpush);
sched_add_before(n, fpush);
DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(fpush), attr->x87[0]->name, attr->x87[2]->name));
-} /* x87_create_fpush */
+}
/**
* Create a fpop before node n.
ia32_x87_attr_t *attr;
assert(num > 0);
- while (num > 0) {
+ do {
x87_pop(state);
if (ia32_cg_config.use_ffreep)
fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
else
fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpop);
- attr->x87[0] = &ia32_st_regs[0];
- attr->x87[1] = &ia32_st_regs[0];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(0);
+ attr->x87[1] = get_st_reg(0);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fpop);
sched_add_before(n, fpop);
DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
-
- --num;
- }
+ } while (--num > 0);
return fpop;
-} /* x87_create_fpop */
+}
/* --------------------------------- liveness ------------------------------------------ */
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
if (get_irn_mode(irn) == mode_T) {
- const ir_edge_t *edge;
-
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
}
}
return live;
-} /* vfp_liveness_transfer */
+}
/**
* Put all live virtual registers at the end of a block into a bitset.
*
* @param sim the simulator handle
- * @param lv the liveness information
* @param bl the block
*
* @return The live bitset at the end of this block
*/
static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
{
- int i;
vfp_liveness live = 0;
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
const be_lv_t *lv = sim->lv;
- be_lv_foreach(lv, block, be_lv_state_end, i) {
+ be_lv_foreach(lv, block, be_lv_state_end, node) {
const arch_register_t *reg;
- const ir_node *node = be_lv_get_irn(lv, block, i);
if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
}
return live;
-} /* vfp_liveness_end_of_block */
+}
/** get the register mask from an arch_register */
-#define REGMASK(reg) (1 << (arch_register_get_index(reg)))
+#define REGMASK(reg) (1 << (arch_register_get_index(reg)))
/**
* Return a bitset of argument registers which are live at the end of a node.
assert(idx < sim->n_idx);
return sim->live[idx] & ~kill;
-} /* vfp_live_args_after */
+}
/**
* Calculate the liveness for a whole block and cache it.
*
* @param sim the simulator handle
- * @param lv the liveness handle
* @param block the block
*/
static void update_liveness(x87_simulator *sim, ir_node *block)
{
vfp_liveness live = vfp_liveness_end_of_block(sim, block);
unsigned idx;
- ir_node *irn;
/* now iterate through the block backward and cache the results */
sched_foreach_reverse(block, irn) {
}
idx = get_irn_idx(block);
sim->live[idx] = live;
-} /* update_liveness */
+}
/**
* Returns true if a register is live in a set.
}
}
DB((dbg, LEVEL_2, "\n"));
-} /* vfp_dump_live */
+}
#endif /* DEBUG_libfirm */
/* --------------------------------- simulators ---------------------------------------- */
DB((dbg, LEVEL_1, ">>> %+F %s, %s -> %s\n", n,
arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
arch_register_get_name(out)));
- DEBUG_ONLY(vfp_dump_live(live));
+ DEBUG_ONLY(vfp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
op1_idx = x87_on_stack(state, reg_index_1);
assert(op1_idx >= 0);
- op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live);
+ op1_live_after = is_vfp_live(reg_index_1, live);
attr = get_ia32_x87_attr(n);
permuted = attr->attr.data.ins_permuted;
- if (reg_index_2 != REG_VFP_NOREG) {
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
assert(!permuted);
/* second operand is a vfp register */
op2_idx = x87_on_stack(state, reg_index_2);
assert(op2_idx >= 0);
- op2_live_after = is_vfp_live(arch_register_get_index(op2_reg), live);
+ op2_live_after = is_vfp_live(reg_index_2, live);
if (op2_live_after) {
/* Second operand is live. */
}
/* patch the operation */
- attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
- if (reg_index_2 != REG_VFP_NOREG) {
- attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
+ attr->x87[0] = op1_reg = get_st_reg(op1_idx);
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
+ attr->x87[1] = op2_reg = get_st_reg(op2_idx);
}
- attr->x87[2] = out = &ia32_st_regs[out_idx];
+ attr->x87[2] = out = get_st_reg(out_idx);
- if (reg_index_2 != REG_VFP_NOREG) {
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
arch_register_get_name(out)));
}
return NO_NODE_ADDED;
-} /* sim_binop */
+}
/**
* Simulate a virtual Unop.
*/
static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
{
- int op1_idx;
x87_simulator *sim = state->sim;
- const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, UNOP_IDX));
+ const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
const arch_register_t *out = x87_get_irn_register(n);
ia32_x87_attr_t *attr;
unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
- DEBUG_ONLY(vfp_dump_live(live));
+ DEBUG_ONLY(vfp_dump_live(live);)
- op1_idx = x87_on_stack(state, arch_register_get_index(op1));
+ int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* push the operand here */
- x87_create_fpush(state, n, op1_idx, UNOP_IDX);
+ x87_create_fpush(state, n, op1_idx, 0);
op1_idx = 0;
- }
- else {
+ } else {
/* operand is dead, bring it to tos */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
- op1_idx = 0;
}
}
x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
attr = get_ia32_x87_attr(n);
- attr->x87[0] = op1 = &ia32_st_regs[0];
- attr->x87[2] = out = &ia32_st_regs[0];
+ attr->x87[0] = op1 = get_st_reg(0);
+ attr->x87[2] = out = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
return NO_NODE_ADDED;
-} /* sim_unop */
+}
/**
* Simulate a virtual Load instruction.
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
assert(out == x87_irn_get_register(n, res_pos));
attr = get_ia32_x87_attr(n);
- attr->x87[2] = out = &ia32_st_regs[0];
+ attr->x87[2] = out = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
return NO_NODE_ADDED;
-} /* sim_load */
+}
/**
* Rewire all users of @p old_val to @new_val iff they are scheduled after @p store.
*/
static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
{
- const ir_edge_t *edge, *ne;
-
- foreach_out_edge_safe(old_val, edge, ne) {
+ foreach_out_edge_safe(old_val, edge) {
ir_node *user = get_edge_src_irn(edge);
if (! user || user == store)
}
}
}
-} /* collect_and_rewire_users */
+}
/**
* Simulate a virtual Store.
Note that we cannot test on mode_E, because floats might be 96bit ...
*/
if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
- if (depth < N_x87_REGS) {
+ if (depth < N_ia32_st_REGS) {
/* ok, we have a free register: push + fstp */
x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
x87_pop(state);
x87_patch_insn(n, op_p);
} else {
ir_node *vfld, *mem, *block, *rproj, *mproj;
- ir_graph *irg;
+ ir_graph *irg = get_irn_irg(n);
+ ir_node *nomem = get_irg_no_mem(irg);
/* stack full here: need fstp + load */
x87_pop(state);
x87_patch_insn(n, op_p);
block = get_nodes_block(n);
- vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), new_NoMem(), get_ia32_ls_mode(n));
+ vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n));
/* copy all attributes */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
arch_set_irn_register(rproj, op2);
/* reroute all former users of the store memory to the load memory */
- irg = get_irn_irg(n);
- edges_reroute(mem, mproj, irg);
+ edges_reroute(mem, mproj);
/* set the memory input of the load to the store memory */
set_irn_n(vfld, n_ia32_vfld_mem, mem);
}
attr = get_ia32_x87_attr(n);
- attr->x87[1] = op2 = &ia32_st_regs[0];
+ attr->x87[1] = op2 = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
return insn;
-} /* sim_store */
+}
#define _GEN_BINOP(op, rev) \
static int sim_##op(x87_state *state, ir_node *n) { \
}
#define GEN_BINOP(op) _GEN_BINOP(op, op)
-#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
+#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
#define GEN_LOAD(op) \
static int sim_##op(x87_state *state, ir_node *n) { \
x87_patch_insn(n, op_ia32_fisttp);
attr = get_ia32_x87_attr(n);
- attr->x87[1] = op2 = &ia32_st_regs[0];
+ attr->x87[1] = op2 = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
return NO_NODE_ADDED;
-} /* sim_fisttp */
+}
/**
* Simulate a virtual FtstFnstsw.
unsigned live = vfp_live_args_after(sim, n, 0);
DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
- DEBUG_ONLY(vfp_dump_live(live));
+ DEBUG_ONLY(vfp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
assert(op1_idx >= 0);
if (op1_idx != 0) {
/* patch the operation */
x87_patch_insn(n, op_ia32_FtstFnstsw);
- reg1 = &ia32_st_regs[op1_idx];
+ reg1 = get_st_reg(op1_idx);
attr->x87[0] = reg1;
attr->x87[1] = NULL;
attr->x87[2] = NULL;
x87_create_fpop(state, sched_next(n), 1);
return NO_NODE_ADDED;
-} /* sim_FtstFnstsw */
+}
/**
* Simulate a Fucom
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
arch_register_get_name(op1), arch_register_get_name(op2)));
- DEBUG_ONLY(vfp_dump_live(live));
+ DEBUG_ONLY(vfp_dump_live(live);)
DB((dbg, LEVEL_1, "Stack before: "));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
op1_idx = x87_on_stack(state, reg_index_1);
assert(op1_idx >= 0);
/* BEWARE: check for comp a,a cases, they might happen */
- if (reg_index_2 != REG_VFP_NOREG) {
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
/* second operand is a vfp register */
op2_idx = x87_on_stack(state, reg_index_2);
assert(op2_idx >= 0);
case 0: dst = op_ia32_FucomFnstsw; break;
case 1: dst = op_ia32_FucompFnstsw; break;
case 2: dst = op_ia32_FucomppFnstsw; break;
- default: panic("invalid popcount in sim_Fucom");
+ default: panic("invalid popcount");
}
for (i = 0; i < pops; ++i) {
x87_pop(state);
x87_create_fpop(state, sched_next(n), 1);
break;
- default: panic("invalid popcount in sim_Fucom");
+ default: panic("invalid popcount");
}
} else {
- panic("invalid operation %+F in sim_FucomFnstsw", n);
+ panic("invalid operation %+F", n);
}
x87_patch_insn(n, dst);
op2_idx = tmp;
}
- op1 = &ia32_st_regs[op1_idx];
+ op1 = get_st_reg(op1_idx);
attr->x87[0] = op1;
if (op2_idx >= 0) {
- op2 = &ia32_st_regs[op2_idx];
+ op2 = get_st_reg(op2_idx);
attr->x87[1] = op2;
}
attr->x87[2] = NULL;
}
return NO_NODE_ADDED;
-} /* sim_Fucom */
+}
/**
* Simulate a Keep.
}
DB((dbg, LEVEL_1, "Stack after: "));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
return NO_NODE_ADDED;
-} /* sim_Keep */
+}
/**
* Keep the given node alive by adding a be_Keep.
x87_push(state, arch_register_get_index(out), res);
attr = get_ia32_x87_attr(res);
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[2] = get_st_reg(0);
} else {
int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
x87_push(state, arch_register_get_index(out), res);
attr = get_ia32_x87_attr(res);
- attr->x87[0] = &ia32_st_regs[op1_idx];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(op1_idx);
+ attr->x87[2] = get_st_reg(0);
}
arch_set_irn_register(res, out);
return res;
-} /* create_Copy */
+}
/**
* Simulate a be_Copy.
int op1_idx, out_idx;
unsigned live;
- cls = arch_get_irn_reg_class_out(n);
- if (cls->regs != ia32_vfp_regs)
+ cls = arch_get_irn_reg_class(n);
+ if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
return 0;
- pred = get_irn_n(n, 0);
+ pred = be_get_Copy_op(n);
out = x87_get_irn_register(n);
op1 = x87_get_irn_register(pred);
live = vfp_live_args_after(state->sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
arch_register_get_name(op1), arch_register_get_name(out)));
- DEBUG_ONLY(vfp_dump_live(live));
+ DEBUG_ONLY(vfp_dump_live(live);)
op1_idx = x87_on_stack(state, arch_register_get_index(op1));
if (is_vfp_live(arch_register_get_index(op1), live)) {
- ir_node *pred = get_irn_n(n, 0);
-
/* Operand is still live, a real copy. We need here an fpush that can
hold a a register, so use the fpushCopy or recreate constants */
node = create_Copy(state, n);
if (out_idx >= 0 && out_idx != op1_idx) {
/* Matze: out already on stack? how can this happen? */
- panic("invalid stack state in x87 simulator");
+ panic("invalid stack state");
#if 0
/* op1 must be killed and placed where out is */
/* best case, simple remove and rename */
x87_patch_insn(n, op_ia32_Pop);
attr = get_ia32_x87_attr(n);
- attr->x87[0] = op1 = &ia32_st_regs[0];
+ attr->x87[0] = op1 = get_st_reg(0);
x87_pop(state);
x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
}
x87_patch_insn(n, op_ia32_Pop);
attr = get_ia32_x87_attr(n);
- attr->x87[0] = op1 = &ia32_st_regs[out_idx];
+ attr->x87[0] = op1 = get_st_reg(out_idx);
x87_pop(state);
x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
#endif
} else {
/* just a virtual copy */
- x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
+ x87_set_st(state, arch_register_get_index(out), pred, op1_idx);
/* don't remove the node to keep the verifier quiet :),
the emitter won't emit any code for the node */
#if 0
sched_remove(n);
DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
- exchange(n, get_unop_op(n));
+ exchange(n, pred);
#endif
}
}
return NO_NODE_ADDED;
-} /* sim_Copy */
+}
/**
* Returns the vf0 result Proj of a Call.
*/
static ir_node *get_call_result_proj(ir_node *call)
{
- const ir_edge_t *edge;
-
/* search the result proj */
foreach_out_edge(call, edge) {
ir_node *proj = get_edge_src_irn(edge);
}
return NULL;
-} /* get_call_result_proj */
+}
+
+static int sim_Asm(x87_state *const state, ir_node *const n)
+{
+ (void)state;
+
+ for (size_t i = get_irn_arity(n); i-- != 0;) {
+ arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
+ panic("cannot handle %+F with x87 constraints", n);
+ }
+
+ for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
+ arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
+ panic("cannot handle %+F with x87 constraints", n);
+ }
+
+ return NO_NODE_ADDED;
+}
/**
* Simulate a ia32_Call.
end_call:
DB((dbg, LEVEL_1, "Stack after: "));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
return NO_NODE_ADDED;
-} /* sim_Call */
+}
/**
* Simulate a be_Return.
*/
static int sim_Return(x87_state *state, ir_node *n)
{
- int n_res = be_Return_get_n_rets(n);
- int i, n_float_res = 0;
-
+#ifdef DEBUG_libfirm
/* only floating point return values must reside on stack */
- for (i = 0; i < n_res; ++i) {
- ir_node *res = get_irn_n(n, be_pos_Return_val + i);
-
+ int n_float_res = 0;
+ int const n_res = be_Return_get_n_rets(n);
+ for (int i = 0; i < n_res; ++i) {
+ ir_node *const res = get_irn_n(n, n_be_Return_val + i);
if (mode_is_float(get_irn_mode(res)))
++n_float_res;
}
assert(x87_get_depth(state) == n_float_res);
+#endif
/* pop them virtually */
- for (i = n_float_res - 1; i >= 0; --i)
- x87_pop(state);
-
+ x87_emms(state);
return NO_NODE_ADDED;
-} /* sim_Return */
-
-typedef struct perm_data_t {
- const arch_register_t *in;
- const arch_register_t *out;
-} perm_data_t;
+}
/**
* Simulate a be_Perm.
*/
static int sim_Perm(x87_state *state, ir_node *irn)
{
- int i, n;
- ir_node *pred = get_irn_n(irn, 0);
- int *stack_pos;
- const ir_edge_t *edge;
+ int i, n;
+ ir_node *pred = get_irn_n(irn, 0);
+ int *stack_pos;
/* handle only floating point Perms */
if (! mode_is_float(get_irn_mode(pred)))
DB((dbg, LEVEL_1, "<<< %+F\n", irn));
return NO_NODE_ADDED;
-} /* sim_Perm */
+}
/**
* Kill any dead registers at block start by popping them from the stack.
*
- * @param sim the simulator handle
- * @param block the current block
- * @param start_state the x87 state at the begin of the block
- *
- * @return the x87 state after dead register killed
+ * @param sim the simulator handle
+ * @param block the current block
+ * @param state the x87 state at the begin of the block
*/
-static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
+static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
{
- x87_state *state = start_state;
ir_node *first_insn = sched_first(block);
ir_node *keep = NULL;
unsigned live = vfp_live_args_after(sim, block, 0);
}
if (kill_mask) {
- /* create a new state, will be changed */
- state = x87_clone_state(sim, state);
-
DB((dbg, LEVEL_1, "Killing deads:\n"));
- DEBUG_ONLY(vfp_dump_live(live));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(vfp_dump_live(live);)
+ DEBUG_ONLY(x87_dump_stack(state);)
if (kill_mask != 0 && live == 0) {
/* special case: kill all registers */
sched_add_before(first_insn, keep);
keep_alive(keep);
x87_emms(state);
- return state;
+ return;
}
}
/* now kill registers */
}
keep_alive(keep);
}
- return state;
-} /* x87_kill_deads */
+}
/**
* Run a simulation and fix all virtual instructions for a block.
ir_node *n, *next;
blk_state *bl_state = x87_get_bl_state(sim, block);
x87_state *state = bl_state->begin;
- const ir_edge_t *edge;
ir_node *start_block;
assert(state != NULL);
DB((dbg, LEVEL_1, "Simulate %+F\n", block));
DB((dbg, LEVEL_2, "State at Block begin:\n "));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
- /* at block begin, kill all dead registers */
- state = x87_kill_deads(sim, block, state);
/* create a new state, will be changed */
state = x87_clone_state(sim, state);
+ /* at block begin, kill all dead registers */
+ x87_kill_deads(sim, block, state);
/* beware, n might change */
for (n = sched_first(block); !sched_is_end(n); n = next) {
start_block = get_irg_start_block(get_irn_irg(block));
- DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state));
+ DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state);)
/* check if the state must be shuffled */
foreach_block_succ(block, edge) {
if (succ_state->begin == NULL) {
DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
- DEBUG_ONLY(x87_dump_stack(state));
+ DEBUG_ONLY(x87_dump_stack(state);)
succ_state->begin = state;
waitq_put(sim->worklist, succ);
If the successor has more than one possible input, then it must
be the only one.
*/
- x87_shuffle(sim, block, state, succ, succ_state->begin);
+ x87_shuffle(block, state, succ_state->begin);
}
}
bl_state->end = state;
-} /* x87_simulate_block */
+}
/**
* Register a simulator function.
{
assert(op->ops.generic == NULL);
op->ops.generic = (op_func) func;
-} /* register_sim */
+}
/**
* Create a new x87 simulator.
obstack_init(&sim->obst);
sim->blk_states = pmap_create();
sim->n_idx = get_irg_last_idx(irg);
- sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
+ sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
DB((dbg, LEVEL_1, "--------------------------------\n"
"x87 Simulator started for %+F\n", irg));
/* set the generic function pointer of instruction we must simulate */
- clear_irp_opcodes_generic_func();
+ ir_clear_opcodes_generic_func();
+ register_sim(op_ia32_Asm, sim_Asm);
register_sim(op_ia32_Call, sim_Call);
register_sim(op_ia32_vfld, sim_fld);
register_sim(op_ia32_vfild, sim_fild);
register_sim(op_be_Return, sim_Return);
register_sim(op_be_Perm, sim_Perm);
register_sim(op_be_Keep, sim_Keep);
-} /* x87_init_simulator */
+}
/**
* Destroy a x87 simulator.
pmap_destroy(sim->blk_states);
obstack_free(&sim->obst, NULL);
DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
-} /* x87_destroy_simulator */
+}
/**
* Pre-block walker: calculate the liveness information for the block
*/
static void update_liveness_walker(ir_node *block, void *data)
{
- x87_simulator *sim = data;
+ x87_simulator *sim = (x87_simulator*)data;
update_liveness(sim, block);
-} /* update_liveness_walker */
+}
/*
* Run a simulation and fix all virtual instructions for a graph.
* Replaces all virtual floating point instructions and registers
* by real ones.
*/
-void x87_simulate_graph(ir_graph *irg)
+void ia32_x87_simulate_graph(ir_graph *irg)
{
/* TODO improve code quality (less executed fxch) by using execfreqs */
sim.worklist = new_waitq();
waitq_put(sim.worklist, start_block);
- be_assure_liveness(irg);
+ be_assure_live_sets(irg);
sim.lv = be_get_irg_liveness(irg);
- be_liveness_assure_sets(sim.lv);
/* Calculate the liveness for all nodes. We must precalculate this info,
* because the simulator adds new nodes (possible before Phi nodes) which
/* iterate */
do {
- block = waitq_get(sim.worklist);
+ block = (ir_node*)waitq_get(sim.worklist);
x87_simulate_block(&sim, block);
} while (! waitq_empty(sim.worklist));
/* kill it */
del_waitq(sim.worklist);
x87_destroy_simulator(&sim);
-} /* x87_simulate_graph */
+}
/* Initializes the x87 simulator. */
void ia32_init_x87(void)
{
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
-} /* ia32_init_x87 */
+}
projects / libfirm / blobdiff