vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
waitq *worklist; /**< Worklist of blocks that must be processed. */
- ia32_isa_t *isa; /**< the ISA object */
};
/**
return state->depth;
}
+static st_entry *x87_get_entry(x87_state *const state, int const pos)
+{
+ assert(0 <= pos && pos < state->depth);
+ return &state->st[MASK_TOS(state->tos + pos)];
+}
+
/**
* Return the virtual register index at st(pos).
*
*/
static int x87_get_st_reg(const x87_state *state, int pos)
{
- assert(pos < state->depth);
- return state->st[MASK_TOS(state->tos + pos)].reg_idx;
+ return x87_get_entry((x87_state*)state, pos)->reg_idx;
}
#ifdef DEBUG_libfirm
-/**
- * Return the node at st(pos).
- *
- * @param state the x87 state
- * @param pos a stack position
- *
- * @return the IR node that produced the value at st(pos)
- */
-static ir_node *x87_get_st_node(const x87_state *state, int pos)
-{
- assert(pos < state->depth);
- return state->st[MASK_TOS(state->tos + pos)].node;
-}
-
/**
* Dump the stack for debugging.
*
*/
static void x87_dump_stack(const x87_state *state)
{
- int i;
-
- for (i = state->depth - 1; i >= 0; --i) {
- DB((dbg, LEVEL_2, "vf%d(%+F) ", x87_get_st_reg(state, i),
- x87_get_st_node(state, i)));
+ for (int i = state->depth; i-- != 0;) {
+ st_entry const *const entry = x87_get_entry((x87_state*)state, i);
+ DB((dbg, LEVEL_2, "vf%d(%+F) ", entry->reg_idx, entry->node));
}
DB((dbg, LEVEL_2, "<-- TOS\n"));
}
*/
static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
{
- assert(0 < state->depth);
- state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
- state->st[MASK_TOS(state->tos + pos)].node = node;
+ st_entry *const entry = x87_get_entry(state, pos);
+ entry->reg_idx = reg_idx;
+ entry->node = node;
DB((dbg, LEVEL_2, "After SET_REG: "));
DEBUG_ONLY(x87_dump_stack(state);)
*/
static void x87_fxch(x87_state *state, int pos)
{
- st_entry entry;
- assert(pos < state->depth);
-
- entry = state->st[MASK_TOS(state->tos + pos)];
- state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
- state->st[MASK_TOS(state->tos)] = entry;
+ st_entry *const a = x87_get_entry(state, pos);
+ st_entry *const b = x87_get_entry(state, 0);
+ st_entry const t = *a;
+ *a = *b;
+ *b = t;
DB((dbg, LEVEL_2, "After FXCH: "));
DEBUG_ONLY(x87_dump_stack(state);)
*/
static int x87_on_stack(const x87_state *state, int reg_idx)
{
- int i, tos = state->tos;
-
- for (i = 0; i < state->depth; ++i)
- if (state->st[MASK_TOS(tos + i)].reg_idx == reg_idx)
+ for (int i = 0; i < state->depth; ++i) {
+ if (x87_get_st_reg(state, i) == reg_idx)
return i;
+ }
return -1;
}
++state->depth;
state->tos = MASK_TOS(state->tos - 1);
- state->st[state->tos].reg_idx = reg_idx;
- state->st[state->tos].node = node;
+ st_entry *const entry = x87_get_entry(state, 0);
+ entry->reg_idx = reg_idx;
+ entry->node = node;
DB((dbg, LEVEL_2, "After PUSH: ")); DEBUG_ONLY(x87_dump_stack(state);)
}
* @param state the x87 state
* @param reg_idx the register vfp index
* @param node the node that produces the value of the vfp register
- * @param dbl_push if != 0 double pushes are allowed
*/
static void x87_push(x87_state *state, int reg_idx, ir_node *node)
{
*/
static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
{
- blk_state *res = pmap_get(sim->blk_states, block);
+ blk_state *res = pmap_get(blk_state, sim->blk_states, block);
if (res == NULL) {
res = OALLOC(&sim->obst, blk_state);
if (mode == mode_T) {
/* patch all Proj's */
- const ir_edge_t *edge;
-
foreach_out_edge(n, edge) {
ir_node *proj = get_edge_src_irn(edge);
if (is_Proj(proj)) {
*/
static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
{
- const ir_edge_t *edge;
-
assert(get_irn_mode(n) == mode_T && "Need mode_T node");
foreach_out_edge(n, edge) {
* Note that critical edges are removed here, so we need only
* a shuffle if the current block has only one successor.
*
- * @param sim the simulator handle
* @param block the current block
* @param state the current x87 stack state, might be modified
- * @param dst_block the destination block
* @param dst_state destination state
*
* @return state
*/
-static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
- x87_state *state, ir_node *dst_block,
- const x87_state *dst_state)
+static x87_state *x87_shuffle(ir_node *block, x87_state *state, const x87_state *dst_state)
{
int i, n_cycles, k, ri;
unsigned cycles[4], all_mask;
char cycle_idx[4][8];
ir_node *fxch, *before, *after;
- (void) sim;
- (void) dst_block;
assert(state->depth == dst_state->depth);
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
if (get_irn_mode(irn) == mode_T) {
- const ir_edge_t *edge;
-
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
* Put all live virtual registers at the end of a block into a bitset.
*
* @param sim the simulator handle
- * @param lv the liveness information
* @param bl the block
*
* @return The live bitset at the end of this block
*/
static vfp_liveness vfp_liveness_end_of_block(x87_simulator *sim, const ir_node *block)
{
- int i;
vfp_liveness live = 0;
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
const be_lv_t *lv = sim->lv;
- be_lv_foreach(lv, block, be_lv_state_end, i) {
+ be_lv_foreach(lv, block, be_lv_state_end, node) {
const arch_register_t *reg;
- const ir_node *node = be_lv_get_irn(lv, block, i);
if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
* Calculate the liveness for a whole block and cache it.
*
* @param sim the simulator handle
- * @param lv the liveness handle
* @param block the block
*/
static void update_liveness(x87_simulator *sim, ir_node *block)
{
vfp_liveness live = vfp_liveness_end_of_block(sim, block);
unsigned idx;
- ir_node *irn;
/* now iterate through the block backward and cache the results */
sched_foreach_reverse(block, irn) {
*/
static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
{
- int op1_idx;
x87_simulator *sim = state->sim;
const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
const arch_register_t *out = x87_get_irn_register(n);
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, out->name));
DEBUG_ONLY(vfp_dump_live(live);)
- op1_idx = x87_on_stack(state, arch_register_get_index(op1));
+ int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* push the operand here */
x87_create_fpush(state, n, op1_idx, 0);
op1_idx = 0;
- }
- else {
+ } else {
/* operand is dead, bring it to tos */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
- op1_idx = 0;
}
}
*/
static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
{
- const ir_edge_t *edge, *ne;
-
- foreach_out_edge_safe(old_val, edge, ne) {
+ foreach_out_edge_safe(old_val, edge) {
ir_node *user = get_edge_src_irn(edge);
if (! user || user == store)
case 0: dst = op_ia32_FucomFnstsw; break;
case 1: dst = op_ia32_FucompFnstsw; break;
case 2: dst = op_ia32_FucomppFnstsw; break;
- default: panic("invalid popcount in sim_Fucom");
+ default: panic("invalid popcount");
}
for (i = 0; i < pops; ++i) {
x87_pop(state);
x87_create_fpop(state, sched_next(n), 1);
break;
- default: panic("invalid popcount in sim_Fucom");
+ default: panic("invalid popcount");
}
} else {
- panic("invalid operation %+F in sim_FucomFnstsw", n);
+ panic("invalid operation %+F", n);
}
x87_patch_insn(n, dst);
if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
return 0;
- pred = get_irn_n(n, 0);
+ pred = be_get_Copy_op(n);
out = x87_get_irn_register(n);
op1 = x87_get_irn_register(pred);
live = vfp_live_args_after(state->sim, n, REGMASK(out));
if (out_idx >= 0 && out_idx != op1_idx) {
/* Matze: out already on stack? how can this happen? */
- panic("invalid stack state in x87 simulator");
+ panic("invalid stack state");
#if 0
/* op1 must be killed and placed where out is */
#endif
} else {
/* just a virtual copy */
- x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
+ x87_set_st(state, arch_register_get_index(out), pred, op1_idx);
/* don't remove the node to keep the verifier quiet :),
the emitter won't emit any code for the node */
#if 0
sched_remove(n);
DB((dbg, LEVEL_1, "<<< KILLED %s\n", get_irn_opname(n)));
- exchange(n, get_unop_op(n));
+ exchange(n, pred);
#endif
}
}
*/
static ir_node *get_call_result_proj(ir_node *call)
{
- const ir_edge_t *edge;
-
/* search the result proj */
foreach_out_edge(call, edge) {
ir_node *proj = get_edge_src_irn(edge);
return NULL;
}
+static int sim_Asm(x87_state *const state, ir_node *const n)
+{
+ (void)state;
+
+ for (size_t i = get_irn_arity(n); i-- != 0;) {
+ arch_register_req_t const *const req = arch_get_irn_register_req_in(n, i);
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
+ panic("cannot handle %+F with x87 constraints", n);
+ }
+
+ for (size_t i = arch_get_irn_n_outs(n); i-- != 0;) {
+ arch_register_req_t const *const req = arch_get_irn_register_req_out(n, i);
+ if (req->cls == &ia32_reg_classes[CLASS_ia32_vfp])
+ panic("cannot handle %+F with x87 constraints", n);
+ }
+
+ return NO_NODE_ADDED;
+}
+
/**
* Simulate a ia32_Call.
*
*/
static int sim_Return(x87_state *state, ir_node *n)
{
- int n_res = be_Return_get_n_rets(n);
- int i, n_float_res = 0;
-
+#ifdef DEBUG_libfirm
/* only floating point return values must reside on stack */
- for (i = 0; i < n_res; ++i) {
- ir_node *res = get_irn_n(n, n_be_Return_val + i);
-
+ int n_float_res = 0;
+ int const n_res = be_Return_get_n_rets(n);
+ for (int i = 0; i < n_res; ++i) {
+ ir_node *const res = get_irn_n(n, n_be_Return_val + i);
if (mode_is_float(get_irn_mode(res)))
++n_float_res;
}
assert(x87_get_depth(state) == n_float_res);
+#endif
/* pop them virtually */
- for (i = n_float_res - 1; i >= 0; --i)
- x87_pop(state);
-
+ x87_emms(state);
return NO_NODE_ADDED;
}
-typedef struct perm_data_t {
- const arch_register_t *in;
- const arch_register_t *out;
-} perm_data_t;
-
/**
* Simulate a be_Perm.
*
*/
static int sim_Perm(x87_state *state, ir_node *irn)
{
- int i, n;
- ir_node *pred = get_irn_n(irn, 0);
- int *stack_pos;
- const ir_edge_t *edge;
+ int i, n;
+ ir_node *pred = get_irn_n(irn, 0);
+ int *stack_pos;
/* handle only floating point Perms */
if (! mode_is_float(get_irn_mode(pred)))
/**
* Kill any dead registers at block start by popping them from the stack.
*
- * @param sim the simulator handle
- * @param block the current block
- * @param start_state the x87 state at the begin of the block
- *
- * @return the x87 state after dead register killed
+ * @param sim the simulator handle
+ * @param block the current block
+ * @param state the x87 state at the begin of the block
*/
-static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
+static void x87_kill_deads(x87_simulator *const sim, ir_node *const block, x87_state *const state)
{
- x87_state *state = start_state;
ir_node *first_insn = sched_first(block);
ir_node *keep = NULL;
unsigned live = vfp_live_args_after(sim, block, 0);
}
if (kill_mask) {
- /* create a new state, will be changed */
- state = x87_clone_state(sim, state);
-
DB((dbg, LEVEL_1, "Killing deads:\n"));
DEBUG_ONLY(vfp_dump_live(live);)
DEBUG_ONLY(x87_dump_stack(state);)
sched_add_before(first_insn, keep);
keep_alive(keep);
x87_emms(state);
- return state;
+ return;
}
}
/* now kill registers */
}
keep_alive(keep);
}
- return state;
}
/**
ir_node *n, *next;
blk_state *bl_state = x87_get_bl_state(sim, block);
x87_state *state = bl_state->begin;
- const ir_edge_t *edge;
ir_node *start_block;
assert(state != NULL);
DB((dbg, LEVEL_2, "State at Block begin:\n "));
DEBUG_ONLY(x87_dump_stack(state);)
- /* at block begin, kill all dead registers */
- state = x87_kill_deads(sim, block, state);
/* create a new state, will be changed */
state = x87_clone_state(sim, state);
+ /* at block begin, kill all dead registers */
+ x87_kill_deads(sim, block, state);
/* beware, n might change */
for (n = sched_first(block); !sched_is_end(n); n = next) {
If the successor has more than one possible input, then it must
be the only one.
*/
- x87_shuffle(sim, block, state, succ, succ_state->begin);
+ x87_shuffle(block, state, succ_state->begin);
}
}
bl_state->end = state;
"x87 Simulator started for %+F\n", irg));
/* set the generic function pointer of instruction we must simulate */
- clear_irp_opcodes_generic_func();
+ ir_clear_opcodes_generic_func();
+ register_sim(op_ia32_Asm, sim_Asm);
register_sim(op_ia32_Call, sim_Call);
register_sim(op_ia32_vfld, sim_fld);
register_sim(op_ia32_vfild, sim_fild);
sim.worklist = new_waitq();
waitq_put(sim.worklist, start_block);
- be_assure_liveness(irg);
+ be_assure_live_sets(irg);
sim.lv = be_get_irg_liveness(irg);
- be_liveness_assure_sets(sim.lv);
/* Calculate the liveness for all nodes. We must precalculate this info,
* because the simulator adds new nodes (possible before Phi nodes) which
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