/*
- * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2010 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
#include "error.h"
#include "../belive_t.h"
-#include "../besched_t.h"
-#include "../benode_t.h"
+#include "../besched.h"
+#include "../benode.h"
#include "bearch_ia32_t.h"
#include "ia32_new_nodes.h"
#include "gen_ia32_new_nodes.h"
#include "ia32_x87.h"
#include "ia32_architecture.h"
-#define N_x87_REGS 8
-
-/* the unop index */
-#define UNOP_IDX 0
-
-#define MASK_TOS(x) ((x) & (N_x87_REGS - 1))
+#define MASK_TOS(x) ((x) & (N_ia32_st_REGS - 1))
/** the debug handle */
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
/* Forward declaration. */
-typedef struct _x87_simulator x87_simulator;
+typedef struct x87_simulator x87_simulator;
/**
* An exchange template.
* their opcodes!
* Further, x87 supports inverse instructions, so we can handle them.
*/
-typedef struct _exchange_tmpl {
+typedef struct exchange_tmpl {
ir_op *normal_op; /**< the normal one */
ir_op *reverse_op; /**< the reverse one if exists */
ir_op *normal_pop_op; /**< the normal one with tos pop */
/**
* An entry on the simulated x87 stack.
*/
-typedef struct _st_entry {
+typedef struct st_entry {
int reg_idx; /**< the virtual register index of this stack value */
ir_node *node; /**< the node that produced this value */
} st_entry;
/**
* The x87 state.
*/
-typedef struct _x87_state {
- st_entry st[N_x87_REGS]; /**< the register stack */
- int depth; /**< the current stack depth */
- int tos; /**< position of the tos */
- x87_simulator *sim; /**< The simulator. */
+typedef struct x87_state {
+ st_entry st[N_ia32_st_REGS]; /**< the register stack */
+ int depth; /**< the current stack depth */
+ int tos; /**< position of the tos */
+ x87_simulator *sim; /**< The simulator. */
} x87_state;
/** An empty state, used for blocks without fp instructions. */
static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
static x87_state *empty = (x87_state *)&_empty;
+/**
+ * Return values of the instruction simulator functions.
+ */
enum {
- NO_NODE_ADDED = 0, /**< No node was added. */
- NODE_ADDED = 1 /**< A node was added by the simulator in the schedule. */
+ NO_NODE_ADDED = 0, /**< No node that needs simulation was added. */
+ NODE_ADDED = 1 /**< A node that must be simulated was added by the simulator
+ in the schedule AFTER the current node. */
};
/**
* @param state the x87 state
* @param n the node to be simulated
*
- * @return NODE_ADDED if a node was added AFTER n in schedule,
- * NO_NODE_ADDED else
+ * @return NODE_ADDED if a node was added AFTER n in schedule that MUST be
+ * simulated further
+ * NO_NODE_ADDED otherwise
*/
typedef int (*sim_func)(x87_state *state, ir_node *n);
/**
* A block state: Every block has a x87 state at the beginning and at the end.
*/
-typedef struct _blk_state {
+typedef struct blk_state {
x87_state *begin; /**< state at the begin or NULL if not assigned */
x87_state *end; /**< state at the end or NULL if not assigned */
} blk_state;
-#define PTR_TO_BLKSTATE(p) ((blk_state *)(p))
+#define PTR_TO_BLKSTATE(p) ((blk_state *)(p))
/** liveness bitset for vfp registers. */
typedef unsigned char vfp_liveness;
/**
* The x87 simulator.
*/
-struct _x87_simulator {
+struct x87_simulator {
struct obstack obst; /**< An obstack for fast allocating. */
pmap *blk_states; /**< Map blocks to states. */
be_lv_t *lv; /**< intrablock liveness. */
state->st[MASK_TOS(state->tos + pos)] = state->st[MASK_TOS(state->tos)];
state->st[MASK_TOS(state->tos)] = entry;
- DB((dbg, LEVEL_2, "After FXCH: ")); DEBUG_ONLY(x87_dump_stack(state));
+ DB((dbg, LEVEL_2, "After FXCH: "));
+ DEBUG_ONLY(x87_dump_stack(state));
} /* x87_fxch */
/**
*/
static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
{
- assert(state->depth < N_x87_REGS && "stack overrun");
+ assert(state->depth < N_ia32_st_REGS && "stack overrun");
++state->depth;
state->tos = MASK_TOS(state->tos - 1);
pmap_entry *entry = pmap_find(sim->blk_states, block);
if (! entry) {
- blk_state *bl_state = obstack_alloc(&sim->obst, sizeof(*bl_state));
+ blk_state *bl_state = OALLOC(&sim->obst, blk_state);
bl_state->begin = NULL;
bl_state->end = NULL;
*/
static x87_state *x87_alloc_state(x87_simulator *sim)
{
- x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
+ x87_state *res = OALLOC(&sim->obst, x87_state);
res->sim = sim;
return res;
{
x87_state *res = x87_alloc_state(sim);
- memcpy(res, src, sizeof(*res));
+ *res = *src;
return res;
} /* x87_clone_state */
mode = get_irn_mode(proj);
if (mode_is_float(mode)) {
res = proj;
- set_irn_mode(proj, mode_E);
+ set_irn_mode(proj, ia32_reg_classes[CLASS_ia32_st].mode);
}
}
}
} else if (mode_is_float(mode))
- set_irn_mode(n, mode_E);
+ set_irn_mode(n, ia32_reg_classes[CLASS_ia32_st].mode);
return res;
} /* x87_patch_insn */
/**
* Wrap the arch_* function here so we can check for errors.
*/
-static INLINE const arch_register_t *x87_get_irn_register(const ir_node *irn)
+static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
{
const arch_register_t *res = arch_get_irn_register(irn);
- assert(res->reg_class->regs == ia32_vfp_regs);
+ assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
return res;
} /* x87_get_irn_register */
+static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
+ int pos)
+{
+ const arch_register_t *res = arch_get_irn_register_out(irn, pos);
+
+ assert(res->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]);
+ return res;
+} /* x87_irn_get_register */
+
+static inline const arch_register_t *get_st_reg(int index)
+{
+ return &ia32_registers[REG_ST0 + index];
+}
+
/* -------------- x87 perm --------------- */
/**
ir_node *fxch;
ia32_x87_attr_t *attr;
- fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block);
+ fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
- attr->x87[0] = &ia32_st_regs[pos];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(pos);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fxch);
{
ir_node *fxch;
ia32_x87_attr_t *attr;
- ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
x87_fxch(state, pos);
- fxch = new_rd_ia32_fxch(NULL, irg, block);
+ fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
- attr->x87[0] = &ia32_st_regs[pos];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(pos);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fxch);
x87_push_dbl(state, arch_register_get_index(out), pred);
- fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpush);
- attr->x87[0] = &ia32_st_regs[pos];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(pos);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fpush);
sched_add_before(n, fpush);
ia32_x87_attr_t *attr;
assert(num > 0);
- while (num > 0) {
+ do {
x87_pop(state);
if (ia32_cg_config.use_ffreep)
- fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
else
- fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpop);
- attr->x87[0] = &ia32_st_regs[0];
- attr->x87[1] = &ia32_st_regs[0];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(0);
+ attr->x87[1] = get_st_reg(0);
+ attr->x87[2] = get_st_reg(0);
keep_alive(fpop);
sched_add_before(n, fpop);
DB((dbg, LEVEL_1, "<<< %s %s\n", get_irn_opname(fpop), attr->x87[0]->name));
-
- --num;
- }
+ } while (--num > 0);
return fpop;
} /* x87_create_fpop */
-/**
- * Creates an fldz before node n
- *
- * @param state the x87 state
- * @param n the node after the fldz
- *
- * @return the fldz node
- */
-static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx)
-{
- ir_graph *irg = get_irn_irg(n);
- ir_node *block = get_nodes_block(n);
- ir_node *fldz;
-
- fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
-
- sched_add_before(n, fldz);
- DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
- keep_alive(fldz);
-
- x87_push(state, regidx, fldz);
-
- return fldz;
-}
-
/* --------------------------------- liveness ------------------------------------------ */
/**
live &= ~(1 << arch_register_get_index(reg));
}
}
- }
-
- if (arch_irn_consider_in_reg_alloc(cls, irn)) {
+ } else if (arch_irn_consider_in_reg_alloc(cls, irn)) {
const arch_register_t *reg = x87_get_irn_register(irn);
live &= ~(1 << arch_register_get_index(reg));
}
} /* vfp_liveness_end_of_block */
/** get the register mask from an arch_register */
-#define REGMASK(reg) (1 << (arch_register_get_index(reg)))
+#define REGMASK(reg) (1 << (arch_register_get_index(reg)))
/**
* Return a bitset of argument registers which are live at the end of a node.
/* --------------------------------- simulators ---------------------------------------- */
-#define XCHG(a, b) do { int t = (a); (a) = (b); (b) = t; } while (0)
-
-/* Pseudocode:
-
-
-
-
-
-
-*/
-
/**
* Simulate a virtual binop.
*
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
const arch_register_t *op1_reg = x87_get_irn_register(op1);
const arch_register_t *op2_reg = x87_get_irn_register(op2);
- const arch_register_t *out = x87_get_irn_register(n);
+ const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state));
- if (reg_index_1 == REG_VFP_UKNWN) {
- op1_idx = 0;
- op1_live_after = 1;
- } else {
- op1_idx = x87_on_stack(state, reg_index_1);
- assert(op1_idx >= 0);
- op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live);
- }
+ op1_idx = x87_on_stack(state, reg_index_1);
+ assert(op1_idx >= 0);
+ op1_live_after = is_vfp_live(reg_index_1, live);
attr = get_ia32_x87_attr(n);
permuted = attr->attr.data.ins_permuted;
- if (reg_index_2 != REG_VFP_NOREG) {
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
assert(!permuted);
- if (reg_index_2 == REG_VFP_UKNWN) {
- op2_idx = 0;
- op2_live_after = 1;
- } else {
- /* second operand is a vfp register */
- op2_idx = x87_on_stack(state, reg_index_2);
- assert(op2_idx >= 0);
- op2_live_after
- = is_vfp_live(arch_register_get_index(op2_reg), live);
- }
+ /* second operand is a vfp register */
+ op2_idx = x87_on_stack(state, reg_index_2);
+ assert(op2_idx >= 0);
+ op2_live_after = is_vfp_live(reg_index_2, live);
if (op2_live_after) {
/* Second operand is live. */
}
/* patch the operation */
- attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
- if (reg_index_2 != REG_VFP_NOREG) {
- attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
+ attr->x87[0] = op1_reg = get_st_reg(op1_idx);
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
+ attr->x87[1] = op2_reg = get_st_reg(op2_idx);
}
- attr->x87[2] = out = &ia32_st_regs[out_idx];
+ attr->x87[2] = out = get_st_reg(out_idx);
- if (reg_index_2 != REG_VFP_NOREG) {
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
DB((dbg, LEVEL_1, "<<< %s %s, %s -> %s\n", get_irn_opname(n),
arch_register_get_name(op1_reg), arch_register_get_name(op2_reg),
arch_register_get_name(out)));
*/
static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
{
- int op1_idx, out_idx;
+ int op1_idx;
x87_simulator *sim = state->sim;
- const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, UNOP_IDX));
+ const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, 0));
const arch_register_t *out = x87_get_irn_register(n);
ia32_x87_attr_t *attr;
unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* push the operand here */
- x87_create_fpush(state, n, op1_idx, UNOP_IDX);
+ x87_create_fpush(state, n, op1_idx, 0);
op1_idx = 0;
}
else {
}
x87_set_tos(state, arch_register_get_index(out), x87_patch_insn(n, op));
- out_idx = 0;
attr = get_ia32_x87_attr(n);
- attr->x87[0] = op1 = &ia32_st_regs[0];
- attr->x87[2] = out = &ia32_st_regs[0];
+ attr->x87[0] = op1 = get_st_reg(0);
+ attr->x87[2] = out = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), out->name));
return NO_NODE_ADDED;
*
* @return NO_NODE_ADDED
*/
-static int sim_load(x87_state *state, ir_node *n, ir_op *op)
+static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
{
- const arch_register_t *out = x87_get_irn_register(n);
+ const arch_register_t *out = x87_irn_get_register(n, res_pos);
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
- assert(out == x87_get_irn_register(n));
+ assert(out == x87_irn_get_register(n, res_pos));
attr = get_ia32_x87_attr(n);
- attr->x87[2] = out = &ia32_st_regs[0];
+ attr->x87[2] = out = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
return NO_NODE_ADDED;
ir_mode *mode;
op2_reg_idx = arch_register_get_index(op2);
- if (op2_reg_idx == REG_VFP_UKNWN) {
- /* just take any value from stack */
- if (state->depth > 0) {
- op2_idx = 0;
- DEBUG_ONLY(op2 = NULL);
- live_after_node = 1;
- } else {
- /* produce a new value which we will consume immediately */
- x87_create_fldz(state, n, op2_reg_idx);
- live_after_node = 0;
- op2_idx = x87_on_stack(state, op2_reg_idx);
- assert(op2_idx >= 0);
- }
- } else {
- op2_idx = x87_on_stack(state, op2_reg_idx);
- live_after_node = is_vfp_live(arch_register_get_index(op2), live);
- DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
- assert(op2_idx >= 0);
- }
+ op2_idx = x87_on_stack(state, op2_reg_idx);
+ live_after_node = is_vfp_live(arch_register_get_index(op2), live);
+ DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
+ assert(op2_idx >= 0);
mode = get_ia32_ls_mode(n);
depth = x87_get_depth(state);
if (live_after_node) {
/*
- Problem: fst doesn't support mode_E (spills), only fstp does
+ Problem: fst doesn't support 96bit modes (spills), only fstp does
+ fist doesn't support 64bit mode, only fistp
Solution:
- stack not full: push value and fstp
- stack full: fstp value and load again
Note that we cannot test on mode_E, because floats might be 96bit ...
*/
- if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) {
- if (depth < N_x87_REGS) {
+ if (get_mode_size_bits(mode) > 64 || (mode_is_int(mode) && get_mode_size_bits(mode) > 32)) {
+ if (depth < N_ia32_st_REGS) {
/* ok, we have a free register: push + fstp */
x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
x87_pop(state);
x87_patch_insn(n, op_p);
} else {
ir_node *vfld, *mem, *block, *rproj, *mproj;
- ir_graph *irg;
+ ir_graph *irg = get_irn_irg(n);
+ ir_node *nomem = get_irg_no_mem(irg);
/* stack full here: need fstp + load */
x87_pop(state);
x87_patch_insn(n, op_p);
block = get_nodes_block(n);
- irg = get_irn_irg(n);
- vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
+ vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), nomem, get_ia32_ls_mode(n));
/* copy all attributes */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
- rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
- mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
+ rproj = new_r_Proj(vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
+ mproj = new_r_Proj(vfld, mode_M, pn_ia32_vfld_M);
mem = get_irn_Proj_for_mode(n, mode_M);
assert(mem && "Store memory not found");
arch_set_irn_register(rproj, op2);
/* reroute all former users of the store memory to the load memory */
- edges_reroute(mem, mproj, irg);
+ edges_reroute(mem, mproj);
/* set the memory input of the load to the store memory */
set_irn_n(vfld, n_ia32_vfld_mem, mem);
if (op2_idx != 0)
x87_create_fxch(state, n, op2_idx);
- /* mode != mode_E -> use normal fst */
+ /* mode size 64 or smaller -> use normal fst */
x87_patch_insn(n, op);
}
} else {
}
attr = get_ia32_x87_attr(n);
- attr->x87[1] = op2 = &ia32_st_regs[0];
+ attr->x87[1] = op2 = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
return insn;
}
#define GEN_BINOP(op) _GEN_BINOP(op, op)
-#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
+#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
-#define GEN_LOAD2(op, nop) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_load(state, n, op_ia32_##nop); \
+#define GEN_LOAD(op) \
+static int sim_##op(x87_state *state, ir_node *n) { \
+ return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
}
-#define GEN_LOAD(op) GEN_LOAD2(op, op)
-
#define GEN_UNOP(op) \
static int sim_##op(x87_state *state, ir_node *n) { \
return sim_unop(state, n, op_ia32_##op); \
GEN_STORE(fist)
/**
-* Simulate a virtual fisttp.
-*
-* @param state the x87 state
-* @param n the node that should be simulated (and patched)
-*/
+ * Simulate a virtual fisttp.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_fisttp(x87_state *state, ir_node *n)
{
ir_node *val = get_irn_n(n, n_ia32_vfst_val);
const arch_register_t *op2 = x87_get_irn_register(val);
- int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
- int op2_reg_idx, op2_idx, depth;
+ int op2_reg_idx, op2_idx;
op2_reg_idx = arch_register_get_index(op2);
- if (op2_reg_idx == REG_VFP_UKNWN) {
- /* just take any value from stack */
- if (state->depth > 0) {
- op2_idx = 0;
- DEBUG_ONLY(op2 = NULL);
- } else {
- /* produce a new value which we will consume immediately */
- x87_create_fldz(state, n, op2_reg_idx);
- op2_idx = x87_on_stack(state, op2_reg_idx);
- assert(op2_idx >= 0);
- }
- } else {
- op2_idx = x87_on_stack(state, op2_reg_idx);
- DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
- assert(op2_idx >= 0);
- }
-
- depth = x87_get_depth(state);
+ op2_idx = x87_on_stack(state, op2_reg_idx);
+ DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
+ assert(op2_idx >= 0);
/* Note: although the value is still live here, it is destroyed because
of the pop. The register allocator is aware of that and introduced a copy
x87_patch_insn(n, op_ia32_fisttp);
attr = get_ia32_x87_attr(n);
- attr->x87[1] = op2 = &ia32_st_regs[0];
+ attr->x87[1] = op2 = get_st_reg(0);
DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
- return insn;
+ return NO_NODE_ADDED;
} /* sim_fisttp */
+/**
+ * Simulate a virtual FtstFnstsw.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_FtstFnstsw(x87_state *state, ir_node *n)
{
x87_simulator *sim = state->sim;
/* patch the operation */
x87_patch_insn(n, op_ia32_FtstFnstsw);
- reg1 = &ia32_st_regs[op1_idx];
+ reg1 = get_st_reg(op1_idx);
attr->x87[0] = reg1;
attr->x87[1] = NULL;
attr->x87[2] = NULL;
- if (!is_vfp_live(reg_index_1, live)) {
+ if (!is_vfp_live(reg_index_1, live))
x87_create_fpop(state, sched_next(n), 1);
- return NODE_ADDED;
- }
return NO_NODE_ADDED;
-}
+} /* sim_FtstFnstsw */
/**
+ * Simulate a Fucom
+ *
* @param state the x87 state
* @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
*/
static int sim_Fucom(x87_state *state, ir_node *n)
{
int op2_idx = -1;
ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
ir_op *dst;
- x87_simulator *sim = state->sim;
- ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
- ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
- const arch_register_t *op1 = x87_get_irn_register(op1_node);
- const arch_register_t *op2 = x87_get_irn_register(op2_node);
+ x87_simulator *sim = state->sim;
+ ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
+ ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
+ const arch_register_t *op1 = x87_get_irn_register(op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(op2_node);
int reg_index_1 = arch_register_get_index(op1);
- int reg_index_2 = arch_register_get_index(op2);
- unsigned live = vfp_live_args_after(sim, n, 0);
- int permuted = attr->attr.data.ins_permuted;
- int xchg = 0;
- int pops = 0;
- int node_added = NO_NODE_ADDED;
+ int reg_index_2 = arch_register_get_index(op2);
+ unsigned live = vfp_live_args_after(sim, n, 0);
+ bool permuted = attr->attr.data.ins_permuted;
+ bool xchg = false;
+ int pops = 0;
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
arch_register_get_name(op1), arch_register_get_name(op2)));
assert(op1_idx >= 0);
/* BEWARE: check for comp a,a cases, they might happen */
- if (reg_index_2 != REG_VFP_NOREG) {
+ if (reg_index_2 != REG_VFP_VFP_NOREG) {
/* second operand is a vfp register */
op2_idx = x87_on_stack(state, reg_index_2);
assert(op2_idx >= 0);
} else if (op2_idx == 0) {
/* res = op X tos */
permuted = !permuted;
- xchg = 1;
+ xchg = true;
} else {
/* bring the first one to tos */
x87_create_fxch(state, n, op1_idx);
- if (op2_idx == 0)
+ if (op1_idx == op2_idx) {
+ op2_idx = 0;
+ } else if (op2_idx == 0) {
op2_idx = op1_idx;
+ }
op1_idx = 0;
/* res = tos X op */
}
op2_idx = 0;
}
/* res = op X tos, pop */
- pops = 1;
+ pops = 1;
permuted = !permuted;
- xchg = 1;
+ xchg = true;
} else {
/* both operands are dead here, check first for identity. */
if (op1_idx == op2_idx) {
}
/* res = op X tos, pop, pop */
permuted = !permuted;
- xchg = 1;
- pops = 2;
+ xchg = true;
+ pops = 2;
} else {
/* if one is already the TOS, we need two fxch */
if (op1_idx == 0) {
x87_create_fxch(state, n, op2_idx);
op2_idx = 0;
/* res = op X tos, pop, pop */
- pops = 2;
+ pops = 2;
permuted = !permuted;
- xchg = 1;
+ xchg = true;
} else if (op2_idx == 0) {
/* second one is TOS, move to st(1) */
x87_create_fxch(state, n, 1);
dst = op_ia32_Fucompi;
x87_pop(state);
x87_create_fpop(state, sched_next(n), 1);
- node_added = NODE_ADDED;
break;
default: panic("invalid popcount in sim_Fucom");
}
op2_idx = tmp;
}
- op1 = &ia32_st_regs[op1_idx];
+ op1 = get_st_reg(op1_idx);
attr->x87[0] = op1;
if (op2_idx >= 0) {
- op2 = &ia32_st_regs[op2_idx];
+ op2 = get_st_reg(op2_idx);
attr->x87[1] = op2;
}
attr->x87[2] = NULL;
arch_register_get_name(op1)));
}
- return node_added;
-}
+ return NO_NODE_ADDED;
+} /* sim_Fucom */
+/**
+ * Simulate a Keep.
+ *
+ * @param state the x87 state
+ * @param n the node that should be simulated (and patched)
+ *
+ * @return NO_NODE_ADDED
+ */
static int sim_Keep(x87_state *state, ir_node *node)
{
const ir_node *op;
int op_stack_idx;
unsigned live;
int i, arity;
- int node_added = NO_NODE_ADDED;
DB((dbg, LEVEL_1, ">>> %+F\n", node));
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
- if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
+ if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live))
x87_create_fpop(state, sched_next(node), 1);
- node_added = NODE_ADDED;
- }
}
DB((dbg, LEVEL_1, "Stack after: "));
DEBUG_ONLY(x87_dump_stack(state));
- return node_added;
-}
+ return NO_NODE_ADDED;
+} /* sim_Keep */
+/**
+ * Keep the given node alive by adding a be_Keep.
+ *
+ * @param node the node to kept alive
+ */
static void keep_float_node_alive(ir_node *node)
{
- ir_graph *irg;
- ir_node *block;
- ir_node *in[1];
- ir_node *keep;
- const arch_register_class_t *cls;
-
- irg = get_irn_irg(node);
- block = get_nodes_block(node);
- cls = arch_get_irn_reg_class(node, -1);
- in[0] = node;
- keep = be_new_Keep(cls, irg, block, 1, in);
+ ir_node *block = get_nodes_block(node);
+ ir_node *keep = be_new_Keep(block, 1, &node);
assert(sched_is_scheduled(node));
sched_add_after(node, keep);
*/
static ir_node *create_Copy(x87_state *state, ir_node *n)
{
- ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
ir_mode *mode = get_irn_mode(n);
ir_node *block = get_nodes_block(n);
ir_node *pred = get_irn_n(n, 0);
- ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
+ ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
ir_node *res;
const arch_register_t *out;
const arch_register_t *op1;
/* Do not copy constants, recreate them. */
switch (get_ia32_irn_opcode(pred)) {
- case iro_ia32_Unknown_VFP:
case iro_ia32_fldz:
- cnstr = new_rd_ia32_fldz;
+ cnstr = new_bd_ia32_fldz;
break;
case iro_ia32_fld1:
- cnstr = new_rd_ia32_fld1;
+ cnstr = new_bd_ia32_fld1;
break;
case iro_ia32_fldpi:
- cnstr = new_rd_ia32_fldpi;
+ cnstr = new_bd_ia32_fldpi;
break;
case iro_ia32_fldl2e:
- cnstr = new_rd_ia32_fldl2e;
+ cnstr = new_bd_ia32_fldl2e;
break;
case iro_ia32_fldl2t:
- cnstr = new_rd_ia32_fldl2t;
+ cnstr = new_bd_ia32_fldl2t;
break;
case iro_ia32_fldlg2:
- cnstr = new_rd_ia32_fldlg2;
+ cnstr = new_bd_ia32_fldlg2;
break;
case iro_ia32_fldln2:
- cnstr = new_rd_ia32_fldln2;
+ cnstr = new_bd_ia32_fldln2;
break;
default:
break;
if (cnstr != NULL) {
/* copy a constant */
- res = (*cnstr)(n_dbg, irg, block, mode);
+ res = (*cnstr)(n_dbg, block, mode);
x87_push(state, arch_register_get_index(out), res);
attr = get_ia32_x87_attr(res);
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[2] = get_st_reg(0);
} else {
int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
- res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
+ res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
x87_push(state, arch_register_get_index(out), res);
attr = get_ia32_x87_attr(res);
- attr->x87[0] = &ia32_st_regs[op1_idx];
- attr->x87[2] = &ia32_st_regs[0];
+ attr->x87[0] = get_st_reg(op1_idx);
+ attr->x87[2] = get_st_reg(0);
}
arch_set_irn_register(res, out);
const arch_register_t *op1;
const arch_register_class_t *cls;
ir_node *node, *next;
- ia32_x87_attr_t *attr;
int op1_idx, out_idx;
unsigned live;
- cls = arch_get_irn_reg_class(n, -1);
- if (cls->regs != ia32_vfp_regs)
+ cls = arch_get_irn_reg_class(n);
+ if (cls != &ia32_reg_classes[CLASS_ia32_vfp])
return 0;
pred = get_irn_n(n, 0);
arch_register_get_name(op1), arch_register_get_name(out)));
DEBUG_ONLY(vfp_dump_live(live));
- /* handle the infamous unknown value */
- if (arch_register_get_index(op1) == REG_VFP_UKNWN) {
- /* Operand is still live, a real copy. We need here an fpush that can
- hold a a register, so use the fpushCopy or recreate constants */
- node = create_Copy(state, n);
-
- assert(is_ia32_fldz(node));
- next = sched_next(n);
- sched_remove(n);
- exchange(n, node);
- sched_add_before(next, node);
-
- DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
- arch_get_irn_register(node)->name));
- return NO_NODE_ADDED;
- }
-
op1_idx = x87_on_stack(state, arch_register_get_index(op1));
if (is_vfp_live(arch_register_get_index(op1), live)) {
- ir_node *pred = get_irn_n(n, 0);
-
/* Operand is still live, a real copy. We need here an fpush that can
hold a a register, so use the fpushCopy or recreate constants */
node = create_Copy(state, n);
if (out_idx >= 0 && out_idx != op1_idx) {
/* Matze: out already on stack? how can this happen? */
- assert(0);
+ panic("invalid stack state in x87 simulator");
+#if 0
/* op1 must be killed and placed where out is */
if (out_idx == 0) {
+ ia32_x87_attr_t *attr;
/* best case, simple remove and rename */
x87_patch_insn(n, op_ia32_Pop);
attr = get_ia32_x87_attr(n);
- attr->x87[0] = op1 = &ia32_st_regs[0];
+ attr->x87[0] = op1 = get_st_reg(0);
x87_pop(state);
x87_set_st(state, arch_register_get_index(out), n, op1_idx - 1);
} else {
+ ia32_x87_attr_t *attr;
/* move op1 to tos, store and pop it */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
}
x87_patch_insn(n, op_ia32_Pop);
attr = get_ia32_x87_attr(n);
- attr->x87[0] = op1 = &ia32_st_regs[out_idx];
+ attr->x87[0] = op1 = get_st_reg(out_idx);
x87_pop(state);
x87_set_st(state, arch_register_get_index(out), n, out_idx - 1);
}
DB((dbg, LEVEL_1, "<<< %+F %s\n", n, op1->name));
+#endif
} else {
/* just a virtual copy */
x87_set_st(state, arch_register_get_index(out), get_unop_op(n), op1_idx);
} /* sim_Copy */
/**
- * Returns the result proj of the call
+ * Returns the vf0 result Proj of a Call.
+ *
+ * @para call the Call node
*/
static ir_node *get_call_result_proj(ir_node *call)
{
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
- if (pn == pn_ia32_Call_vf0) {
+ if (pn == pn_ia32_Call_vf0)
return proj;
- }
}
return NULL;
* Simulate a ia32_Call.
*
* @param state the x87 state
- * @param n the node that should be simulated
+ * @param n the node that should be simulated (and patched)
*
* @return NO_NODE_ADDED
*/
return NO_NODE_ADDED;
} /* sim_Call */
-/**
- * Simulate a be_Spill.
- *
- * @param state the x87 state
- * @param n the node that should be simulated (and patched)
- *
- * Should not happen, spills are lowered before x87 simulator see them.
- */
-static int sim_Spill(x87_state *state, ir_node *n)
-{
- assert(0 && "Spill not lowered");
- return sim_fst(state, n);
-} /* sim_Spill */
-
-/**
- * Simulate a be_Reload.
- *
- * @param state the x87 state
- * @param n the node that should be simulated (and patched)
- *
- * Should not happen, reloads are lowered before x87 simulator see them.
- */
-static int sim_Reload(x87_state *state, ir_node *n)
-{
- assert(0 && "Reload not lowered");
- return sim_fld(state, n);
-} /* sim_Reload */
-
/**
* Simulate a be_Return.
*
/* only floating point return values must reside on stack */
for (i = 0; i < n_res; ++i) {
- ir_node *res = get_irn_n(n, be_pos_Return_val + i);
+ ir_node *res = get_irn_n(n, n_be_Return_val + i);
if (mode_is_float(get_irn_mode(res)))
++n_float_res;
return NO_NODE_ADDED;
} /* sim_Return */
-typedef struct _perm_data_t {
+typedef struct perm_data_t {
const arch_register_t *in;
const arch_register_t *out;
} perm_data_t;
return NO_NODE_ADDED;
} /* sim_Perm */
-static int sim_Barrier(x87_state *state, ir_node *node)
-{
- int i, arity;
-
- /* materialize unknown if needed */
- arity = get_irn_arity(node);
- for (i = 0; i < arity; ++i) {
- const arch_register_t *reg;
- ir_node *zero;
- ir_node *block;
- ia32_x87_attr_t *attr;
- ir_node *in = get_irn_n(node, i);
-
- if (!is_ia32_Unknown_VFP(in))
- continue;
-
- /* TODO: not completely correct... */
- reg = &ia32_vfp_regs[REG_VFP_UKNWN];
-
- /* create a zero */
- block = get_nodes_block(node);
- zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E);
- x87_push(state, arch_register_get_index(reg), zero);
-
- attr = get_ia32_x87_attr(zero);
- attr->x87[2] = &ia32_st_regs[0];
-
- sched_add_before(node, zero);
-
- set_irn_n(node, i, zero);
- }
-
- return NO_NODE_ADDED;
-}
-
-
/**
* Kill any dead registers at block start by popping them from the stack.
*
if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
if (ia32_cg_config.use_femms) {
/* use FEMMS on AMD processors to clear all */
- keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block);
+ keep = new_bd_ia32_femms(NULL, block);
} else {
/* use EMMS to clear all */
- keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block);
+ keep = new_bd_ia32_emms(NULL, block);
}
sched_add_before(first_insn, keep);
keep_alive(keep);
return state;
} /* x87_kill_deads */
-/**
- * If we have PhiEs with unknown operands then we have to make sure that some
- * value is actually put onto the stack.
- */
-static void fix_unknown_phis(x87_state *state, ir_node *block,
- ir_node *pred_block, int pos)
-{
- ir_node *node, *op;
-
- sched_foreach(block, node) {
- ir_node *zero;
- const arch_register_t *reg;
- ia32_x87_attr_t *attr;
-
- if (!is_Phi(node))
- break;
-
- op = get_Phi_pred(node, pos);
- if (!is_ia32_Unknown_VFP(op))
- continue;
-
- reg = arch_get_irn_register(node);
-
- /* create a zero at end of pred block */
- zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
- x87_push(state, arch_register_get_index(reg), zero);
-
- attr = get_ia32_x87_attr(zero);
- attr->x87[2] = &ia32_st_regs[0];
-
- assert(is_ia32_fldz(zero));
- sched_add_before(sched_last(pred_block), zero);
-
- set_Phi_pred(node, pos, zero);
- }
-}
-
/**
* Run a simulation and fix all virtual instructions for a block.
*
sim_func func;
ir_op *op = get_irn_op(n);
+ /*
+ * get the next node to be simulated here.
+ * n might be completely removed from the schedule-
+ */
next = sched_next(n);
- if (op->ops.generic == NULL)
- continue;
-
- func = (sim_func)op->ops.generic;
+ if (op->ops.generic != NULL) {
+ func = (sim_func)op->ops.generic;
- /* simulate it */
- node_inserted = (*func)(state, n);
+ /* simulate it */
+ node_inserted = (*func)(state, n);
- /*
- sim_func might have added an additional node after n,
- so update next node
- beware: n must not be changed by sim_func
- (i.e. removed from schedule) in this case
- */
- if (node_inserted != NO_NODE_ADDED)
- next = sched_next(n);
+ /*
+ * sim_func might have added an additional node after n,
+ * so update next node
+ * beware: n must not be changed by sim_func
+ * (i.e. removed from schedule) in this case
+ */
+ if (node_inserted != NO_NODE_ADDED)
+ next = sched_next(n);
+ }
}
start_block = get_irg_start_block(get_irn_irg(block));
succ_state = x87_get_bl_state(sim, succ);
- fix_unknown_phis(state, succ, block, get_edge_src_pos(edge));
-
if (succ_state->begin == NULL) {
DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
DEBUG_ONLY(x87_dump_stack(state));
bl_state->end = state;
} /* x87_simulate_block */
+/**
+ * Register a simulator function.
+ *
+ * @param op the opcode to simulate
+ * @param func the simulator function for the opcode
+ */
static void register_sim(ir_op *op, sim_func func)
{
assert(op->ops.generic == NULL);
op->ops.generic = (op_func) func;
-}
+} /* register_sim */
/**
* Create a new x87 simulator.
obstack_init(&sim->obst);
sim->blk_states = pmap_create();
sim->n_idx = get_irg_last_idx(irg);
- sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
+ sim->live = OALLOCN(&sim->obst, vfp_liveness, sim->n_idx);
DB((dbg, LEVEL_1, "--------------------------------\n"
"x87 Simulator started for %+F\n", irg));
register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
register_sim(op_ia32_vFucomi, sim_Fucom);
register_sim(op_be_Copy, sim_Copy);
- register_sim(op_be_Spill, sim_Spill);
- register_sim(op_be_Reload, sim_Reload);
register_sim(op_be_Return, sim_Return);
register_sim(op_be_Perm, sim_Perm);
register_sim(op_be_Keep, sim_Keep);
- register_sim(op_be_Barrier, sim_Barrier);
} /* x87_init_simulator */
/**
*/
static void update_liveness_walker(ir_node *block, void *data)
{
- x87_simulator *sim = data;
+ x87_simulator *sim = (x87_simulator*)data;
update_liveness(sim, block);
} /* update_liveness_walker */
-void x87_simulate_graph(be_irg_t *birg)
+/*
+ * Run a simulation and fix all virtual instructions for a graph.
+ * Replaces all virtual floating point instructions and registers
+ * by real ones.
+ */
+void ia32_x87_simulate_graph(ir_graph *irg)
{
+ /* TODO improve code quality (less executed fxch) by using execfreqs */
+
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
- ir_graph *irg = be_get_birg_irg(birg);
/* create the simulator */
x87_init_simulator(&sim, irg);
sim.worklist = new_waitq();
waitq_put(sim.worklist, start_block);
- be_assure_liveness(birg);
- sim.lv = be_get_birg_liveness(birg);
-// sim.lv = be_liveness(be_get_birg_irg(birg));
+ be_assure_liveness(irg);
+ sim.lv = be_get_irg_liveness(irg);
be_liveness_assure_sets(sim.lv);
/* Calculate the liveness for all nodes. We must precalculate this info,
/* iterate */
do {
- block = waitq_get(sim.worklist);
+ block = (ir_node*)waitq_get(sim.worklist);
x87_simulate_block(&sim, block);
} while (! waitq_empty(sim.worklist));
/* kill it */
del_waitq(sim.worklist);
x87_destroy_simulator(&sim);
-} /* x87_simulate_graph */
+} /* ia32_x87_simulate_graph */
+/* Initializes the x87 simulator. */
void ia32_init_x87(void)
{
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
projects / libfirm / blobdiff