* @author Michael Beck
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include <assert.h>
struct _x87_simulator {
struct obstack obst; /**< An obstack for fast allocating. */
pmap *blk_states; /**< Map blocks to states. */
- const arch_env_t *arch_env; /**< The architecture environment. */
be_lv_t *lv; /**< intrablock liveness. */
vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
/**
* Wrap the arch_* function here so we can check for errors.
*/
-static INLINE const arch_register_t *x87_get_irn_register(const ir_node *irn)
+static inline const arch_register_t *x87_get_irn_register(const ir_node *irn)
{
const arch_register_t *res = arch_get_irn_register(irn);
return res;
} /* x87_get_irn_register */
+static inline const arch_register_t *x87_irn_get_register(const ir_node *irn,
+ int pos)
+{
+ const arch_register_t *res = arch_irn_get_register(irn, pos);
+
+ assert(res->reg_class->regs == ia32_vfp_regs);
+ return res;
+}
+
/* -------------- x87 perm --------------- */
/**
ir_node *fxch;
ia32_x87_attr_t *attr;
- fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block);
+ fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
{
ir_node *fxch;
ia32_x87_attr_t *attr;
- ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
x87_fxch(state, pos);
- fxch = new_rd_ia32_fxch(NULL, irg, block);
+ fxch = new_bd_ia32_fxch(NULL, block);
attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
x87_push_dbl(state, arch_register_get_index(out), pred);
- fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpush = new_bd_ia32_fpush(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpush);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
while (num > 0) {
x87_pop(state);
if (ia32_cg_config.use_ffreep)
- fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpop = new_bd_ia32_ffreep(NULL, get_nodes_block(n));
else
- fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n));
+ fpop = new_bd_ia32_fpop(NULL, get_nodes_block(n));
attr = get_ia32_x87_attr(fpop);
attr->x87[0] = &ia32_st_regs[0];
attr->x87[1] = &ia32_st_regs[0];
*/
static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx)
{
- ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
ir_node *fldz;
- fldz = new_rd_ia32_fldz(NULL, irg, block, mode_E);
+ fldz = new_bd_ia32_fldz(NULL, block, mode_E);
sched_add_before(n, fldz);
DB((dbg, LEVEL_1, "<<< %s\n", get_irn_opname(fldz)));
* Updates a live set over a single step from a given node to its predecessor.
* Everything defined at the node is removed from the set, the uses of the node get inserted.
*
- * @param sim The simulator handle.
* @param irn The node at which liveness should be computed.
* @param live The bitset of registers live before @p irn. This set gets modified by updating it to
* the registers live after irn.
*
* @return The live bitset.
*/
-static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live)
+static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
{
int i, n;
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
- const arch_env_t *arch_env = sim->arch_env;
if (get_irn_mode(irn) == mode_T) {
const ir_edge_t *edge;
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
- if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
+ if (arch_irn_consider_in_reg_alloc(cls, proj)) {
const arch_register_t *reg = x87_get_irn_register(proj);
live &= ~(1 << arch_register_get_index(reg));
}
}
}
- if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
+ if (arch_irn_consider_in_reg_alloc(cls, irn)) {
const arch_register_t *reg = x87_get_irn_register(irn);
live &= ~(1 << arch_register_get_index(reg));
}
for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
ir_node *op = get_irn_n(irn, i);
- if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
+ if (mode_is_float(get_irn_mode(op)) &&
+ arch_irn_consider_in_reg_alloc(cls, op)) {
const arch_register_t *reg = x87_get_irn_register(op);
live |= 1 << arch_register_get_index(reg);
}
int i;
vfp_liveness live = 0;
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
- const arch_env_t *arch_env = sim->arch_env;
const be_lv_t *lv = sim->lv;
be_lv_foreach(lv, block, be_lv_state_end, i) {
const arch_register_t *reg;
const ir_node *node = be_lv_get_irn(lv, block, i);
- if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node))
+ if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
reg = x87_get_irn_register(node);
idx = get_irn_idx(irn);
sim->live[idx] = live;
- live = vfp_liveness_transfer(sim, irn, live);
+ live = vfp_liveness_transfer(irn, live);
}
idx = get_irn_idx(block);
sim->live[idx] = live;
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
const arch_register_t *op1_reg = x87_get_irn_register(op1);
const arch_register_t *op2_reg = x87_get_irn_register(op2);
- const arch_register_t *out = x87_get_irn_register(n);
+ const arch_register_t *out = x87_irn_get_register(n, pn_ia32_res);
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
*
* @return NO_NODE_ADDED
*/
-static int sim_load(x87_state *state, ir_node *n, ir_op *op)
+static int sim_load(x87_state *state, ir_node *n, ir_op *op, int res_pos)
{
- const arch_register_t *out = x87_get_irn_register(n);
+ const arch_register_t *out = x87_irn_get_register(n, res_pos);
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
- assert(out == x87_get_irn_register(n));
+ assert(out == x87_irn_get_register(n, res_pos));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
x87_patch_insn(n, op_p);
block = get_nodes_block(n);
- irg = get_irn_irg(n);
- vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
+ vfld = new_bd_ia32_vfld(NULL, block, get_irn_n(n, 0), get_irn_n(n, 1), new_NoMem(), get_ia32_ls_mode(n));
/* copy all attributes */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
+ irg = get_irn_irg(n);
rproj = new_r_Proj(irg, block, vfld, get_ia32_ls_mode(vfld), pn_ia32_vfld_res);
mproj = new_r_Proj(irg, block, vfld, mode_M, pn_ia32_vfld_M);
mem = get_irn_Proj_for_mode(n, mode_M);
#define GEN_BINOP(op) _GEN_BINOP(op, op)
#define GEN_BINOPR(op) _GEN_BINOP(op, op##r)
-#define GEN_LOAD2(op, nop) \
-static int sim_##op(x87_state *state, ir_node *n) { \
- return sim_load(state, n, op_ia32_##nop); \
+#define GEN_LOAD(op) \
+static int sim_##op(x87_state *state, ir_node *n) { \
+ return sim_load(state, n, op_ia32_##op, pn_ia32_v##op##_res); \
}
-#define GEN_LOAD(op) GEN_LOAD2(op, op)
-
#define GEN_UNOP(op) \
static int sim_##op(x87_state *state, ir_node *n) { \
return sim_unop(state, n, op_ia32_##op); \
static void keep_float_node_alive(ir_node *node)
{
- ir_graph *irg;
- ir_node *block;
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *block = get_nodes_block(node);
+ const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
ir_node *in[1];
ir_node *keep;
- const arch_register_class_t *cls;
- irg = get_irn_irg(node);
- block = get_nodes_block(node);
- cls = arch_get_irn_reg_class(node, -1);
in[0] = node;
keep = be_new_Keep(cls, irg, block, 1, in);
*/
static ir_node *create_Copy(x87_state *state, ir_node *n)
{
- ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
ir_mode *mode = get_irn_mode(n);
ir_node *block = get_nodes_block(n);
ir_node *pred = get_irn_n(n, 0);
- ir_node *(*cnstr)(dbg_info *, ir_graph *, ir_node *, ir_mode *) = NULL;
+ ir_node *(*cnstr)(dbg_info *, ir_node *, ir_mode *) = NULL;
ir_node *res;
const arch_register_t *out;
const arch_register_t *op1;
switch (get_ia32_irn_opcode(pred)) {
case iro_ia32_Unknown_VFP:
case iro_ia32_fldz:
- cnstr = new_rd_ia32_fldz;
+ cnstr = new_bd_ia32_fldz;
break;
case iro_ia32_fld1:
- cnstr = new_rd_ia32_fld1;
+ cnstr = new_bd_ia32_fld1;
break;
case iro_ia32_fldpi:
- cnstr = new_rd_ia32_fldpi;
+ cnstr = new_bd_ia32_fldpi;
break;
case iro_ia32_fldl2e:
- cnstr = new_rd_ia32_fldl2e;
+ cnstr = new_bd_ia32_fldl2e;
break;
case iro_ia32_fldl2t:
- cnstr = new_rd_ia32_fldl2t;
+ cnstr = new_bd_ia32_fldl2t;
break;
case iro_ia32_fldlg2:
- cnstr = new_rd_ia32_fldlg2;
+ cnstr = new_bd_ia32_fldlg2;
break;
case iro_ia32_fldln2:
- cnstr = new_rd_ia32_fldln2;
+ cnstr = new_bd_ia32_fldln2;
break;
default:
break;
if (cnstr != NULL) {
/* copy a constant */
- res = (*cnstr)(n_dbg, irg, block, mode);
+ res = (*cnstr)(n_dbg, block, mode);
x87_push(state, arch_register_get_index(out), res);
} else {
int op1_idx = x87_on_stack(state, arch_register_get_index(op1));
- res = new_rd_ia32_fpushCopy(n_dbg, irg, block, pred, mode);
+ res = new_bd_ia32_fpushCopy(n_dbg, block, pred, mode);
x87_push(state, arch_register_get_index(out), res);
int op1_idx, out_idx;
unsigned live;
- cls = arch_get_irn_reg_class(n, -1);
+ cls = arch_get_irn_reg_class_out(n);
if (cls->regs != ia32_vfp_regs)
return 0;
*/
static int sim_Spill(x87_state *state, ir_node *n)
{
- assert(0 && "Spill not lowered");
+ panic("Spill not lowered");
return sim_fst(state, n);
} /* sim_Spill */
*/
static int sim_Reload(x87_state *state, ir_node *n)
{
- assert(0 && "Reload not lowered");
+ panic("Reload not lowered");
return sim_fld(state, n);
} /* sim_Reload */
static int sim_Barrier(x87_state *state, ir_node *node)
{
- //const arch_env_t *arch_env = state->sim->arch_env;
int i, arity;
/* materialize unknown if needed */
/* create a zero */
block = get_nodes_block(node);
- zero = new_rd_ia32_fldz(NULL, current_ir_graph, block, mode_E);
+ zero = new_bd_ia32_fldz(NULL, block, mode_E);
x87_push(state, arch_register_get_index(reg), zero);
attr = get_ia32_x87_attr(zero);
if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
if (ia32_cg_config.use_femms) {
/* use FEMMS on AMD processors to clear all */
- keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block);
+ keep = new_bd_ia32_femms(NULL, block);
} else {
/* use EMMS to clear all */
- keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block);
+ keep = new_bd_ia32_emms(NULL, block);
}
sched_add_before(first_insn, keep);
keep_alive(keep);
reg = arch_get_irn_register(node);
/* create a zero at end of pred block */
- zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
+ zero = new_bd_ia32_fldz(NULL, pred_block, mode_E);
x87_push(state, arch_register_get_index(reg), zero);
attr = get_ia32_x87_attr(zero);
*
* @param sim a simulator handle, will be initialized
* @param irg the current graph
- * @param arch_env the architecture environment
*/
-static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
- const arch_env_t *arch_env)
+static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
{
obstack_init(&sim->obst);
sim->blk_states = pmap_create();
- sim->arch_env = arch_env;
sim->n_idx = get_irg_last_idx(irg);
sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
update_liveness(sim, block);
} /* update_liveness_walker */
-/**
- * Run a simulation and fix all virtual instructions for a graph.
- *
- * @param env the architecture environment
- * @param irg the current graph
- *
- * Needs a block-schedule.
- */
-void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg)
+void x87_simulate_graph(be_irg_t *birg)
{
+ /* TODO improve code quality (less executed fxch) by using execfreqs */
+
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
ir_graph *irg = be_get_birg_irg(birg);
/* create the simulator */
- x87_init_simulator(&sim, irg, arch_env);
+ x87_init_simulator(&sim, irg);
start_block = get_irg_start_block(irg);
bl_state = x87_get_bl_state(&sim, start_block);
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