} x87_state;
/** An empty state, used for blocks without fp instructions. */
-static x87_state _empty = { { {0, NULL}, }, 0, 0 };
+static x87_state _empty = { { {0, NULL}, }, 0, 0, NULL };
static x87_state *empty = (x87_state *)&_empty;
enum {
*
* @return state
*/
-static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block, x87_state *state, ir_node *dst_block, const x87_state *dst_state) {
+static x87_state *x87_shuffle(x87_simulator *sim, ir_node *block,
+ x87_state *state, ir_node *dst_block,
+ const x87_state *dst_state)
+{
int i, n_cycles, k, ri;
unsigned cycles[4], all_mask;
char cycle_idx[4][8];
ir_node *fxch, *before, *after;
+ (void) sim;
+ (void) dst_block;
assert(state->depth == dst_state->depth);
* @param state the x87 state
* @param n the node after the fxch
* @param pos exchange st(pos) with st(0)
- * @param op_idx if >= 0, replace input op_idx of n with the fxch result
*
* @return the fxch
*/
-static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos, int op_idx) {
+static ir_node *x87_create_fxch(x87_state *state, ir_node *n, int pos)
+{
ir_node *fxch;
ia32_x87_attr_t *attr;
ir_graph *irg = get_irn_irg(n);
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
const arch_env_t *arch_env = sim->arch_env;
+#ifndef SCHEDULE_PROJS
+ if (get_irn_mode(irn) == mode_T) {
+ const ir_edge_t *edge;
+
+ foreach_out_edge(irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+
+ if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
+ const arch_register_t *reg = x87_get_irn_register(sim, proj);
+ live &= ~(1 << arch_register_get_index(reg));
+ }
+ }
+ }
+#endif
+
if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
- const arch_register_t *reg = x87_get_irn_register(sim, irn);
- live &= ~(1 << arch_register_get_index(reg));
+ const arch_register_t *reg = x87_get_irn_register(sim, irn);
+ live &= ~(1 << arch_register_get_index(reg));
}
for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
} else {
/* Second live, first operand is dead here, bring it to tos. */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
if (op2_idx == 0)
op2_idx = op1_idx;
op1_idx = 0;
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* First operand is live: bring second to tos. */
if (op2_idx != 0) {
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
if (op1_idx == 0)
op1_idx = op2_idx;
op2_idx = 0;
out_idx = op2_idx;
} else {
/* Bring the second on top. */
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
if (op1_idx == op2_idx) {
/* Both are identically and on tos now, no pop needed. */
op1_idx = 0;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
else {
/* operand is dead, bring it to tos */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, UNOP_IDX);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
}
} else {
op2_idx = x87_on_stack(state, op2_reg_idx);
live_after_node = is_vfp_live(arch_register_get_index(op2), live);
- assert(op2_idx >= 0);
DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
+ assert(op2_idx >= 0);
}
mode = get_ia32_ls_mode(n);
block = get_nodes_block(n);
irg = get_irn_irg(n);
- vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg));
+ vfld = new_rd_ia32_vfld(NULL, irg, block, get_irn_n(n, 0), get_irn_n(n, 1), new_rd_NoMem(irg), get_ia32_ls_mode(n));
/* copy all attributes */
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
} else {
/* we can only store the tos to memory */
if (op2_idx != 0)
- x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
+ x87_create_fxch(state, n, op2_idx);
/* mode != mode_E -> use normal fst */
x87_patch_insn(n, op);
} else {
/* we can only store the tos to memory */
if (op2_idx != 0)
- x87_create_fxch(state, n, op2_idx, STORE_VAL_IDX);
+ x87_create_fxch(state, n, op2_idx);
x87_pop(state);
x87_patch_insn(n, op_p);
return insn;
} /* sim_store */
-/**
- * Simulate a virtual Phi.
- * Just for cosmetic reasons change the mode of Phi nodes to mode_E.
- *
- * @param state the x87 state
- * @param n the node that should be simulated (and patched)
- * @param arch_env the architecture environment
- *
- * @return NO_NODE_ADDED
- */
-static int sim_Phi(x87_state *state, ir_node *n, const arch_env_t *arch_env) {
- ir_mode *mode = get_irn_mode(n);
-
- if (mode_is_float(mode))
- set_irn_mode(n, mode_E);
-
- return NO_NODE_ADDED;
-} /* sim_Phi */
-
#define _GEN_BINOP(op, rev) \
static int sim_##op(x87_state *state, ir_node *n) { \
exchange_tmpl tmpl = { op_ia32_##op, op_ia32_##rev, op_ia32_##op##p, op_ia32_##rev##p }; \
GEN_UNOP(fabs)
GEN_UNOP(fchs)
-GEN_UNOP(fsin)
-GEN_UNOP(fcos)
-GEN_UNOP(fsqrt)
GEN_LOAD(fld)
GEN_LOAD(fild)
ia32_x87_attr_t *attr;
ir_op *dst;
x87_simulator *sim = state->sim;
- const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_1));
- const arch_register_t *op2 = x87_get_irn_register(sim, get_irn_n(n, BINOP_IDX_2));
+ ir_node *op1_node = get_irn_n(n, n_ia32_vfCondJmp_left);
+ ir_node *op2_node = get_irn_n(n, n_ia32_vfCondJmp_right);
+ const arch_register_t *op1 = x87_get_irn_register(sim, op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(sim, op2_node);
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
unsigned live = vfp_live_args_after(sim, n, 0);
dst = op_ia32_fcomrJmp;
} else {
/* bring the first one to tos */
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
if (op2_idx == 0)
op2_idx = op1_idx;
op1_idx = 0;
This means further, op1_idx != op2_idx. */
assert(op1_idx != op2_idx);
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
if (op2_idx == 0)
op2_idx = op1_idx;
op1_idx = 0;
This means further, op1_idx != op2_idx. */
assert(op1_idx != op2_idx);
if (op2_idx != 0) {
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
if (op1_idx == 0)
op1_idx = op2_idx;
op2_idx = 0;
if (op1_idx == op2_idx) {
/* identically, one pop needed */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
op2_idx = 0;
}
/* good, second operand is already in the right place, move the first */
if (op1_idx != 0) {
/* bring the first on top */
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
assert(op2_idx != 0);
op1_idx = 0;
}
/* good, first operand is already in the right place, move the second */
if (op2_idx != 0) {
/* bring the first on top */
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
assert(op1_idx != 0);
op2_idx = 0;
}
/* if one is already the TOS, we need two fxch */
if (op1_idx == 0) {
/* first one is TOS, move to st(1) */
- x87_create_fxch(state, n, 1, BINOP_IDX_1);
+ x87_create_fxch(state, n, 1);
assert(op2_idx != 1);
op1_idx = 1;
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
op2_idx = 0;
/* res = op X tos, pop, pop */
dst = op_ia32_fcomrppJmp;
pop_cnt = 2;
} else if (op2_idx == 0) {
/* second one is TOS, move to st(1) */
- x87_create_fxch(state, n, 1, BINOP_IDX_2);
+ x87_create_fxch(state, n, 1);
assert(op1_idx != 1);
op2_idx = 1;
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
/* res = tos X op, pop, pop */
dst = op_ia32_fcomppJmp;
pop_cnt = 2;
} else {
/* none of them is either TOS or st(1), 3 fxch needed */
- x87_create_fxch(state, n, op2_idx, BINOP_IDX_2);
+ x87_create_fxch(state, n, op2_idx);
assert(op1_idx != 0);
- x87_create_fxch(state, n, 1, BINOP_IDX_2);
+ x87_create_fxch(state, n, 1);
op2_idx = 1;
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
/* res = tos X op, pop, pop */
dst = op_ia32_fcomppJmp;
if (is_vfp_live(arch_register_get_index(op1), live)) {
/* first operand is live: bring it to TOS */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
dst = op_ia32_fcomJmp;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, BINOP_IDX_1);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
dst = op_ia32_fcompJmp;
} else {
/* move op1 to tos, store and pop it */
if (op1_idx != 0) {
- x87_create_fxch(state, n, op1_idx, 0);
+ x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
x87_patch_insn(n, op_ia32_Pop);
*
* @return NO_NODE_ADDED
*/
-static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env) {
+static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
+{
ir_type *call_tp = be_Call_get_type(n);
ir_type *res_type;
ir_mode *mode;
ir_node *resproj;
const arch_register_t *reg;
+ (void) arch_env;
/* at the begin of a call the x87 state should be empty */
assert(state->depth == 0 && "stack not empty before call");
if (keep)
x87_set_st(state, -1, keep, i);
- x87_create_fxch(state, first_insn, i, -1);
+ x87_create_fxch(state, first_insn, i);
}
if ((kill_mask & 3) == 3) {
return state;
} /* x87_kill_deads */
+/**
+ * If we have PhiEs with unknown operands then we have to make sure that some
+ * value is actually put onto the stack.
+ */
+static void fix_unknown_phis(x87_state *state, ir_node *block,
+ ir_node *pred_block, int pos)
+{
+ ir_node *node, *op;
+
+ sched_foreach(block, node) {
+ ir_node *zero;
+ const arch_register_t *reg;
+ ia32_x87_attr_t *attr;
+
+ if(!is_Phi(node))
+ break;
+
+ op = get_Phi_pred(node, pos);
+ if(!is_ia32_Unknown_VFP(op))
+ continue;
+
+ reg = arch_get_irn_register(state->sim->arch_env, node);
+
+ /* create a zero at end of pred block */
+ zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
+ x87_push(state, arch_register_get_index(reg), zero);
+
+ attr = get_ia32_x87_attr(zero);
+ attr->x87[2] = &ia32_st_regs[0];
+
+ assert(is_ia32_fldz(zero));
+ sched_add_before(sched_last(pred_block), zero);
+
+ set_Phi_pred(node, pos, zero);
+ }
+}
+
/**
* Run a simulation and fix all virtual instructions for a block.
*
/* at block begin, kill all dead registers */
state = x87_kill_deads(sim, block, state);
+ /* create a new state, will be changed */
+ state = x87_clone_state(sim, state);
/* beware, n might change */
for (n = sched_first(block); !sched_is_end(n); n = next) {
func = (sim_func)op->ops.generic;
- /* have work to do */
- if (state == bl_state->begin) {
- /* create a new state, will be changed */
- state = x87_clone_state(sim, state);
- }
-
/* simulate it */
node_inserted = (*func)(state, n);
start_block = get_irg_start_block(get_irn_irg(block));
+ DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state));
+
/* check if the state must be shuffled */
foreach_block_succ(block, edge) {
ir_node *succ = get_edge_src_irn(edge);
succ_state = x87_get_bl_state(sim, succ);
+ fix_unknown_phis(state, succ, block, get_edge_src_pos(edge));
+
if (succ_state->begin == NULL) {
+ DB((dbg, LEVEL_2, "Set begin state for succ %+F:\n", succ));
+ DEBUG_ONLY(x87_dump_stack(state));
succ_state->begin = state;
+
waitq_put(sim->worklist, succ);
} else {
+ DB((dbg, LEVEL_2, "succ %+F already has a state, shuffling\n", succ));
/* There is already a begin state for the successor, bad.
Do the necessary permutations.
Note that critical edges are removed, so this is always possible:
}
}
bl_state->end = state;
-
- DB((dbg, LEVEL_2, "State at Block end:\n ")); DEBUG_ONLY(x87_dump_stack(state));
} /* x87_simulate_block */
/**
ASSOC_IA32(fprem);
ASSOC_IA32(fabs);
ASSOC_IA32(fchs);
- ASSOC_IA32(fsin);
- ASSOC_IA32(fcos);
- ASSOC_IA32(fsqrt);
ASSOC_IA32(fist);
ASSOC_IA32(fst);
ASSOC_IA32(fCondJmp);
ASSOC_BE(Return);
ASSOC_BE(Perm);
ASSOC_BE(Keep);
- ASSOC(Phi);
#undef ASSOC_BE
#undef ASSOC_IA32
#undef ASSOC
sim.worklist = new_waitq();
waitq_put(sim.worklist, start_block);
- be_invalidate_liveness(birg);
be_assure_liveness(birg);
sim.lv = be_get_birg_liveness(birg);
+// sim.lv = be_liveness(be_get_birg_irg(birg));
+ be_liveness_assure_sets(sim.lv);
/* Calculate the liveness for all nodes. We must precalculate this info,
* because the simulator adds new nodes (possible before Phi nodes) which