/*
- * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
+ * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
*
* This file is part of libFirm.
*
* @author Michael Beck
* @version $Id$
*/
-#ifdef HAVE_CONFIG_H
#include "config.h"
-#endif
#include <assert.h>
#include "irgwalk.h"
#include "obst.h"
#include "pmap.h"
+#include "array_t.h"
#include "pdeq.h"
#include "irprintf.h"
#include "debug.h"
#include "gen_ia32_new_nodes.h"
#include "gen_ia32_regalloc_if.h"
#include "ia32_x87.h"
+#include "ia32_architecture.h"
#define N_x87_REGS 8
struct _x87_simulator {
struct obstack obst; /**< An obstack for fast allocating. */
pmap *blk_states; /**< Map blocks to states. */
- const arch_env_t *arch_env; /**< The architecture environment. */
be_lv_t *lv; /**< intrablock liveness. */
vfp_liveness *live; /**< Liveness information. */
unsigned n_idx; /**< The cached get_irg_last_idx() result. */
*
* @return the x87 stack depth
*/
-static int x87_get_depth(const x87_state *state) {
+static int x87_get_depth(const x87_state *state)
+{
return state->depth;
} /* x87_get_depth */
*
* @return the vfp register index that produced the value at st(pos)
*/
-static int x87_get_st_reg(const x87_state *state, int pos) {
+static int x87_get_st_reg(const x87_state *state, int pos)
+{
assert(pos < state->depth);
return state->st[MASK_TOS(state->tos + pos)].reg_idx;
} /* x87_get_st_reg */
+#ifdef DEBUG_libfirm
/**
* Return the node at st(pos).
*
*
* @return the IR node that produced the value at st(pos)
*/
-static ir_node *x87_get_st_node(const x87_state *state, int pos) {
+static ir_node *x87_get_st_node(const x87_state *state, int pos)
+{
assert(pos < state->depth);
return state->st[MASK_TOS(state->tos + pos)].node;
} /* x87_get_st_node */
-#ifdef DEBUG_libfirm
/**
* Dump the stack for debugging.
*
* @param state the x87 state
*/
-static void x87_dump_stack(const x87_state *state) {
+static void x87_dump_stack(const x87_state *state)
+{
int i;
for (i = state->depth - 1; i >= 0; --i) {
* @param node the IR node that produces the value of the vfp register
* @param pos the stack position where the new value should be entered
*/
-static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos) {
+static void x87_set_st(x87_state *state, int reg_idx, ir_node *node, int pos)
+{
assert(0 < state->depth);
state->st[MASK_TOS(state->tos + pos)].reg_idx = reg_idx;
state->st[MASK_TOS(state->tos + pos)].node = node;
* @param reg_idx the vfp register index that should be set
* @param node the IR node that produces the value of the vfp register
*/
-static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_set_tos(x87_state *state, int reg_idx, ir_node *node)
+{
x87_set_st(state, reg_idx, node, 0);
} /* x87_set_tos */
* @param state the x87 state
* @param pos the stack position to change the tos with
*/
-static void x87_fxch(x87_state *state, int pos) {
+static void x87_fxch(x87_state *state, int pos)
+{
st_entry entry;
assert(pos < state->depth);
* @return the stack position where the register is stacked
* or -1 if the virtual register was not found
*/
-static int x87_on_stack(const x87_state *state, int reg_idx) {
+static int x87_on_stack(const x87_state *state, int reg_idx)
+{
int i, tos = state->tos;
for (i = 0; i < state->depth; ++i)
* @param reg_idx the register vfp index
* @param node the node that produces the value of the vfp register
*/
-static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_push_dbl(x87_state *state, int reg_idx, ir_node *node)
+{
assert(state->depth < N_x87_REGS && "stack overrun");
++state->depth;
* @param node the node that produces the value of the vfp register
* @param dbl_push if != 0 double pushes are allowed
*/
-static void x87_push(x87_state *state, int reg_idx, ir_node *node) {
+static void x87_push(x87_state *state, int reg_idx, ir_node *node)
+{
assert(x87_on_stack(state, reg_idx) == -1 && "double push");
x87_push_dbl(state, reg_idx, node);
*
* @param state the x87 state
*/
-static void x87_pop(x87_state *state) {
+static void x87_pop(x87_state *state)
+{
assert(state->depth > 0 && "stack underrun");
--state->depth;
*
* @param state the x87 state
*/
-static void x87_emms(x87_state *state) {
+static void x87_emms(x87_state *state)
+{
state->depth = 0;
state->tos = 0;
}
*
* @return the block state
*/
-static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block) {
+static blk_state *x87_get_bl_state(x87_simulator *sim, ir_node *block)
+{
pmap_entry *entry = pmap_find(sim->blk_states, block);
if (! entry) {
*
* @return a new x87 state
*/
-static x87_state *x87_alloc_state(x87_simulator *sim) {
+static x87_state *x87_alloc_state(x87_simulator *sim)
+{
x87_state *res = obstack_alloc(&sim->obst, sizeof(*res));
res->sim = sim;
*
* @return a cloned copy of the src state
*/
-static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src) {
+static x87_state *x87_clone_state(x87_simulator *sim, const x87_state *src)
+{
x87_state *res = x87_alloc_state(sim);
memcpy(res, src, sizeof(*res));
* @param n the IR node to patch
* @param op the x87 opcode to patch in
*/
-static ir_node *x87_patch_insn(ir_node *n, ir_op *op) {
+static ir_node *x87_patch_insn(ir_node *n, ir_op *op)
+{
ir_mode *mode = get_irn_mode(n);
ir_node *res = n;
* @param m the desired mode of the Proj
* @return The first Proj of mode @p m found or NULL.
*/
-static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m) {
+static ir_node *get_irn_Proj_for_mode(ir_node *n, ir_mode *m)
+{
const ir_edge_t *edge;
assert(get_irn_mode(n) == mode_T && "Need mode_T node");
/**
* Wrap the arch_* function here so we can check for errors.
*/
-static INLINE const arch_register_t *x87_get_irn_register(x87_simulator *sim, const ir_node *irn) {
- const arch_register_t *res;
+static INLINE const arch_register_t *x87_get_irn_register(const ir_node *irn)
+{
+ const arch_register_t *res = arch_get_irn_register(irn);
- res = arch_get_irn_register(sim->arch_env, irn);
assert(res->reg_class->regs == ia32_vfp_regs);
return res;
} /* x87_get_irn_register */
*
* @return the fxch node
*/
-static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block) {
+static ir_node *x87_fxch_shuffle(x87_state *state, int pos, ir_node *block)
+{
ir_node *fxch;
ia32_x87_attr_t *attr;
- fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block, mode_E);
+ fxch = new_rd_ia32_fxch(NULL, get_irn_irg(block), block);
attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
x87_fxch(state, pos);
- fxch = new_rd_ia32_fxch(NULL, irg, block, mode_E);
+ fxch = new_rd_ia32_fxch(NULL, irg, block);
attr = get_ia32_x87_attr(fxch);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
* @param pos push st(pos) on stack
* @param op_idx replace input op_idx of n with the fpush result
*/
-static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx) {
+static void x87_create_fpush(x87_state *state, ir_node *n, int pos, int op_idx)
+{
ir_node *fpush, *pred = get_irn_n(n, op_idx);
ia32_x87_attr_t *attr;
- const arch_register_t *out = x87_get_irn_register(state->sim, pred);
+ const arch_register_t *out = x87_get_irn_register(pred);
x87_push_dbl(state, arch_register_get_index(out), pred);
- fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
+ fpush = new_rd_ia32_fpush(NULL, get_irn_irg(n), get_nodes_block(n));
attr = get_ia32_x87_attr(fpush);
attr->x87[0] = &ia32_st_regs[pos];
attr->x87[2] = &ia32_st_regs[0];
*/
static ir_node *x87_create_fpop(x87_state *state, ir_node *n, int num)
{
- ir_node *fpop;
+ ir_node *fpop = NULL;
ia32_x87_attr_t *attr;
- int cpu = state->sim->isa->opt_arch;
+ assert(num > 0);
while (num > 0) {
x87_pop(state);
- if (ARCH_ATHLON(cpu))
- fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
+ if (ia32_cg_config.use_ffreep)
+ fpop = new_rd_ia32_ffreep(NULL, get_irn_irg(n), get_nodes_block(n));
else
- fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n), mode_E);
+ fpop = new_rd_ia32_fpop(NULL, get_irn_irg(n), get_nodes_block(n));
attr = get_ia32_x87_attr(fpop);
attr->x87[0] = &ia32_st_regs[0];
attr->x87[1] = &ia32_st_regs[0];
*
* @return the fldz node
*/
-static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx) {
+static ir_node *x87_create_fldz(x87_state *state, ir_node *n, int regidx)
+{
ir_graph *irg = get_irn_irg(n);
ir_node *block = get_nodes_block(n);
ir_node *fldz;
* Updates a live set over a single step from a given node to its predecessor.
* Everything defined at the node is removed from the set, the uses of the node get inserted.
*
- * @param sim The simulator handle.
* @param irn The node at which liveness should be computed.
* @param live The bitset of registers live before @p irn. This set gets modified by updating it to
* the registers live after irn.
*
* @return The live bitset.
*/
-static vfp_liveness vfp_liveness_transfer(x87_simulator *sim, ir_node *irn, vfp_liveness live)
+static vfp_liveness vfp_liveness_transfer(ir_node *irn, vfp_liveness live)
{
int i, n;
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
- const arch_env_t *arch_env = sim->arch_env;
if (get_irn_mode(irn) == mode_T) {
const ir_edge_t *edge;
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
- if (arch_irn_consider_in_reg_alloc(arch_env, cls, proj)) {
- const arch_register_t *reg = x87_get_irn_register(sim, proj);
+ if (arch_irn_consider_in_reg_alloc(cls, proj)) {
+ const arch_register_t *reg = x87_get_irn_register(proj);
live &= ~(1 << arch_register_get_index(reg));
}
}
}
- if (arch_irn_consider_in_reg_alloc(arch_env, cls, irn)) {
- const arch_register_t *reg = x87_get_irn_register(sim, irn);
+ if (arch_irn_consider_in_reg_alloc(cls, irn)) {
+ const arch_register_t *reg = x87_get_irn_register(irn);
live &= ~(1 << arch_register_get_index(reg));
}
for (i = 0, n = get_irn_arity(irn); i < n; ++i) {
ir_node *op = get_irn_n(irn, i);
- if (mode_is_float(get_irn_mode(op)) && arch_irn_consider_in_reg_alloc(arch_env, cls, op)) {
- const arch_register_t *reg = x87_get_irn_register(sim, op);
+ if (mode_is_float(get_irn_mode(op)) &&
+ arch_irn_consider_in_reg_alloc(cls, op)) {
+ const arch_register_t *reg = x87_get_irn_register(op);
live |= 1 << arch_register_get_index(reg);
}
}
int i;
vfp_liveness live = 0;
const arch_register_class_t *cls = &ia32_reg_classes[CLASS_ia32_vfp];
- const arch_env_t *arch_env = sim->arch_env;
const be_lv_t *lv = sim->lv;
be_lv_foreach(lv, block, be_lv_state_end, i) {
const arch_register_t *reg;
const ir_node *node = be_lv_get_irn(lv, block, i);
- if (!arch_irn_consider_in_reg_alloc(arch_env, cls, node))
+ if (!arch_irn_consider_in_reg_alloc(cls, node))
continue;
- reg = x87_get_irn_register(sim, node);
+ reg = x87_get_irn_register(node);
live |= 1 << arch_register_get_index(reg);
}
* @param lv the liveness handle
* @param block the block
*/
-static void update_liveness(x87_simulator *sim, ir_node *block) {
+static void update_liveness(x87_simulator *sim, ir_node *block)
+{
vfp_liveness live = vfp_liveness_end_of_block(sim, block);
unsigned idx;
ir_node *irn;
idx = get_irn_idx(irn);
sim->live[idx] = live;
- live = vfp_liveness_transfer(sim, irn, live);
+ live = vfp_liveness_transfer(irn, live);
}
idx = get_irn_idx(block);
sim->live[idx] = live;
*
* @param live the live bitset
*/
-static void vfp_dump_live(vfp_liveness live) {
+static void vfp_dump_live(vfp_liveness live)
+{
int i;
DB((dbg, LEVEL_2, "Live after: "));
*
* @return NO_NODE_ADDED
*/
-static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl) {
+static int sim_binop(x87_state *state, ir_node *n, const exchange_tmpl *tmpl)
+{
int op2_idx = 0, op1_idx;
int out_idx, do_pop = 0;
ia32_x87_attr_t *attr;
+ int permuted;
ir_node *patched_insn;
ir_op *dst;
x87_simulator *sim = state->sim;
ir_node *op1 = get_irn_n(n, n_ia32_binary_left);
ir_node *op2 = get_irn_n(n, n_ia32_binary_right);
- const arch_register_t *op1_reg = x87_get_irn_register(sim, op1);
- const arch_register_t *op2_reg = x87_get_irn_register(sim, op2);
- const arch_register_t *out = x87_get_irn_register(sim, n);
+ const arch_register_t *op1_reg = x87_get_irn_register(op1);
+ const arch_register_t *op2_reg = x87_get_irn_register(op2);
+ const arch_register_t *out = x87_get_irn_register(n);
int reg_index_1 = arch_register_get_index(op1_reg);
int reg_index_2 = arch_register_get_index(op2_reg);
vfp_liveness live = vfp_live_args_after(sim, n, REGMASK(out));
DB((dbg, LEVEL_1, "Stack before: "));
DEBUG_ONLY(x87_dump_stack(state));
- if(reg_index_1 == REG_VFP_UKNWN) {
+ if (reg_index_1 == REG_VFP_UKNWN) {
op1_idx = 0;
op1_live_after = 1;
} else {
op1_live_after = is_vfp_live(arch_register_get_index(op1_reg), live);
}
+ attr = get_ia32_x87_attr(n);
+ permuted = attr->attr.data.ins_permuted;
+
if (reg_index_2 != REG_VFP_NOREG) {
- if(reg_index_2 == REG_VFP_UKNWN) {
+ assert(!permuted);
+
+ if (reg_index_2 == REG_VFP_UKNWN) {
op2_idx = 0;
op2_live_after = 1;
} else {
/* first operand is live: push it here */
x87_create_fpush(state, n, op1_idx, n_ia32_binary_left);
op1_idx = 0;
- /* use fxxx (tos = tos X mem) */
- dst = tmpl->normal_op;
- out_idx = 0;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
-
- /* use fxxxp (tos = tos X mem) */
- dst = tmpl->normal_op;
- out_idx = 0;
}
+
+ /* use fxxx (tos = tos X mem) */
+ dst = permuted ? tmpl->reverse_op : tmpl->normal_op;
+ out_idx = 0;
}
patched_insn = x87_patch_insn(n, dst);
}
/* patch the operation */
- attr = get_ia32_x87_attr(n);
attr->x87[0] = op1_reg = &ia32_st_regs[op1_idx];
if (reg_index_2 != REG_VFP_NOREG) {
attr->x87[1] = op2_reg = &ia32_st_regs[op2_idx];
*
* @return NO_NODE_ADDED
*/
-static int sim_unop(x87_state *state, ir_node *n, ir_op *op) {
+static int sim_unop(x87_state *state, ir_node *n, ir_op *op)
+{
int op1_idx, out_idx;
x87_simulator *sim = state->sim;
- const arch_register_t *op1 = x87_get_irn_register(sim, get_irn_n(n, UNOP_IDX));
- const arch_register_t *out = x87_get_irn_register(sim, n);
+ const arch_register_t *op1 = x87_get_irn_register(get_irn_n(n, UNOP_IDX));
+ const arch_register_t *out = x87_get_irn_register(n);
ia32_x87_attr_t *attr;
unsigned live = vfp_live_args_after(sim, n, REGMASK(out));
*
* @return NO_NODE_ADDED
*/
-static int sim_load(x87_state *state, ir_node *n, ir_op *op) {
- const arch_register_t *out = x87_get_irn_register(state->sim, n);
+static int sim_load(x87_state *state, ir_node *n, ir_op *op)
+{
+ const arch_register_t *out = x87_get_irn_register(n);
ia32_x87_attr_t *attr;
DB((dbg, LEVEL_1, ">>> %+F -> %s\n", n, arch_register_get_name(out)));
x87_push(state, arch_register_get_index(out), x87_patch_insn(n, op));
- assert(out == x87_get_irn_register(state->sim, n));
+ assert(out == x87_get_irn_register(n));
attr = get_ia32_x87_attr(n);
attr->x87[2] = out = &ia32_st_regs[0];
DB((dbg, LEVEL_1, "<<< %s -> %s\n", get_irn_opname(n), arch_register_get_name(out)));
* @param old_val The former value
* @param new_val The new value
*/
-static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val) {
+static void collect_and_rewire_users(ir_node *store, ir_node *old_val, ir_node *new_val)
+{
const ir_edge_t *edge, *ne;
foreach_out_edge_safe(old_val, edge, ne) {
* @param op the x87 store opcode
* @param op_p the x87 store and pop opcode
*/
-static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p) {
- x87_simulator *sim = state->sim;
+static int sim_store(x87_state *state, ir_node *n, ir_op *op, ir_op *op_p)
+{
ir_node *val = get_irn_n(n, n_ia32_vfst_val);
- const arch_register_t *op2 = x87_get_irn_register(sim, val);
- unsigned live = vfp_live_args_after(sim, n, 0);
+ const arch_register_t *op2 = x87_get_irn_register(val);
+ unsigned live = vfp_live_args_after(state->sim, n, 0);
int insn = NO_NODE_ADDED;
ia32_x87_attr_t *attr;
int op2_reg_idx, op2_idx, depth;
op2_reg_idx = arch_register_get_index(op2);
if (op2_reg_idx == REG_VFP_UKNWN) {
/* just take any value from stack */
- if(state->depth > 0) {
+ if (state->depth > 0) {
op2_idx = 0;
DEBUG_ONLY(op2 = NULL);
live_after_node = 1;
Solution:
- stack not full: push value and fstp
- stack full: fstp value and load again
+ Note that we cannot test on mode_E, because floats might be 96bit ...
*/
- if (mode == mode_E) {
+ if (get_mode_size_bits(mode) > 64 || mode == mode_Ls) {
if (depth < N_x87_REGS) {
/* ok, we have a free register: push + fstp */
x87_create_fpush(state, n, op2_idx, n_ia32_vfst_val);
set_ia32_frame_ent(vfld, get_ia32_frame_ent(n));
if (is_ia32_use_frame(n))
set_ia32_use_frame(vfld);
- set_ia32_op_type(vfld, ia32_am_Source);
+ set_ia32_op_type(vfld, ia32_AddrModeS);
add_ia32_am_offs_int(vfld, get_ia32_am_offs_int(n));
set_ia32_am_sc(vfld, get_ia32_am_sc(n));
set_ia32_ls_mode(vfld, get_ia32_ls_mode(n));
assert(mem && "Store memory not found");
- arch_set_irn_register(sim->arch_env, rproj, op2);
+ arch_set_irn_register(rproj, op2);
/* reroute all former users of the store memory to the load memory */
edges_reroute(mem, mproj, irg);
GEN_STORE(fist)
/**
- * Simulate a fCondJmp.
- *
+* Simulate a virtual fisttp.
+*
+* @param state the x87 state
+* @param n the node that should be simulated (and patched)
+*/
+static int sim_fisttp(x87_state *state, ir_node *n)
+{
+ ir_node *val = get_irn_n(n, n_ia32_vfst_val);
+ const arch_register_t *op2 = x87_get_irn_register(val);
+ int insn = NO_NODE_ADDED;
+ ia32_x87_attr_t *attr;
+ int op2_reg_idx, op2_idx, depth;
+
+ op2_reg_idx = arch_register_get_index(op2);
+ if (op2_reg_idx == REG_VFP_UKNWN) {
+ /* just take any value from stack */
+ if (state->depth > 0) {
+ op2_idx = 0;
+ DEBUG_ONLY(op2 = NULL);
+ } else {
+ /* produce a new value which we will consume immediately */
+ x87_create_fldz(state, n, op2_reg_idx);
+ op2_idx = x87_on_stack(state, op2_reg_idx);
+ assert(op2_idx >= 0);
+ }
+ } else {
+ op2_idx = x87_on_stack(state, op2_reg_idx);
+ DB((dbg, LEVEL_1, ">>> %+F %s ->\n", n, arch_register_get_name(op2)));
+ assert(op2_idx >= 0);
+ }
+
+ depth = x87_get_depth(state);
+
+ /* Note: although the value is still live here, it is destroyed because
+ of the pop. The register allocator is aware of that and introduced a copy
+ if the value must be alive. */
+
+ /* we can only store the tos to memory */
+ if (op2_idx != 0)
+ x87_create_fxch(state, n, op2_idx);
+
+ x87_pop(state);
+ x87_patch_insn(n, op_ia32_fisttp);
+
+ attr = get_ia32_x87_attr(n);
+ attr->x87[1] = op2 = &ia32_st_regs[0];
+ DB((dbg, LEVEL_1, "<<< %s %s ->\n", get_irn_opname(n), arch_register_get_name(op2)));
+
+ return insn;
+} /* sim_fisttp */
+
+static int sim_FtstFnstsw(x87_state *state, ir_node *n)
+{
+ x87_simulator *sim = state->sim;
+ ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
+ ir_node *op1_node = get_irn_n(n, n_ia32_vFtstFnstsw_left);
+ const arch_register_t *reg1 = x87_get_irn_register(op1_node);
+ int reg_index_1 = arch_register_get_index(reg1);
+ int op1_idx = x87_on_stack(state, reg_index_1);
+ unsigned live = vfp_live_args_after(sim, n, 0);
+
+ DB((dbg, LEVEL_1, ">>> %+F %s\n", n, arch_register_get_name(reg1)));
+ DEBUG_ONLY(vfp_dump_live(live));
+ DB((dbg, LEVEL_1, "Stack before: "));
+ DEBUG_ONLY(x87_dump_stack(state));
+ assert(op1_idx >= 0);
+
+ if (op1_idx != 0) {
+ /* bring the value to tos */
+ x87_create_fxch(state, n, op1_idx);
+ op1_idx = 0;
+ }
+
+ /* patch the operation */
+ x87_patch_insn(n, op_ia32_FtstFnstsw);
+ reg1 = &ia32_st_regs[op1_idx];
+ attr->x87[0] = reg1;
+ attr->x87[1] = NULL;
+ attr->x87[2] = NULL;
+
+ if (!is_vfp_live(reg_index_1, live)) {
+ x87_create_fpop(state, sched_next(n), 1);
+ return NODE_ADDED;
+ }
+
+ return NO_NODE_ADDED;
+}
+
+/**
* @param state the x87 state
* @param n the node that should be simulated (and patched)
- *
- * @return NO_NODE_ADDED
*/
-static int sim_fCmpJmp(x87_state *state, ir_node *n) {
+static int sim_Fucom(x87_state *state, ir_node *n)
+{
int op1_idx;
int op2_idx = -1;
- int pop_cnt = 0;
- ia32_x87_attr_t *attr;
+ ia32_x87_attr_t *attr = get_ia32_x87_attr(n);
ir_op *dst;
x87_simulator *sim = state->sim;
- ir_node *op1_node = get_irn_n(n, n_ia32_vfCmpJmp_left);
- ir_node *op2_node = get_irn_n(n, n_ia32_vfCmpJmp_right);
- const arch_register_t *op1 = x87_get_irn_register(sim, op1_node);
- const arch_register_t *op2 = x87_get_irn_register(sim, op2_node);
+ ir_node *op1_node = get_irn_n(n, n_ia32_vFucomFnstsw_left);
+ ir_node *op2_node = get_irn_n(n, n_ia32_vFucomFnstsw_right);
+ const arch_register_t *op1 = x87_get_irn_register(op1_node);
+ const arch_register_t *op2 = x87_get_irn_register(op2_node);
int reg_index_1 = arch_register_get_index(op1);
int reg_index_2 = arch_register_get_index(op2);
unsigned live = vfp_live_args_after(sim, n, 0);
+ int permuted = attr->attr.data.ins_permuted;
+ int xchg = 0;
+ int pops = 0;
+ int node_added = NO_NODE_ADDED;
DB((dbg, LEVEL_1, ">>> %+F %s, %s\n", n,
arch_register_get_name(op1), arch_register_get_name(op2)));
op2_idx = x87_on_stack(state, reg_index_2);
assert(op2_idx >= 0);
- if (is_vfp_live(arch_register_get_index(op2), live)) {
+ if (is_vfp_live(reg_index_2, live)) {
/* second operand is live */
- if (is_vfp_live(arch_register_get_index(op1), live)) {
+ if (is_vfp_live(reg_index_1, live)) {
/* both operands are live */
if (op1_idx == 0) {
/* res = tos X op */
- dst = op_ia32_fcomJmp;
} else if (op2_idx == 0) {
/* res = op X tos */
- dst = op_ia32_fcomrJmp;
+ permuted = !permuted;
+ xchg = 1;
} else {
/* bring the first one to tos */
x87_create_fxch(state, n, op1_idx);
op2_idx = op1_idx;
op1_idx = 0;
/* res = tos X op */
- dst = op_ia32_fcomJmp;
}
} else {
/* second live, first operand is dead here, bring it to tos.
op1_idx = 0;
}
/* res = tos X op, pop */
- dst = op_ia32_fcompJmp;
- pop_cnt = 1;
+ pops = 1;
}
} else {
/* second operand is dead */
- if (is_vfp_live(arch_register_get_index(op1), live)) {
+ if (is_vfp_live(reg_index_1, live)) {
/* first operand is live: bring second to tos.
This means further, op1_idx != op2_idx. */
assert(op1_idx != op2_idx);
op2_idx = 0;
}
/* res = op X tos, pop */
- dst = op_ia32_fcomrpJmp;
- pop_cnt = 1;
+ pops = 1;
+ permuted = !permuted;
+ xchg = 1;
} else {
/* both operands are dead here, check first for identity. */
if (op1_idx == op2_idx) {
op2_idx = 0;
}
/* res = tos X op, pop */
- dst = op_ia32_fcompJmp;
- pop_cnt = 1;
+ pops = 1;
}
/* different, move them to st and st(1) and pop both.
The tricky part is to get one into st(1).*/
op1_idx = 0;
}
/* res = tos X op, pop, pop */
- dst = op_ia32_fcomppJmp;
- pop_cnt = 2;
+ pops = 2;
} else if (op1_idx == 1) {
/* good, first operand is already in the right place, move the second */
if (op2_idx != 0) {
assert(op1_idx != 0);
op2_idx = 0;
}
- dst = op_ia32_fcomrppJmp;
- pop_cnt = 2;
+ /* res = op X tos, pop, pop */
+ permuted = !permuted;
+ xchg = 1;
+ pops = 2;
} else {
/* if one is already the TOS, we need two fxch */
if (op1_idx == 0) {
x87_create_fxch(state, n, op2_idx);
op2_idx = 0;
/* res = op X tos, pop, pop */
- dst = op_ia32_fcomrppJmp;
- pop_cnt = 2;
+ pops = 2;
+ permuted = !permuted;
+ xchg = 1;
} else if (op2_idx == 0) {
/* second one is TOS, move to st(1) */
x87_create_fxch(state, n, 1);
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
/* res = tos X op, pop, pop */
- dst = op_ia32_fcomppJmp;
- pop_cnt = 2;
+ pops = 2;
} else {
/* none of them is either TOS or st(1), 3 fxch needed */
x87_create_fxch(state, n, op2_idx);
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
/* res = tos X op, pop, pop */
- dst = op_ia32_fcomppJmp;
- pop_cnt = 2;
+ pops = 2;
}
}
}
}
} else {
/* second operand is an address mode */
- if (is_vfp_live(arch_register_get_index(op1), live)) {
+ if (is_vfp_live(reg_index_1, live)) {
/* first operand is live: bring it to TOS */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
- dst = op_ia32_fcomJmp;
} else {
/* first operand is dead: bring it to tos */
if (op1_idx != 0) {
x87_create_fxch(state, n, op1_idx);
op1_idx = 0;
}
- dst = op_ia32_fcompJmp;
- pop_cnt = 1;
+ pops = 1;
+ }
+ }
+
+ /* patch the operation */
+ if (is_ia32_vFucomFnstsw(n)) {
+ int i;
+
+ switch (pops) {
+ case 0: dst = op_ia32_FucomFnstsw; break;
+ case 1: dst = op_ia32_FucompFnstsw; break;
+ case 2: dst = op_ia32_FucomppFnstsw; break;
+ default: panic("invalid popcount in sim_Fucom");
+ }
+
+ for (i = 0; i < pops; ++i) {
+ x87_pop(state);
}
+ } else if (is_ia32_vFucomi(n)) {
+ switch (pops) {
+ case 0: dst = op_ia32_Fucomi; break;
+ case 1: dst = op_ia32_Fucompi; x87_pop(state); break;
+ case 2:
+ dst = op_ia32_Fucompi;
+ x87_pop(state);
+ x87_create_fpop(state, sched_next(n), 1);
+ node_added = NODE_ADDED;
+ break;
+ default: panic("invalid popcount in sim_Fucom");
+ }
+ } else {
+ panic("invalid operation %+F in sim_FucomFnstsw", n);
}
x87_patch_insn(n, dst);
- assert(pop_cnt < 3);
- if (pop_cnt >= 2)
- x87_pop(state);
- if (pop_cnt >= 1)
- x87_pop(state);
+ if (xchg) {
+ int tmp = op1_idx;
+ op1_idx = op2_idx;
+ op2_idx = tmp;
+ }
- /* patch the operation */
- attr = get_ia32_x87_attr(n);
op1 = &ia32_st_regs[op1_idx];
attr->x87[0] = op1;
if (op2_idx >= 0) {
attr->x87[1] = op2;
}
attr->x87[2] = NULL;
+ attr->attr.data.ins_permuted = permuted;
- if (op2_idx >= 0)
+ if (op2_idx >= 0) {
DB((dbg, LEVEL_1, "<<< %s %s, %s\n", get_irn_opname(n),
arch_register_get_name(op1), arch_register_get_name(op2)));
- else
+ } else {
DB((dbg, LEVEL_1, "<<< %s %s, [AM]\n", get_irn_opname(n),
arch_register_get_name(op1)));
+ }
- return NO_NODE_ADDED;
-} /* sim_fCondJmp */
+ return node_added;
+}
-static
-int sim_Keep(x87_state *state, ir_node *node)
+static int sim_Keep(x87_state *state, ir_node *node)
{
const ir_node *op;
const arch_register_t *op_reg;
DB((dbg, LEVEL_1, ">>> %+F\n", node));
arity = get_irn_arity(node);
- for(i = 0; i < arity; ++i) {
+ for (i = 0; i < arity; ++i) {
op = get_irn_n(node, i);
- op_reg = arch_get_irn_register(state->sim->arch_env, op);
- if(arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
+ op_reg = arch_get_irn_register(op);
+ if (arch_register_get_class(op_reg) != &ia32_reg_classes[CLASS_ia32_vfp])
continue;
reg_id = arch_register_get_index(op_reg);
live = vfp_live_args_after(state->sim, node, 0);
op_stack_idx = x87_on_stack(state, reg_id);
- if(op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
+ if (op_stack_idx >= 0 && !is_vfp_live(reg_id, live)) {
x87_create_fpop(state, sched_next(node), 1);
node_added = NODE_ADDED;
}
return node_added;
}
-static
-void keep_float_node_alive(x87_state *state, ir_node *node)
+static void keep_float_node_alive(ir_node *node)
{
ir_graph *irg;
ir_node *block;
irg = get_irn_irg(node);
block = get_nodes_block(node);
- cls = arch_get_irn_reg_class(state->sim->arch_env, node, -1);
+ cls = arch_get_irn_reg_class(node, -1);
in[0] = node;
keep = be_new_Keep(cls, irg, block, 1, in);
*
* @return the copy of n
*/
-static ir_node *create_Copy(x87_state *state, ir_node *n) {
- x87_simulator *sim = state->sim;
+static ir_node *create_Copy(x87_state *state, ir_node *n)
+{
ir_graph *irg = get_irn_irg(n);
dbg_info *n_dbg = get_irn_dbg_info(n);
ir_mode *mode = get_irn_mode(n);
break;
}
- out = x87_get_irn_register(sim, n);
- op1 = x87_get_irn_register(sim, pred);
+ out = x87_get_irn_register(n);
+ op1 = x87_get_irn_register(pred);
if (cnstr != NULL) {
/* copy a constant */
attr->x87[0] = &ia32_st_regs[op1_idx];
attr->x87[2] = &ia32_st_regs[0];
}
- arch_set_irn_register(sim->arch_env, res, out);
+ arch_set_irn_register(res, out);
return res;
} /* create_Copy */
*
* @return NO_NODE_ADDED
*/
-static int sim_Copy(x87_state *state, ir_node *n) {
- x87_simulator *sim = state->sim;
+static int sim_Copy(x87_state *state, ir_node *n)
+{
ir_node *pred;
const arch_register_t *out;
const arch_register_t *op1;
- const arch_register_class_t *class;
+ const arch_register_class_t *cls;
ir_node *node, *next;
ia32_x87_attr_t *attr;
int op1_idx, out_idx;
unsigned live;
- class = arch_get_irn_reg_class(sim->arch_env, n, -1);
- if (class->regs != ia32_vfp_regs)
+ cls = arch_get_irn_reg_class(n, -1);
+ if (cls->regs != ia32_vfp_regs)
return 0;
pred = get_irn_n(n, 0);
- out = x87_get_irn_register(sim, n);
- op1 = x87_get_irn_register(sim, pred);
- live = vfp_live_args_after(sim, n, REGMASK(out));
+ out = x87_get_irn_register(n);
+ op1 = x87_get_irn_register(pred);
+ live = vfp_live_args_after(state->sim, n, REGMASK(out));
DB((dbg, LEVEL_1, ">>> %+F %s -> %s\n", n,
arch_register_get_name(op1), arch_register_get_name(out)));
sched_add_before(next, node);
DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
- arch_get_irn_register(sim->arch_env, node)->name));
+ arch_get_irn_register(node)->name));
return NO_NODE_ADDED;
}
exchange(n, node);
sched_add_before(next, node);
- if(get_irn_n_edges(pred) == 0) {
- keep_float_node_alive(state, pred);
+ if (get_irn_n_edges(pred) == 0) {
+ keep_float_node_alive(pred);
}
- DB((dbg, LEVEL_1, "<<< %+F %s -> %s\n", node, op1->name,
- arch_get_irn_register(sim->arch_env, node)->name));
+ DB((dbg, LEVEL_1, "<<< %+F %s -> ?\n", node, op1->name));
} else {
out_idx = x87_on_stack(state, arch_register_get_index(out));
/**
* Returns the result proj of the call
*/
-static ir_node *get_call_result_proj(ir_node *call) {
+static ir_node *get_call_result_proj(ir_node *call)
+{
const ir_edge_t *edge;
/* search the result proj */
ir_node *proj = get_edge_src_irn(edge);
long pn = get_Proj_proj(proj);
- if (pn == pn_be_Call_first_res) {
+ if (pn == pn_ia32_Call_vf0) {
return proj;
}
}
} /* get_call_result_proj */
/**
- * Simulate a be_Call.
+ * Simulate a ia32_Call.
*
* @param state the x87 state
* @param n the node that should be simulated
- * @param arch_env the architecture environment
*
* @return NO_NODE_ADDED
*/
-static int sim_Call(x87_state *state, ir_node *n, const arch_env_t *arch_env)
+static int sim_Call(x87_state *state, ir_node *n)
{
- ir_type *call_tp = be_Call_get_type(n);
+ ir_type *call_tp = get_ia32_call_attr_const(n)->call_tp;
ir_type *res_type;
ir_mode *mode;
ir_node *resproj;
const arch_register_t *reg;
- (void) arch_env;
DB((dbg, LEVEL_1, ">>> %+F\n", n));
resproj = get_call_result_proj(n);
assert(resproj != NULL);
- reg = x87_get_irn_register(state->sim, resproj);
+ reg = x87_get_irn_register(resproj);
x87_push(state, arch_register_get_index(reg), resproj);
end_call:
*
* Should not happen, spills are lowered before x87 simulator see them.
*/
-static int sim_Spill(x87_state *state, ir_node *n) {
+static int sim_Spill(x87_state *state, ir_node *n)
+{
assert(0 && "Spill not lowered");
return sim_fst(state, n);
} /* sim_Spill */
*
* Should not happen, reloads are lowered before x87 simulator see them.
*/
-static int sim_Reload(x87_state *state, ir_node *n) {
+static int sim_Reload(x87_state *state, ir_node *n)
+{
assert(0 && "Reload not lowered");
return sim_fld(state, n);
} /* sim_Reload */
*
* @return NO_NODE_ADDED
*/
-static int sim_Return(x87_state *state, ir_node *n) {
+static int sim_Return(x87_state *state, ir_node *n)
+{
int n_res = be_Return_get_n_rets(n);
int i, n_float_res = 0;
- /* only floating point return values must resist on stack */
+ /* only floating point return values must reside on stack */
for (i = 0; i < n_res; ++i) {
ir_node *res = get_irn_n(n, be_pos_Return_val + i);
*
* @return NO_NODE_ADDED
*/
-static int sim_Perm(x87_state *state, ir_node *irn) {
+static int sim_Perm(x87_state *state, ir_node *irn)
+{
int i, n;
- x87_simulator *sim = state->sim;
ir_node *pred = get_irn_n(irn, 0);
int *stack_pos;
const ir_edge_t *edge;
/* collect old stack positions */
for (i = 0; i < n; ++i) {
- const arch_register_t *inreg = x87_get_irn_register(sim, get_irn_n(irn, i));
+ const arch_register_t *inreg = x87_get_irn_register(get_irn_n(irn, i));
int idx = x87_on_stack(state, arch_register_get_index(inreg));
assert(idx >= 0 && "Perm argument not on x87 stack");
/* now do the permutation */
foreach_out_edge(irn, edge) {
ir_node *proj = get_edge_src_irn(edge);
- const arch_register_t *out = x87_get_irn_register(sim, proj);
+ const arch_register_t *out = x87_get_irn_register(proj);
long num = get_Proj_proj(proj);
assert(0 <= num && num < n && "More Proj's than Perm inputs");
return NO_NODE_ADDED;
} /* sim_Perm */
-static int sim_Barrier(x87_state *state, ir_node *node) {
- //const arch_env_t *arch_env = state->sim->arch_env;
+static int sim_Barrier(x87_state *state, ir_node *node)
+{
int i, arity;
/* materialize unknown if needed */
arity = get_irn_arity(node);
- for(i = 0; i < arity; ++i) {
+ for (i = 0; i < arity; ++i) {
const arch_register_t *reg;
ir_node *zero;
ir_node *block;
ia32_x87_attr_t *attr;
ir_node *in = get_irn_n(node, i);
- if(!is_ia32_Unknown_VFP(in))
+ if (!is_ia32_Unknown_VFP(in))
continue;
/* TODO: not completely correct... */
*
* @return the x87 state after dead register killed
*/
-static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state) {
+static x87_state *x87_kill_deads(x87_simulator *sim, ir_node *block, x87_state *start_state)
+{
x87_state *state = start_state;
ir_node *first_insn = sched_first(block);
ir_node *keep = NULL;
DEBUG_ONLY(x87_dump_stack(state));
if (kill_mask != 0 && live == 0) {
- int cpu = sim->isa->arch;
-
/* special case: kill all registers */
- if (ARCH_ATHLON(sim->isa->opt_arch) && ARCH_MMX(cpu)) {
- if (ARCH_AMD(cpu)) {
+ if (ia32_cg_config.use_femms || ia32_cg_config.use_emms) {
+ if (ia32_cg_config.use_femms) {
/* use FEMMS on AMD processors to clear all */
- keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block, mode_E);
+ keep = new_rd_ia32_femms(NULL, get_irn_irg(block), block);
} else {
/* use EMMS to clear all */
- keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block, mode_E);
+ keep = new_rd_ia32_emms(NULL, get_irn_irg(block), block);
}
sched_add_before(first_insn, keep);
keep_alive(keep);
const arch_register_t *reg;
ia32_x87_attr_t *attr;
- if(!is_Phi(node))
+ if (!is_Phi(node))
break;
op = get_Phi_pred(node, pos);
- if(!is_ia32_Unknown_VFP(op))
+ if (!is_ia32_Unknown_VFP(op))
continue;
- reg = arch_get_irn_register(state->sim->arch_env, node);
+ reg = arch_get_irn_register(node);
/* create a zero at end of pred block */
zero = new_rd_ia32_fldz(NULL, current_ir_graph, pred_block, mode_E);
* @param sim the simulator handle
* @param block the current block
*/
-static void x87_simulate_block(x87_simulator *sim, ir_node *block) {
+static void x87_simulate_block(x87_simulator *sim, ir_node *block)
+{
ir_node *n, *next;
blk_state *bl_state = x87_get_bl_state(sim, block);
x87_state *state = bl_state->begin;
bl_state->end = state;
} /* x87_simulate_block */
+static void register_sim(ir_op *op, sim_func func)
+{
+ assert(op->ops.generic == NULL);
+ op->ops.generic = (op_func) func;
+}
+
/**
* Create a new x87 simulator.
*
* @param sim a simulator handle, will be initialized
* @param irg the current graph
- * @param arch_env the architecture environment
*/
-static void x87_init_simulator(x87_simulator *sim, ir_graph *irg,
- const arch_env_t *arch_env)
+static void x87_init_simulator(x87_simulator *sim, ir_graph *irg)
{
obstack_init(&sim->obst);
sim->blk_states = pmap_create();
- sim->arch_env = arch_env;
sim->n_idx = get_irg_last_idx(irg);
sim->live = obstack_alloc(&sim->obst, sizeof(*sim->live) * sim->n_idx);
- sim->isa = (ia32_isa_t *)arch_env->isa;
DB((dbg, LEVEL_1, "--------------------------------\n"
"x87 Simulator started for %+F\n", irg));
/* set the generic function pointer of instruction we must simulate */
clear_irp_opcodes_generic_func();
-#define ASSOC(op) (op_ ## op)->ops.generic = (op_func)(sim_##op)
-#define ASSOC_IA32(op) (op_ia32_v ## op)->ops.generic = (op_func)(sim_##op)
-#define ASSOC_BE(op) (op_be_ ## op)->ops.generic = (op_func)(sim_##op)
- ASSOC_IA32(fld);
- ASSOC_IA32(fild);
- ASSOC_IA32(fld1);
- ASSOC_IA32(fldz);
- ASSOC_IA32(fadd);
- ASSOC_IA32(fsub);
- ASSOC_IA32(fmul);
- ASSOC_IA32(fdiv);
- ASSOC_IA32(fprem);
- ASSOC_IA32(fabs);
- ASSOC_IA32(fchs);
- ASSOC_IA32(fist);
- ASSOC_IA32(fst);
- ASSOC_IA32(fCmpJmp);
- ASSOC_BE(Copy);
- ASSOC_BE(Call);
- ASSOC_BE(Spill);
- ASSOC_BE(Reload);
- ASSOC_BE(Return);
- ASSOC_BE(Perm);
- ASSOC_BE(Keep);
- ASSOC_BE(Barrier);
-#undef ASSOC_BE
-#undef ASSOC_IA32
-#undef ASSOC
+ register_sim(op_ia32_Call, sim_Call);
+ register_sim(op_ia32_vfld, sim_fld);
+ register_sim(op_ia32_vfild, sim_fild);
+ register_sim(op_ia32_vfld1, sim_fld1);
+ register_sim(op_ia32_vfldz, sim_fldz);
+ register_sim(op_ia32_vfadd, sim_fadd);
+ register_sim(op_ia32_vfsub, sim_fsub);
+ register_sim(op_ia32_vfmul, sim_fmul);
+ register_sim(op_ia32_vfdiv, sim_fdiv);
+ register_sim(op_ia32_vfprem, sim_fprem);
+ register_sim(op_ia32_vfabs, sim_fabs);
+ register_sim(op_ia32_vfchs, sim_fchs);
+ register_sim(op_ia32_vfist, sim_fist);
+ register_sim(op_ia32_vfisttp, sim_fisttp);
+ register_sim(op_ia32_vfst, sim_fst);
+ register_sim(op_ia32_vFtstFnstsw, sim_FtstFnstsw);
+ register_sim(op_ia32_vFucomFnstsw, sim_Fucom);
+ register_sim(op_ia32_vFucomi, sim_Fucom);
+ register_sim(op_be_Copy, sim_Copy);
+ register_sim(op_be_Spill, sim_Spill);
+ register_sim(op_be_Reload, sim_Reload);
+ register_sim(op_be_Return, sim_Return);
+ register_sim(op_be_Perm, sim_Perm);
+ register_sim(op_be_Keep, sim_Keep);
+ register_sim(op_be_Barrier, sim_Barrier);
} /* x87_init_simulator */
/**
*
* @param sim the simulator handle
*/
-static void x87_destroy_simulator(x87_simulator *sim) {
+static void x87_destroy_simulator(x87_simulator *sim)
+{
pmap_destroy(sim->blk_states);
obstack_free(&sim->obst, NULL);
DB((dbg, LEVEL_1, "x87 Simulator stopped\n\n"));
* Pre-block walker: calculate the liveness information for the block
* and store it into the sim->live cache.
*/
-static void update_liveness_walker(ir_node *block, void *data) {
+static void update_liveness_walker(ir_node *block, void *data)
+{
x87_simulator *sim = data;
update_liveness(sim, block);
} /* update_liveness_walker */
-/**
- * Run a simulation and fix all virtual instructions for a graph.
- *
- * @param env the architecture environment
- * @param irg the current graph
- *
- * Needs a block-schedule.
- */
-void x87_simulate_graph(const arch_env_t *arch_env, be_irg_t *birg) {
+void x87_simulate_graph(be_irg_t *birg)
+{
+ /* TODO improve code quality (less executed fxch) by using execfreqs */
+
ir_node *block, *start_block;
blk_state *bl_state;
x87_simulator sim;
ir_graph *irg = be_get_birg_irg(birg);
/* create the simulator */
- x87_init_simulator(&sim, irg, arch_env);
+ x87_init_simulator(&sim, irg);
start_block = get_irg_start_block(irg);
bl_state = x87_get_bl_state(&sim, start_block);
x87_destroy_simulator(&sim);
} /* x87_simulate_graph */
-void ia32_init_x87(void) {
+void ia32_init_x87(void)
+{
FIRM_DBG_REGISTER(dbg, "firm.be.ia32.x87");
} /* ia32_init_x87 */
projects / libfirm / blobdiff