Remove dead code: tarval_is_long() returns true for mode_P null constants.

[libfirm] / ir / be / ia32 / ia32_transform.c

diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c
index face275..f0d8e56 100644 (file)
--- a/ir/be/ia32/ia32_transform.c
+++ b/ir/be/ia32/ia32_transform.c
@@ -222,17 +222,11 @@ static ir_entity *ia32_get_entity_for_tv(ia32_isa_t *isa, ir_node *cnst)
 }
 
 static int is_Const_0(ir_node *node) {
-       if(!is_Const(node))
-               return 0;
-
-       return classify_Const(node) == CNST_NULL;
+       return is_Const(node) && is_Const_null(node);
 }
 
 static int is_Const_1(ir_node *node) {
-       if(!is_Const(node))
-               return 0;
-
-       return classify_Const(node) == CNST_ONE;
+       return is_Const(node) && is_Const_one(node);
 }
 
 static int is_Const_Minus_1(ir_node *node) {
@@ -248,7 +242,7 @@ static int is_Const_Minus_1(ir_node *node) {
        tv = get_Const_tarval(node);
        tv = tarval_neg(tv);
 
-       return classify_tarval(tv) == CNST_ONE;
+       return tarval_is_one(tv);
 }
 
 /**
@@ -267,10 +261,9 @@ static ir_node *gen_Const(ir_node *node) {
                ir_node   *nomem = new_NoMem();
                ir_node   *load;
                ir_entity *floatent;
-               cnst_classify_t clss = classify_Const(node);
 
                if (USE_SSE2(env_cg)) {
-                       if (clss == CNST_NULL) {
+                       if (is_Const_null(node)) {
                                load = new_rd_ia32_xZero(dbgi, irg, block);
                                set_ia32_ls_mode(load, mode);
                                res  = load;
@@ -285,10 +278,10 @@ static ir_node *gen_Const(ir_node *node) {
                                res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
                        }
                } else {
-                       if (clss == CNST_NULL) {
+                       if (is_Const_null(node)) {
                                load = new_rd_ia32_vfldz(dbgi, irg, block);
                                res  = load;
-                       } else if (clss == CNST_ONE) {
+                       } else if (is_Const_one(node)) {
                                load = new_rd_ia32_vfld1(dbgi, irg, block);
                                res  = load;
                        } else {
@@ -482,12 +475,6 @@ static int use_source_address_mode(ir_node *block, ir_node *node,
        mode = get_irn_mode(node);
        if(!mode_needs_gp_reg(mode))
                return 0;
-       /*
-        * Matze: the unresolved question here is wether 8/16bit operations
-        * are a good idea if they define registers (as writing to an 8/16
-        * bit reg is bad on modern cpu as it confuses the dependency calculation
-        * for the full reg)
-        */
        if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
                return 0;
 
@@ -1776,6 +1763,10 @@ static ir_node *try_create_dest_am(ir_node *node) {
        if(!mode_needs_gp_reg(mode))
                return NULL;
 
+       /* TODO0000 8bit operations have stricter constraints. This is not handled yet */
+       if (get_mode_size_bits(mode) < 16)
+               return NULL;
+
        /* store must be the only user of the val node */
        if(get_irn_n_edges(val) > 1)
                return NULL;
@@ -2839,8 +2830,6 @@ ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
                offset = get_Const_tarval(cnst);
                if(tarval_is_long(offset)) {
                        val = get_tarval_long(offset);
-               } else if(tarval_is_null(offset)) {
-                       val = 0;
                } else {
                        ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
                                   "long?\n", cnst);