#include "array_t.h"
#include "height.h"
-#include "../benode_t.h"
+#include "../benode.h"
#include "../besched.h"
#include "../beabi.h"
#include "../beutil.h"
-#include "../beirg_t.h"
+#include "../beirg.h"
#include "../betranshlp.h"
#include "../be_t.h"
* @param mode the mode for the float type (might be integer mode for SSE2 types)
* @param align alignment
*/
-static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align) {
- char buf[32];
+static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
+{
ir_type *tp;
assert(align <= 16);
static ir_type *int_Iu[16] = {NULL, };
if (int_Iu[align] == NULL) {
- snprintf(buf, sizeof(buf), "int_Iu_%u", align);
- int_Iu[align] = tp = new_type_primitive(new_id_from_str(buf), mode);
+ int_Iu[align] = tp = new_type_primitive(mode);
/* set the specified alignment */
set_type_alignment_bytes(tp, align);
}
static ir_type *int_Lu[16] = {NULL, };
if (int_Lu[align] == NULL) {
- snprintf(buf, sizeof(buf), "int_Lu_%u", align);
- int_Lu[align] = tp = new_type_primitive(new_id_from_str(buf), mode);
+ int_Lu[align] = tp = new_type_primitive(mode);
/* set the specified alignment */
set_type_alignment_bytes(tp, align);
}
static ir_type *float_F[16] = {NULL, };
if (float_F[align] == NULL) {
- snprintf(buf, sizeof(buf), "float_F_%u", align);
- float_F[align] = tp = new_type_primitive(new_id_from_str(buf), mode);
+ float_F[align] = tp = new_type_primitive(mode);
/* set the specified alignment */
set_type_alignment_bytes(tp, align);
}
static ir_type *float_D[16] = {NULL, };
if (float_D[align] == NULL) {
- snprintf(buf, sizeof(buf), "float_D_%u", align);
- float_D[align] = tp = new_type_primitive(new_id_from_str(buf), mode);
+ float_D[align] = tp = new_type_primitive(mode);
/* set the specified alignment */
set_type_alignment_bytes(tp, align);
}
static ir_type *float_E[16] = {NULL, };
if (float_E[align] == NULL) {
- snprintf(buf, sizeof(buf), "float_E_%u", align);
- float_E[align] = tp = new_type_primitive(new_id_from_str(buf), mode);
+ float_E[align] = tp = new_type_primitive(mode);
/* set the specified alignment */
set_type_alignment_bytes(tp, align);
}
*
* @param tp the atomic type
*/
-static ir_type *ia32_create_float_array(ir_type *tp) {
- char buf[32];
+static ir_type *ia32_create_float_array(ir_type *tp)
+{
ir_mode *mode = get_type_mode(tp);
unsigned align = get_type_alignment_bytes(tp);
ir_type *arr;
if (float_F[align] != NULL)
return float_F[align];
- snprintf(buf, sizeof(buf), "arr_float_F_%u", align);
- arr = float_F[align] = new_type_array(new_id_from_str(buf), 1, tp);
+ arr = float_F[align] = new_type_array(1, tp);
} else if (mode == mode_D) {
static ir_type *float_D[16] = {NULL, };
if (float_D[align] != NULL)
return float_D[align];
- snprintf(buf, sizeof(buf), "arr_float_D_%u", align);
- arr = float_D[align] = new_type_array(new_id_from_str(buf), 1, tp);
+ arr = float_D[align] = new_type_array(1, tp);
} else {
static ir_type *float_E[16] = {NULL, };
if (float_E[align] != NULL)
return float_E[align];
- snprintf(buf, sizeof(buf), "arr_float_E_%u", align);
- arr = float_E[align] = new_type_array(new_id_from_str(buf), 1, tp);
+ arr = float_E[align] = new_type_array(1, tp);
}
set_type_alignment_bytes(arr, align);
set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
}
am->op_type = ia32_AddrModeS;
} else {
+ ir_mode *mode;
am->op_type = ia32_Normal;
if (flags & match_try_am) {
return;
}
- new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
- if (new_op2 == NULL)
- new_op2 = be_transform_node(op2);
- am->ls_mode =
- (flags & match_mode_neutral ? mode_Iu : get_irn_mode(op2));
+ mode = get_irn_mode(op2);
+ if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
+ new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
+ if (new_op2 == NULL)
+ new_op2 = create_upconv(op2, NULL);
+ am->ls_mode = mode_Iu;
+ } else {
+ new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
+ if (new_op2 == NULL)
+ new_op2 = be_transform_node(op2);
+ am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
+ }
}
if (addr->base == NULL)
addr->base = noreg_GP;
ir_node *new_node;
ir_node *proj_res_high;
+ if (get_mode_size_bits(mode) != 32) {
+ panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
+ }
+
if (mode_is_signed(mode)) {
new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
panic("invalid divmod node %+F", node);
}
- match_arguments(&am, block, op1, op2, NULL, match_am);
+ match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
/* Beware: We don't need a Sync, if the memory predecessor of the Div node
is the memory of the consumed address. We can have only the second op as address
if (ia32_cg_config.use_fisttp) {
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
- const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp];
ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
ir_node *value = new_r_Proj(block, vfisttp, mode_E, pn_ia32_vfisttp_res);
- be_new_Keep(reg_class, block, 1, &value);
+ be_new_Keep(block, 1, &value);
new_node = new_r_Proj(block, vfisttp, mode_M, pn_ia32_vfisttp_M);
*fist = vfisttp;
switch_max = pn;
}
- if ((unsigned long) (switch_max - switch_min) > 256000) {
- panic("Size of switch %+F bigger than 256000", node);
+ if ((unsigned long) (switch_max - switch_min) > 128000) {
+ panic("Size of switch %+F bigger than 128000", node);
}
if (switch_min != 0) {
unsigned scale;
flags = get_flags_node(cond, &pnc);
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0);
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_permuted=*/0);
if (ia32_cg_config.use_sse2) {
/* cannot load from different mode on SSE */
assert(!mode_is_int(src_mode) || src_bits <= 32);
assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
+ /* modeB -> X should already be lowered by the lower_mode_b pass */
if (src_mode == mode_b) {
- assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode));
- /* nothing to do, we already model bools as 0/1 ints */
- return be_transform_node(op);
+ panic("ConvB not lowered %+F", node);
}
if (src_mode == tgt_mode) {
*/
static ir_node *gen_Phi(ir_node *node)
{
+ const arch_register_req_t *req;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
assert(get_mode_size_bits(mode) <= 32);
/* all integer operations are on 32bit registers now */
mode = mode_Iu;
+ req = ia32_reg_classes[CLASS_ia32_gp].class_req;
} else if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2) {
mode = mode_xmm;
+ req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
} else {
mode = mode_vfp;
+ req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
}
+ } else {
+ req = arch_no_register_req;
}
/* phi nodes allow loops, so we use the old arguments for now
copy_node_attr(node, phi);
be_duplicate_deps(node, phi);
+ arch_set_out_register_req(phi, 0, req);
+
be_enqueue_preds(node);
return phi;
}
+static ir_node *gen_Jmp(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_node;
+
+ new_node = new_bd_ia32_Jmp(dbgi, new_block);
+ SET_IA32_ORIG_NODE(new_node, node);
+
+ return new_node;
+}
+
/**
* Transform IJmp
*/
if (is_Const_0(lower)) {
/* typical case for Java */
ir_node *sub, *res, *flags, *block;
- ir_graph *irg = current_ir_graph;
res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
+ return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_vfld_X_exc);
default:
break;
}
static ir_node *gen_be_Call(ir_node *node)
{
dbg_info *const dbgi = get_irn_dbg_info(node);
- ir_graph *const irg = current_ir_graph;
ir_node *const src_block = get_nodes_block(node);
ir_node *const block = be_transform_node(src_block);
ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *call = get_Proj_pred(node);
ir_node *new_call = be_transform_node(call);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
ir_mode *mode = get_irn_mode(node);
assert(req->type & arch_register_req_type_limited);
for (i = 0; i < n_outs; ++i) {
- arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i);
+ arch_register_req_t const *const new_req
+ = arch_get_out_register_req(new_call, i);
if (!(new_req->type & arch_register_req_type_limited) ||
new_req->cls != req->cls ||
long pos = get_Proj_proj(node);
if (mode == mode_M) {
- pos = arch_irn_get_n_outs(new_pred) + 1;
+ pos = arch_irn_get_n_outs(new_pred)-1;
} else if (mode_is_int(mode) || mode_is_reference(mode)) {
mode = mode_Iu;
} else if (mode_is_float(mode)) {
GEN(Mux);
GEN(Proj);
GEN(Phi);
+ GEN(Jmp);
GEN(IJmp);
GEN(Bound);
continue;
}
- req = get_ia32_out_req(node, i);
+ req = arch_get_out_register_req(node, i);
cls = req->cls;
if (cls == NULL) {
continue;
if (last_keep != NULL) {
be_Keep_add_node(last_keep, cls, in[0]);
} else {
- last_keep = be_new_Keep(cls, block, 1, in);
+ last_keep = be_new_Keep(block, 1, in);
if (sched_is_scheduled(node)) {
sched_add_after(node, last_keep);
}
initial_fpcw = NULL;
no_pic_adjust = 0;
- BE_TIMER_PUSH(t_heights);
+ be_timer_push(T_HEIGHTS);
heights = heights_new(cg->irg);
- BE_TIMER_POP(t_heights);
+ be_timer_pop(T_HEIGHTS);
ia32_calculate_non_address_mode_nodes(cg->birg);
/* the transform phase is not safe for CSE (yet) because several nodes get
projects / libfirm / blobdiff