/**
* @file
- * @brief This file implements the IR transformation from firm into ia32-Firm.
+ * @brief This file implements the IR transformation from firm into
+ * ia32-Firm.
* @author Christian Wuerdig, Matthias Braun
* @version $Id$
*/
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
/** hold the current code generator during transformation */
-static ia32_code_gen_t *env_cg = NULL;
+static ia32_code_gen_t *env_cg = NULL;
+static ir_node *initial_fpcw = NULL;
extern ir_op *get_op_Mulh(void);
static ir_node *create_immediate_or_transform(ir_node *node,
char immediate_constraint_type);
+static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
+ dbg_info *dbgi, ir_node *new_block,
+ ir_node *new_op);
+
/**
* Return true if a mode can be stored in the GP register set
*/
* Transforms a Const.
*/
static ir_node *gen_Const(ir_node *node) {
- ir_graph *irg = current_ir_graph;
- ir_node *old_block = get_nodes_block(node);
- ir_node *block = be_transform_node(old_block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
+ ir_graph *irg = current_ir_graph;
+ ir_node *old_block = get_nodes_block(node);
+ ir_node *block = be_transform_node(old_block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
ir_node *res = NULL;
return new_node;
}
+static ir_node *get_fpcw(void)
+{
+ ir_node *fpcw;
+ if(initial_fpcw != NULL)
+ return initial_fpcw;
+
+ fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
+ &ia32_fp_cw_regs[REG_FPCW]);
+ initial_fpcw = be_transform_node(fpcw);
+
+ return initial_fpcw;
+}
+
/**
* Construct a standard binary operation, set AM and immediate if required.
*
ir_graph *irg = current_ir_graph;
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
- ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
- &ia32_fp_cw_regs[REG_FPCW]);
new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
- nomem, fpcw);
+ nomem, get_fpcw());
set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
if (is_op_commutative(get_irn_op(node))) {
set_ia32_commutative(new_node);
set_ia32_emit_cl(new_op);
+ /* lowered shift instruction may have a dependency operand, handle it here */
+ if (get_irn_arity(node) == 3) {
+ /* we have a dependency */
+ ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
+ add_irn_dep(new_op, new_dep);
+ }
+
return new_op;
}
static ir_node *gen_And(ir_node *node) {
ir_node *op1 = get_And_left(node);
ir_node *op2 = get_And_right(node);
+ assert(! mode_is_float(get_irn_mode(node)));
+
+ /* check for zero extension first */
+ if (is_Const(op2)) {
+ tarval *tv = get_Const_tarval(op2);
+ long v = get_tarval_long(tv);
+
+ if (v == 0xFF || v == 0xFFFF) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *new_op = be_transform_node(op1);
+ ir_mode *src_mode;
+ ir_node *res;
+
+ if(v == 0xFF) {
+ src_mode = mode_Bu;
+ } else {
+ assert(v == 0xFFFF);
+ src_mode = mode_Hu;
+ }
+ res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+
+ return res;
+ }
+ }
- assert (! mode_is_float(get_irn_mode(node)));
return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
}
if (mode_is_signed(mode)) {
/* in signed mode, we need to sign extend the dividend */
ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ add_irn_dep(produceval, get_irg_frame(irg));
sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
produceval);
} else {
}
set_ia32_ls_mode(new_op, mode);
} else {
- ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
- &ia32_fp_cw_regs[REG_FPCW]);
new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
- new_op2, nomem, fpcw);
+ new_op2, nomem, get_fpcw());
// Matze: disabled for now (spillslot coalescer fails)
set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
}
static ir_node *gen_Shrs(ir_node *node) {
ir_node *left = get_Shrs_left(node);
ir_node *right = get_Shrs_right(node);
- if(is_Const(right) && get_irn_mode(left) == mode_Is) {
+ ir_mode *mode = get_irn_mode(node);
+ if(is_Const(right) && mode == mode_Is) {
tarval *tv = get_Const_tarval(right);
long val = get_tarval_long(tv);
if(val == 31) {
ir_node *op = left;
ir_node *new_op = be_transform_node(op);
ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ add_irn_dep(pval, get_irg_frame(irg));
return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
}
}
+#if 1
+ /* 8 or 16 bit sign extension? */
+ if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
+ ir_node *shl_left = get_Shl_left(left);
+ ir_node *shl_right = get_Shl_right(left);
+ if(is_Const(shl_right)) {
+ tarval *tv1 = get_Const_tarval(right);
+ tarval *tv2 = get_Const_tarval(shl_right);
+ if(tv1 == tv2 && tarval_is_long(tv1)) {
+ long val = get_tarval_long(tv1);
+ if(val == 16 || val == 24) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *new_op = be_transform_node(shl_left);
+ ir_mode *src_mode;
+ ir_node *res;
+
+ if(val == 24) {
+ src_mode = mode_Bs;
+ } else {
+ assert(val == 16);
+ src_mode = mode_Hs;
+ }
+ res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
+ new_op);
+ SET_IA32_ORIG_NODE(res,
+ ia32_get_old_node_name(env_cg, node));
+
+ return res;
+ }
+ }
+ }
+ }
+#endif
return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
}
return gen_Minus_ex(node, get_Minus_op(node));
}
+static ir_node *create_Immediate_from_int(int val)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *start_block = get_irg_start_block(irg);
+ ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
+ arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
+
+ return immediate;
+}
+
static ir_node *gen_bin_Not(ir_node *node)
{
ir_graph *irg = current_ir_graph;
ir_node *new_op = be_transform_node(op);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
- ir_node *one = new_rd_ia32_Immediate(dbgi, irg, block, NULL, 0, 1);
- arch_set_irn_register(env_cg->arch_env, one, &ia32_gp_regs[REG_GP_NOREG]);
+ ir_node *one = create_Immediate_from_int(1);
return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
}
ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
pval);
+
+ add_irn_dep(pval, get_irg_frame(irg));
SET_IA32_ORIG_NODE(sign_extension,
ia32_get_old_node_name(env_cg, node));
res_mode = mode_vfp;
}
} else {
- new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
+ if(mode == mode_b)
+ mode = mode_Iu;
+
+ /* create a conv node with address mode for smaller modes */
+ if(get_mode_size_bits(mode) < 32) {
+ new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, lptr, noreg, noreg,
+ new_mem, mode);
+ } else {
+ new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
+ }
res_mode = mode_Iu;
}
}
} else {
new_val = create_immediate_or_transform(val, 0);
+ if(mode == mode_b)
+ mode = mode_Iu;
if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
return new_op;
}
+static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
+{
+ ir_mode *tgt_mode;
+ ir_node *block;
+
+ if(get_mode_size_bits(mode) == 32)
+ return new_op;
+ if(mode == mode_b)
+ return new_op;
+ if(is_ia32_Immediate(new_op))
+ return new_op;
+
+ if(mode_is_signed(mode))
+ tgt_mode = mode_Is;
+ else
+ tgt_mode = mode_Iu;
+
+ block = get_nodes_block(new_op);
+ return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
+}
+
static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
ir_node *cmp_left, ir_node *cmp_right)
{
ir_node *res;
ir_node *noreg;
ir_node *nomem;
+ ir_mode *mode;
long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
if(cmp_right != NULL && !is_Const_0(cmp_right))
and_left = get_And_left(cmp_left);
and_right = get_And_right(cmp_left);
+ mode = get_irn_mode(and_left);
new_cmp_left = be_transform_node(and_left);
new_cmp_right = create_immediate_or_transform(and_right, 0);
} else {
+ mode = get_irn_mode(cmp_left);
new_cmp_left = be_transform_node(cmp_left);
new_cmp_right = be_transform_node(cmp_left);
}
- noreg = ia32_new_NoReg_gp(env_cg);
- nomem = new_NoMem();
+ assert(get_mode_size_bits(mode) <= 32);
+ new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
+ new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
+ noreg = ia32_new_NoReg_gp(env_cg);
+ nomem = new_NoMem();
res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
new_cmp_left, new_cmp_right, nomem, pnc);
int switch_min = INT_MAX;
const ir_edge_t *edge;
+ assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
+
/* determine the smallest switch case value */
foreach_out_edge(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
}
if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
- /* it's some mode_b value not a direct comparison -> create a testjmp */
+ /* it's some mode_b value but not a direct comparison -> create a
+ * testjmp */
res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
return res;
cmp_a = get_Cmp_left(cmp);
cmp_b = get_Cmp_right(cmp);
cmp_mode = get_irn_mode(cmp_a);
- pnc = get_Proj_proj(sel);
+ pnc = get_Proj_proj(sel);
if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
pnc |= ia32_pn_Cmp_Unsigned;
}
set_ia32_commutative(res);
}
} else {
- assert(get_mode_size_bits(cmp_mode) == 32);
+ /** workaround smaller compare modes with converts...
+ * We could easily support 16bit compares, for 8 bit we have to set
+ * additional register constraints, which we don't do yet
+ */
+ new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
+ new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
+
res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
new_cmp_a, new_cmp_b, nomem, pnc);
set_ia32_commutative(res);
ir_graph *irg = current_ir_graph;
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_rd_NoMem(irg);
+ ir_mode *mode;
ir_node *new_cmp_left;
ir_node *new_cmp_right;
ir_node *res;
ir_node *and_left = get_And_left(cmp_left);
ir_node *and_right = get_And_right(cmp_left);
+ mode = get_irn_mode(and_left);
new_cmp_left = be_transform_node(and_left);
new_cmp_right = create_immediate_or_transform(and_right, 0);
} else {
+ mode = get_irn_mode(cmp_left);
new_cmp_left = be_transform_node(cmp_left);
new_cmp_right = be_transform_node(cmp_left);
}
+ assert(get_mode_size_bits(mode) <= 32);
+ new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
+ new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
+
res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
new_cmp_left, new_cmp_right, nomem, pnc);
set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
+ res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, res,
+ nomem, mode_Bu);
+
return res;
}
+ mode = get_irn_mode(cmp_left);
+
new_cmp_left = be_transform_node(cmp_left);
new_cmp_right = create_immediate_or_transform(cmp_right, 0);
- res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem, pnc);
+
+ assert(get_mode_size_bits(mode) <= 32);
+ new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
+ new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
+
+ res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg, new_cmp_left,
+ new_cmp_right, nomem, pnc);
+ res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, res, nomem,
+ mode_Bu);
return res;
}
assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
+ assert(mode_needs_gp_reg(get_irn_mode(node)));
if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
/* a mode_b value, we have to compare it against 0 */
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
+ ir_mode *mode = get_irn_mode(node);
ir_node *fist, *load;
/* do a fist */
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_am_flavour(fist, ia32_am_B);
- set_ia32_ls_mode(fist, mode_Iu);
+
+ assert(get_mode_size_bits(mode) <= 32);
+ /* exception we can only store signed 32 bit integers, so for unsigned
+ we store a 64bit (signed) integer and load the lower bits */
+ if(get_mode_size_bits(mode) == 32 && !mode_is_signed(mode)) {
+ set_ia32_ls_mode(fist, mode_Ls);
+ } else {
+ set_ia32_ls_mode(fist, mode_Is);
+ }
SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
/* do a Load */
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_flavour(load, ia32_am_B);
- set_ia32_ls_mode(load, mode_Iu);
+ set_ia32_ls_mode(load, mode_Is);
+ if(get_ia32_ls_mode(fist) == mode_Ls) {
+ ia32_attr_t *attr = get_ia32_attr(load);
+ attr->data.need_64bit_stackent = 1;
+ } else {
+ ia32_attr_t *attr = get_ia32_attr(load);
+ attr->data.need_32bit_stackent = 1;
+ }
SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
}
-static ir_node *create_strict_conv(ir_mode *src_mode, ir_mode *tgt_mode,
- ir_node *node)
+static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
{
ir_node *block = get_nodes_block(node);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
ir_node *frame = get_irg_frame(irg);
- ir_mode *smaller_mode;
ir_node *store, *load;
ir_node *res;
- if(src_bits <= tgt_bits)
- smaller_mode = src_mode;
- else
- smaller_mode = tgt_mode;
-
store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
- smaller_mode);
+ tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_am_flavour(store, ia32_am_OB);
SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
- smaller_mode);
+ tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_flavour(load, ia32_am_OB);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
+ ir_mode *mode = get_irn_mode(op);
+ ir_mode *store_mode;
ir_node *fild, *store;
ir_node *res;
int src_bits;
- /* first convert to 32 bit if necessary */
+ /* first convert to 32 bit signed if necessary */
src_bits = get_mode_size_bits(src_mode);
if (src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
+ src_mode);
set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
- set_ia32_ls_mode(new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ mode = mode_Is;
} else if (src_bits < 32) {
- new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
- set_ia32_ls_mode(new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ mode = mode_Is;
}
+ assert(get_mode_size_bits(mode) == 32);
+
/* do a store */
store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
set_ia32_am_flavour(store, ia32_am_OB);
set_ia32_ls_mode(store, mode_Iu);
+ /* exception for 32bit unsigned, do a 64bit spill+load */
+ if(!mode_is_signed(mode)) {
+ ir_node *in[2];
+ /* store a zero */
+ ir_node *zero_const = create_Immediate_from_int(0);
+
+ ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
+ zero_const, nomem);
+
+ set_ia32_use_frame(zero_store);
+ set_ia32_op_type(zero_store, ia32_AddrModeD);
+ add_ia32_am_offs_int(zero_store, 4);
+ set_ia32_ls_mode(zero_store, mode_Iu);
+
+ in[0] = zero_store;
+ in[1] = store;
+
+ store = new_rd_Sync(dbgi, irg, block, 2, in);
+ store_mode = mode_Ls;
+ } else {
+ store_mode = mode_Is;
+ }
+
/* do a fild */
fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_am_flavour(fild, ia32_am_OB);
- set_ia32_ls_mode(fild, mode_Iu);
+ set_ia32_ls_mode(fild, store_mode);
res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
- if(get_irg_fp_model(irg) & fp_explicit_rounding) {
- res = create_strict_conv(mode_E, get_irn_mode(node), res);
+ return res;
+}
+
+/**
+ * Crete a conversion from one integer mode into another one
+ */
+static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
+ dbg_info *dbgi, ir_node *new_block,
+ ir_node *new_op)
+{
+ ir_graph *irg = current_ir_graph;
+ int src_bits = get_mode_size_bits(src_mode);
+ int tgt_bits = get_mode_size_bits(tgt_mode);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *res;
+ ir_mode *smaller_mode;
+ int smaller_bits;
+
+ if (src_bits < tgt_bits) {
+ smaller_mode = src_mode;
+ smaller_bits = src_bits;
+ } else {
+ smaller_mode = tgt_mode;
+ smaller_bits = tgt_bits;
}
+ DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
+ if (smaller_bits == 8) {
+ res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
+ new_op, nomem, smaller_mode);
+ } else {
+ res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
+ nomem, smaller_mode);
+ }
+ set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
+
return res;
}
res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
set_ia32_ls_mode(res, tgt_mode);
} else {
- // Matze: TODO what about strict convs?
if(get_Conv_strict(node)) {
- res = create_strict_conv(src_mode, tgt_mode, new_op);
+ res = create_strict_conv(tgt_mode, new_op);
SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
return res;
}
set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
}
} else {
- return gen_x87_gp_to_fp(node, src_mode);
+ res = gen_x87_gp_to_fp(node, src_mode);
+ if(get_Conv_strict(node)) {
+ res = create_strict_conv(tgt_mode, res);
+ SET_IA32_ORIG_NODE(get_Proj_pred(res),
+ ia32_get_old_node_name(env_cg, node));
+ }
+ return res;
}
} else if(tgt_mode == mode_b) {
- /* to bool */
-#if 0
- res = create_set(pn_Cmp_Lg, op, NULL, dbgi, block);
-#else
- DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...", src_mode, tgt_mode));
+ /* mode_b lowering already took care that we only have 0/1 values */
+ DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
+ src_mode, tgt_mode));
return new_op;
-#endif
} else {
/* to int */
- ir_mode *smaller_mode;
- int smaller_bits;
-
if (src_bits == tgt_bits) {
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
return new_op;
}
- if (src_bits < tgt_bits) {
- smaller_mode = src_mode;
- smaller_bits = src_bits;
- } else {
- smaller_mode = tgt_mode;
- smaller_bits = tgt_bits;
- }
-
- DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
- if (smaller_bits == 8) {
- res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem);
- set_ia32_ls_mode(res, smaller_mode);
- } else {
- res = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
- set_ia32_ls_mode(res, smaller_mode);
- }
- set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
+ res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
}
}
*
********************************************/
-static ir_node *gen_be_StackParam(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *nomem = new_rd_NoMem(current_ir_graph);
- ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
- ir_mode *load_mode = get_irn_mode(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_mode *proj_mode;
- long pn_res;
-
- if (mode_is_float(load_mode)) {
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
- pn_res = pn_ia32_xLoad_res;
- proj_mode = mode_xmm;
- } else {
- new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
- pn_res = pn_ia32_vfld_res;
- proj_mode = mode_vfp;
- }
- } else {
- new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
- proj_mode = mode_Iu;
- pn_res = pn_ia32_Load_res;
- }
-
- set_irn_pinned(new_op, op_pin_state_floats);
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
-
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_ls_mode(new_op, load_mode);
- set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
-
- return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
-}
-
/**
* Transforms a FrameAddr into an ia32 Add.
*/
return res;
}
-/**
- * Transforms a FrameLoad into an ia32 Load.
- */
-static ir_node *gen_be_FrameLoad(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
- ir_node *new_mem = be_transform_node(mem);
- ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
- ir_mode *mode = get_type_mode(get_entity_type(ent));
- ir_node *projs[pn_Load_max];
-
- ia32_collect_Projs(node, projs, pn_Load_max);
-
- if (mode_is_float(mode)) {
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
- }
- else {
- new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
- }
- }
- else {
- new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
- }
-
- set_irn_pinned(new_op, op_pin_state_floats);
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
-
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_ls_mode(new_op, mode);
- set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
-
- return new_op;
-}
-
-
-/**
- * Transforms a FrameStore into an ia32 Store.
- */
-static ir_node *gen_be_FrameStore(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
- ir_node *new_mem = be_transform_node(mem);
- ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
- ir_node *new_val = be_transform_node(val);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
- ir_mode *mode = get_irn_mode(val);
-
- if (mode_is_float(mode)) {
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- } else {
- new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
- }
- } else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- } else {
- new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- }
-
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
-
- set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_ls_mode(new_op, mode);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
-
- return new_op;
-}
-
/**
* In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
*/
#if 0
/* Unknown nodes are buggy in x87 sim, use zero for now... */
if (USE_SSE2(env_cg))
- return ia32_new_Unknown_xmm(env_cg);
else
return ia32_new_Unknown_vfp(env_cg);
#else
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_irg_start_block(irg);
- return new_rd_ia32_vfldz(dbgi, irg, block);
+ if (!USE_SSE2(env_cg)) {
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_irg_start_block(irg);
+ return new_rd_ia32_vfldz(dbgi, irg, block);
+ } else {
+ return ia32_new_Unknown_xmm(env_cg);
+ }
#endif
} else if (mode_needs_gp_reg(mode)) {
return ia32_new_Unknown_gp(env_cg);
return phi;
}
+/**
+ * Transform IJmp
+ */
+static ir_node *gen_IJmp(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_op = be_transform_node(get_IJmp_target(node));
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *new_node;
+
+ new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
+
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ return new_node;
+}
+
+
/**********************************************************************
* _ _ _
* | | | | | |
}
/**
-* Transforms a lowered Store into a "real" one.
-*/
+ * Transforms a lowered Store into a "real" one.
+ */
static ir_node *gen_lowered_Store(ir_node *node, construct_store_func func)
{
ir_node *block = be_transform_node(get_nodes_block(node));
return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
}
-#define GEN_LOWERED_SHIFT_OP(op) \
- static ir_node *gen_ia32_l_##op(ir_node *node) {\
- return gen_shift_binop(node, get_binop_left(node), \
- get_binop_right(node), new_rd_ia32_##op); \
+#define GEN_LOWERED_SHIFT_OP(l_op, op) \
+ static ir_node *gen_ia32_##l_op(ir_node *node) { \
+ return gen_shift_binop(node, get_irn_n(node, 0), \
+ get_irn_n(node, 1), new_rd_ia32_##op); \
}
#define GEN_LOWERED_LOAD(op) \
GEN_LOWERED_LOAD(vfild)
GEN_LOWERED_LOAD(Load)
-// GEN_LOWERED_STORE(vfist) TODO
GEN_LOWERED_STORE(Store)
+/**
+ * Transforms a l_vfist into a "real" vfist node.
+ *
+ * @param env The transformation environment
+ * @return the created ia32 vfist node
+ */
+static ir_node *gen_ia32_l_vfist(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *ptr = get_irn_n(node, 0);
+ ir_node *new_ptr = be_transform_node(ptr);
+ ir_node *val = get_irn_n(node, 1);
+ ir_node *new_val = be_transform_node(val);
+ ir_node *mem = get_irn_n(node, 2);
+ ir_node *new_mem = be_transform_node(mem);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
+ ir_node *new_op;
+ long am_offs;
+ ia32_am_flavour_t am_flav = ia32_B;
+
+ new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
+ trunc_mode, new_mem);
+
+ if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
+ am_flav |= ia32_O;
+ add_ia32_am_offs_int(new_op, am_offs);
+ }
+
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, am_flav);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+
+ return new_op;
+}
+
+/**
+ * Transforms a l_vfdiv into a "real" vfdiv node.
+ *
+ * @param env The transformation environment
+ * @return the created ia32 vfdiv node
+ */
static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *left = get_binop_left(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
- &ia32_fp_cw_regs[REG_FPCW]);
+ ir_node *fpcw = get_fpcw();
ir_node *vfdiv;
vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
return muls;
}
-GEN_LOWERED_SHIFT_OP(Shl)
-GEN_LOWERED_SHIFT_OP(Shr)
-GEN_LOWERED_SHIFT_OP(Sar)
+GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
+GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
+GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
+GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
/**
* Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *new_op1 = be_transform_node(op1);
ir_node *new_op2 = be_transform_node(op2);
- ir_node *new_count = be_transform_node(count);
ir_node *new_op = NULL;
+ ir_node *new_count = be_transform_node(count);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
} else if (proj == pn_Load_M) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
}
+ } else if(is_ia32_Conv_I2I(new_pred)) {
+ set_irn_mode(new_pred, mode_T);
+ if (proj == pn_Load_res) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
+ } else if (proj == pn_Load_M) {
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
+ }
} else if (is_ia32_xLoad(new_pred)) {
if (proj == pn_Load_res) {
return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
* Transform the Projs from a be_Call.
*/
static ir_node *gen_Proj_be_Call(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *call = get_Proj_pred(node);
- ir_node *new_call = be_transform_node(call);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- long proj = get_Proj_proj(node);
- ir_mode *mode = get_irn_mode(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *call = get_Proj_pred(node);
+ ir_node *new_call = be_transform_node(call);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_type *method_type = be_Call_get_type(call);
+ int n_res = get_method_n_ress(method_type);
+ long proj = get_Proj_proj(node);
+ ir_mode *mode = get_irn_mode(node);
ir_node *sse_load;
const arch_register_class_t *cls;
pn_ia32_xLoad_M);
}
}
- if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
+ if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
+ && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
+ && USE_SSE2(env_cg)) {
ir_node *fstp;
ir_node *frame = get_irg_frame(irg);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
pn_be_Call_first_res);
/* store st(0) onto stack */
- fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
- call_res, mode);
+ fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
+ call_mem, mode);
set_ia32_op_type(fstp, ia32_AddrModeD);
set_ia32_use_frame(fstp);
set_ia32_am_flavour(fstp, ia32_am_B);
/* transform call modes */
if (mode_is_data(mode)) {
- cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
+ cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
mode = cls->mode;
}
ir_node *pred = get_Proj_pred(node);
long proj = get_Proj_proj(node);
- if (is_Store(pred) || be_is_FrameStore(pred)) {
+ if (is_Store(pred)) {
if (proj == pn_Store_M) {
return be_transform_node(pred);
} else {
assert(0);
return new_r_Bad(irg);
}
- } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
+ } else if (is_Load(pred)) {
return gen_Proj_Load(node);
} else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
return gen_Proj_DivMod(node);
if (node == be_get_old_anchor(anchor_tls)) {
return gen_Proj_tls(node);
}
+#ifdef FIRM_EXT_GRS
+ } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
+#else
} else {
+#endif
ir_node *new_pred = be_transform_node(pred);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_mode *mode = get_irn_mode(node);
GEN(Psi);
GEN(Proj);
GEN(Phi);
+ GEN(IJmp);
/* transform ops from intrinsic lowering */
GEN(ia32_l_Add);
GEN(ia32_l_Mul);
GEN(ia32_l_Xor);
GEN(ia32_l_IMul);
- GEN(ia32_l_Shl);
- GEN(ia32_l_Shr);
+ GEN(ia32_l_ShlDep);
+ GEN(ia32_l_ShrDep);
GEN(ia32_l_Sar);
+ GEN(ia32_l_SarDep);
GEN(ia32_l_ShlD);
GEN(ia32_l_ShrD);
GEN(ia32_l_vfdiv);
GEN(ia32_l_vfsub);
GEN(ia32_l_vfild);
GEN(ia32_l_Load);
- /* GEN(ia32_l_vfist); TODO */
+ GEN(ia32_l_vfist);
GEN(ia32_l_Store);
GEN(ia32_l_X87toSSE);
GEN(ia32_l_SSEtoX87);
GEN(be_FrameAddr);
//GEN(be_Call);
GEN(be_Return);
- GEN(be_FrameLoad);
- GEN(be_FrameStore);
- GEN(be_StackParam);
GEN(be_AddSP);
GEN(be_SubSP);
GEN(be_Copy);
cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
+ get_fpcw();
}
+/**
+ * Walker, checks if all ia32 nodes producing more than one result have
+ * its Projs, other wise creates new projs and keep them using a be_Keep node.
+ */
static
void add_missing_keep_walker(ir_node *node, void *data)
{
}
/**
- * Adds missing keeps to nodes
+ * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
+ * and keeps them.
*/
static
void add_missing_keeps(ia32_code_gen_t *cg)
void ia32_transform_graph(ia32_code_gen_t *cg) {
register_transformers();
env_cg = cg;
+ initial_fpcw = NULL;
be_transform_graph(cg->birg, ia32_pretransform_node, cg);
edges_verify(cg->irg);
add_missing_keeps(cg);