#include "irprintf.h"
#include "debug.h"
#include "irdom.h"
+#include "type.h"
+#include "entity.h"
#include "archop.h" /* we need this for Min and Max nodes */
#include "../benode_t.h"
* Returns 1 if irn is a Const representing 0, 0 otherwise
*/
static INLINE int is_ia32_Const_0(ir_node *irn) {
- return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
+ return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
+ classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
}
/**
* Returns 1 if irn is a Const representing 1, 0 otherwise
*/
static INLINE int is_ia32_Const_1(ir_node *irn) {
- return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
+ return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
+ classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
}
/**
return NULL;
}
+/**
+ * Renumbers the Proj of node irn having pn_old to pn_new.
+ */
+static INLINE void ia32_renumber_Proj(ir_node *irn, long pn_old, long pn_new) {
+ ir_node *proj = get_proj_for_pn(irn, pn_old);
+
+ if (proj)
+ set_Proj_proj(proj, pn_new);
+}
+
/**
* SSE convert of an integer node into a floating point node.
*/
return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
}
+/**
+* SSE convert of an float node into a double node.
+*/
+static ir_node *gen_sse_conv_f2d(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
+ ir_node *in, ir_node *old_node)
+{
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+
+ ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
+ set_ia32_src_mode(conv, mode_F);
+ set_ia32_tgt_mode(conv, mode_D);
+ set_ia32_am_support(conv, ia32_am_Source);
+ SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
+
+ return new_rd_Proj(dbg, irg, block, conv, mode_D, pn_ia32_Conv_FP2FP_res);
+}
+
/* Generates an entity for a known FP const (used for FP Neg + Abs) */
-static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
+static ident *gen_fp_known_const(ia32_known_const_t kct) {
static const struct {
const char *tp_name;
const char *ent_name;
{ TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
{ TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
};
- static struct entity *ent_cache[ia32_known_const_max];
+ static entity *ent_cache[ia32_known_const_max];
const char *tp_name, *ent_name, *cnst_str;
ir_type *tp;
ir_graph *rem;
entity *ent;
tarval *tv;
+ ir_mode *mode;
ent_name = names[kct].ent_name;
if (! ent_cache[kct]) {
tp_name = names[kct].tp_name;
cnst_str = names[kct].cnst_str;
+ mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
tp = new_type_primitive(new_id_from_str(tp_name), mode);
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
* @return The constructed ia32 node.
*/
static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
- ir_node *new_op = NULL;
- ir_mode *mode = env->mode;
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
- ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
- ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
- ir_node *nomem = new_NoMem();
- ir_node *expr_op, *imm_op;
+ ir_node *new_op = NULL;
+ ir_mode *mode = env->mode;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
+ ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
+ ir_node *nomem = new_NoMem();
+ int is_mul = 0;
+ ir_node *expr_op, *imm_op;
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- /* MulS and Mulh don't support immediates */
+ /* Mul/MulS/Mulh don't support immediates */
if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
+ func == new_rd_ia32_Mul ||
func == new_rd_ia32_Mulh ||
func == new_rd_ia32_MulS)
{
expr_op = op1;
imm_op = NULL;
+ /* immediate operations are requested, but we are here: it a mul */
+ if (env->cg->opt & IA32_OPT_IMMOPS)
+ is_mul = 1;
}
else if (is_op_commutative(get_irn_op(env->irn))) {
imm_op = get_immediate_op(op1, op2);
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
}
+
+ /* Muls can only have AM source */
+ if (is_mul)
+ set_ia32_am_support(new_op, ia32_am_Source);
}
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
set_ia32_am_flavour(new_op, ia32_am_OB);
- DBG_OPT_LEA1(op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- DBG_OPT_LEA2(op1, op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
}
else {
/* integer SUB */
- if (!expr_op) {
+ if (! expr_op) {
/* No expr_op means, that we have two const - one symconst and */
/* one tarval or another symconst - because this case is not */
/* covered by constant folding */
/* We need to check for: */
- /* 1) symconst + const -> becomes a LEA */
- /* 2) symconst + symconst -> becomes a const + LEA as the elf */
+ /* 1) symconst - const -> becomes a LEA */
+ /* 2) symconst - symconst -> becomes a const - LEA as the elf */
/* linker doesn't support two symconsts */
if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
set_ia32_am_sc_sign(new_op);
set_ia32_am_flavour(new_op, ia32_am_OB);
- DBG_OPT_LEA1(op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- DBG_OPT_LEA2(op1, op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
+ ia32_renumber_Proj(env->irn, pn_DivMod_M, pn_ia32_DivMod_M);
+ ia32_renumber_Proj(env->irn, pn_DivMod_res_mod, pn_ia32_DivMod_mod_res);
+ ia32_renumber_Proj(env->irn, pn_DivMod_res_div, pn_ia32_DivMod_div_res);
+
set_ia32_res_mode(res, mode);
return res;
new_op = new_rd_ia32_xDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
set_ia32_am_support(new_op, ia32_am_Source);
}
+ ia32_renumber_Proj(env->irn, pn_Quot_M, pn_ia32_xDiv_M);
+ ia32_renumber_Proj(env->irn, pn_Quot_res, pn_ia32_xDiv_res);
}
else {
new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem);
set_ia32_am_support(new_op, ia32_am_Source);
+ ia32_renumber_Proj(env->irn, pn_Quot_M, pn_ia32_vfdiv_M);
+ ia32_renumber_Proj(env->irn, pn_Quot_res, pn_ia32_vfdiv_res);
}
set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
-
return new_op;
}
new_op = new_rd_ia32_xEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
size = get_mode_size_bits(env->mode);
- name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
+ name = gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
- set_ia32_sc(new_op, name);
+ set_ia32_am_sc(new_op, name);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, env->mode);
- set_ia32_immop_type(new_op, ia32_ImmSymConst);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_ls_mode(new_op, env->mode);
new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
}
res = new_rd_ia32_xAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem);
size = get_mode_size_bits(mode);
- name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
+ name = gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_sc(res, name);
+ set_ia32_am_sc(res, name);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
- set_ia32_immop_type(res, ia32_ImmSymConst);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ set_ia32_ls_mode(res, env->mode);
res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
}
if (mode_is_float(mode)) {
FP_USED(env->cg);
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
- else
+ ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_xLoad_M);
+ ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_xLoad_res);
+ }
+ else {
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
+ ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_vfld_M);
+ ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_vfld_res);
+ }
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node));
+ ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_Load_M);
+ ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_Load_res);
}
/* base is an constant address */
ir_node *ptr = get_Store_ptr(node);
ir_node *sptr = ptr;
ir_node *mem = get_Store_mem(node);
- ir_mode *mode = get_irn_link(node);
+ ir_mode *mode = get_irn_mode(val);
ir_node *sval = val;
int is_imm = 0;
ir_node *new_op;
if (mode_is_float(mode)) {
FP_USED(env->cg);
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
- else
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_xStore_M);
+ }
+ else {
new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_vfst_M);
+ }
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store8Bit_M);
}
else {
new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store_M);
}
/* stored const is an attribute (saves a register) */
/* base is an constant address */
if (is_imm) {
- if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
+ if (get_ia32_op_type(ptr) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
am_flav = ia32_am_N;
}
if (is_Proj(sel) && sel_mode == mode_b) {
ir_node *nomem = new_NoMem();
+ pn_Cmp pnc = get_Proj_proj(sel);
pred = get_Proj_pred(sel);
expr = get_expr_op(cmp_a, cmp_b);
if (cnst && expr) {
- pn_Cmp pnc = get_Proj_proj(sel);
+ /* immop has to be the right operand, we might need to flip pnc */
+ if(cnst != cmp_b) {
+ pnc = get_inversed_pnc(pnc);
+ }
if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
if (get_ia32_op_type(cnst) == ia32_Const &&
cnst = (is_ia32_ImmConst(and) || is_ia32_ImmSymConst(and)) ? get_ia32_cnst(and) : NULL;
}
res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
- set_ia32_pncode(res, get_Proj_proj(sel));
+ set_ia32_pncode(res, pnc);
set_ia32_res_mode(res, get_irn_mode(op1));
if (cnst) {
set_ia32_res_mode(res, get_irn_mode(cmp_a));
}
- set_ia32_pncode(res, get_Proj_proj(sel));
+ set_ia32_pncode(res, pnc);
//set_ia32_am_support(res, ia32_am_Source);
}
else {
* @return The transformed node.
*/
static ir_node *gen_CopyB(ia32_transform_env_t *env) {
- ir_node *res = NULL;
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_mode *mode = env->mode;
- ir_node *block = env->block;
- ir_node *node = env->irn;
- ir_node *src = get_CopyB_src(node);
- ir_node *dst = get_CopyB_dst(node);
- ir_node *mem = get_CopyB_mem(node);
- int size = get_type_size_bytes(get_CopyB_type(node));
- int rem;
-
- /* If we have to copy more than 16 bytes, we use REP MOVSx and */
+ ir_node *res = NULL;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *node = env->irn;
+ ir_node *src = get_CopyB_src(node);
+ ir_node *dst = get_CopyB_dst(node);
+ ir_node *mem = get_CopyB_mem(node);
+ int size = get_type_size_bytes(get_CopyB_type(node));
+ ir_mode *dst_mode = get_irn_mode(dst);
+ ir_mode *src_mode = get_irn_mode(src);
+ int rem;
+ ir_node *in[3];
+
+ /* If we have to copy more than 32 bytes, we use REP MOVSx and */
/* then we need the size explicitly in ECX. */
- if (size >= 16 * 4) {
+ if (size >= 32 * 4) {
rem = size & 0x3; /* size % 4 */
size >>= 2;
set_ia32_op_type(res, ia32_Const);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
- res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
+ res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
+
+ /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
+ in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
+ in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
+ in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
+
+ ia32_renumber_Proj(env->irn, pn_CopyB_M_regular, pn_ia32_CopyB_M);
}
else {
- res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
+ res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
set_ia32_immop_type(res, ia32_ImmConst);
+
+ /* ok: now attach Proj's because movsd will destroy esi and edi */
+ in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
+ in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
+
+ ia32_renumber_Proj(env->irn, pn_CopyB_M_regular, pn_ia32_CopyB_i_M);
}
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
set_ia32_am_support(and1, ia32_am_None);
set_ia32_res_mode(and1, mode);
+ set_ia32_commutative(and1);
SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
set_ia32_am_support(and2, ia32_am_None);
set_ia32_res_mode(and2, mode);
+ set_ia32_commutative(and2);
SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
set_ia32_am_support(new_op, ia32_am_None);
set_ia32_res_mode(new_op, mode);
+ set_ia32_commutative(new_op);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
}
* Create a conversion from x87 state register to general purpose.
*/
static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
- ia32_code_gen_t *cg = env->cg;
- entity *ent = cg->fp_to_gp;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *op = get_Conv_op(env->irn);
- ir_node *fist, *mem, *load;
+ ia32_code_gen_t *cg = env->cg;
+ entity *ent = cg->fp_to_gp;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *op = get_Conv_op(env->irn);
+ ir_node *fist, *mem, *load;
if (! ent) {
int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
set_ia32_am_flavour(store, ia32_B);
set_ia32_ls_mode(store, mode_Is);
- mem = new_r_Proj(irg, block, store, mode_M, 0);
+ mem = new_r_Proj(irg, block, store, mode_M, pn_ia32_Store_M);
/* do a fild */
fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem);
set_ia32_am_flavour(fild, ia32_B);
set_ia32_ls_mode(fild, mode_F);
- return new_r_Proj(irg, block, fild, mode_F, 0);
+ return new_r_Proj(irg, block, fild, mode_F, pn_ia32_vfild_res);
}
/**
int src_bits = get_mode_size_bits(src_mode);
int tgt_bits = get_mode_size_bits(tgt_mode);
int pn = -1;
+ int kill = 0;
ir_node *block = env->block;
ir_node *new_op = NULL;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
}
else {
DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
- edges_reroute(env->irn, op, irg);
+ /*
+ remark: we create a intermediate conv here, so modes will be spread correctly
+ these convs will be killed later
+ */
+ new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_FP2FP_res;
+ kill = 1;
}
}
else {
if (tgt_bits < 32) {
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_tgt_mode(new_op, tgt_mode);
+ set_ia32_tgt_mode(new_op, mode_Is);
set_ia32_src_mode(new_op, src_mode);
proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
pn = pn_ia32_Conv_I2I_res;
}
+ src_mode = mode_Is;
}
}
}
/* ... to int */
if (get_mode_size_bits(src_mode) == tgt_bits) {
DB((mod, LEVEL_1, "omitting equal size Conv(%+F, %+F) ...", src_mode, tgt_mode));
- edges_reroute(env->irn, op, irg);
+ /*
+ remark: we create a intermediate conv here, so modes will be spread correctly
+ these convs will be killed later
+ */
+ new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_I2I_res;
+ kill = 1;
}
else {
DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
set_ia32_am_support(new_op, ia32_am_Source);
new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
+
+ if (kill)
+ nodeset_insert(env->cg->kill_conv, new_op);
}
return new_op;
*
********************************************/
- /**
- * Decides in which block the transformed StackParam should be placed.
- * If the StackParam has more than one user, the dominator block of
- * the users will be returned. In case of only one user, this is either
- * the user block or, in case of a Phi, the predecessor block of the Phi.
- */
- static ir_node *get_block_transformed_stack_param(ir_node *irn) {
- ir_node *dom_bl = NULL;
-
- if (get_irn_n_edges(irn) == 1) {
- ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
-
- if (! is_Phi(src)) {
- dom_bl = get_nodes_block(src);
- }
- else {
- /* Determine on which in position of the Phi the irn is */
- /* and get the corresponding cfg predecessor block. */
-
- int i = get_irn_pred_pos(src, irn);
- assert(i >= 0 && "kaputt");
- dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
- }
- }
- else {
- dom_bl = node_users_smallest_common_dominator(irn, 1);
- }
-
- assert(dom_bl && "dominator block not found");
-
- return dom_bl;
- }
-
static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
ir_node *node = env->irn;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *mem = new_rd_NoMem(env->irg);
ir_node *ptr = get_irn_n(node, 0);
- entity *ent = be_get_frame_entity(node);
+ entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
ir_mode *mode = env->mode;
-
- /* choose the block where to place the load */
- env->block = get_block_transformed_stack_param(node);
+ long pn_res;
if (mode_is_float(mode)) {
FP_USED(env->cg);
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
- else
+ pn_res = pn_ia32_xLoad_res;
+ }
+ else {
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
+ pn_res = pn_ia32_vfld_res;
+ }
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
+ pn_res = pn_ia32_Load_res;
}
set_ia32_frame_ent(new_op, ent);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, mode);
+ set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
- return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_ia32_Load_res);
+ return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, pn_res);
}
/**
ir_node *nomem = new_rd_NoMem(env->irg);
new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem);
- set_ia32_frame_ent(new_op, be_get_frame_entity(node));
+ set_ia32_frame_ent(new_op, arch_get_frame_entity(env->cg->arch_env, node));
set_ia32_am_support(new_op, ia32_am_Full);
set_ia32_use_frame(new_op);
set_ia32_immop_type(new_op, ia32_ImmConst);
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *mem = get_irn_n(node, 0);
ir_node *ptr = get_irn_n(node, 1);
- entity *ent = be_get_frame_entity(node);
+ entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
ir_mode *mode = get_type_mode(get_entity_type(ent));
if (mode_is_float(mode)) {
FP_USED(env->cg);
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, mem);
- else
+ ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_xLoad_M);
+ ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_xLoad_res);
+ }
+ else {
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
+ ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_vfld_M);
+ ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_vfld_res);
+ }
}
- else
+ else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem);
+ ia32_renumber_Proj(env->irn, pn_Load_M, pn_ia32_Load_M);
+ ia32_renumber_Proj(env->irn, pn_Load_res, pn_ia32_Load_res);
+ }
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
ir_node *mem = get_irn_n(node, 0);
ir_node *ptr = get_irn_n(node, 1);
ir_node *val = get_irn_n(node, 2);
- entity *ent = be_get_frame_entity(node);
+ entity *ent = arch_get_frame_entity(env->cg->arch_env, node);
ir_mode *mode = get_irn_mode(val);
if (mode_is_float(mode)) {
FP_USED(env->cg);
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
- else
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_xStore_M);
+ }
+ else {
new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_vfst_M);
+ }
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store8Bit_M);
}
else {
new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
+ ia32_renumber_Proj(env->irn, pn_Store_M, pn_ia32_Store_M);
}
set_ia32_frame_ent(new_op, ent);
return new_op;
}
+/**
+ * In case SSE is used we need to copy the result from FPU TOS.
+ */
+static ir_node *gen_be_Call(ia32_transform_env_t *env) {
+ ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
+ ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
+ ir_mode *mode;
+
+ if (! call_res || ! USE_SSE2(env->cg))
+ return NULL;
+
+ mode = get_irn_mode(call_res);
+
+ /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
+ if (! call_mem)
+ call_mem = new_r_Proj(env->irg, env->block, env->irn, mode_M, pn_be_Call_M_regular);
+
+ if (mode_is_float(mode)) {
+ /* store st(0) onto stack */
+ ir_node *frame = get_irg_frame(env->irg);
+ ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
+ ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
+ entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
+ ir_node *sse_load, *p, *bad, *keep;
+ ir_node **in_keep;
+ int keep_arity, i;
+
+ set_ia32_ls_mode(fstp, mode);
+ set_ia32_op_type(fstp, ia32_AddrModeD);
+ set_ia32_use_frame(fstp);
+ set_ia32_frame_ent(fstp, ent);
+ set_ia32_am_flavour(fstp, ia32_B);
+ set_ia32_am_support(fstp, ia32_am_Dest);
+
+ /* load into SSE register */
+ sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
+ set_ia32_ls_mode(sse_load, mode);
+ set_ia32_op_type(sse_load, ia32_AddrModeS);
+ set_ia32_use_frame(sse_load);
+ set_ia32_frame_ent(sse_load, ent);
+ set_ia32_am_flavour(sse_load, ia32_B);
+ set_ia32_am_support(sse_load, ia32_am_Source);
+ sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
+
+ /* reroute all users of the result proj to the sse load */
+ edges_reroute(call_res, sse_load, env->irg);
+
+ /* now: create new Keep whith all former ins and one additional in - the result Proj */
+
+ /* get a Proj representing a caller save register */
+ p = get_proj_for_pn(env->irn, pn_be_Call_first_res + 1);
+ assert(is_Proj(p) && "Proj expected.");
+
+ /* user of the the proj is the Keep */
+ p = get_edge_src_irn(get_irn_out_edge_first(p));
+ assert(be_is_Keep(p) && "Keep expected.");
+
+ /* copy in array of the old keep and set the result proj as additional in */
+ keep_arity = get_irn_arity(p) + 1;
+ NEW_ARR_A(ir_node *, in_keep, keep_arity);
+ in_keep[keep_arity - 1] = call_res;
+ for (i = 0; i < keep_arity - 1; ++i)
+ in_keep[i] = get_irn_n(p, i);
+
+ /* create new keep and set the in class requirements properly */
+ keep = be_new_Keep(NULL, env->irg, env->block, keep_arity, in_keep);
+ for(i = 0; i < keep_arity; ++i) {
+ const arch_register_class_t *cls = arch_get_irn_reg_class(env->cg->arch_env, in_keep[i], -1);
+ be_node_set_reg_class(keep, i, cls);
+ }
+
+ /* kill the old keep */
+ bad = get_irg_bad(env->irg);
+ for (i = 0; i < keep_arity - 1; i++)
+ set_irn_n(p, i, bad);
+ remove_End_keepalive(get_irg_end(env->irg), p);
+ }
+
+ return NULL;
+}
+
+/**
+ * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
+ */
+static ir_node *gen_be_Return(ia32_transform_env_t *env) {
+ ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val);
+ ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem);
+ entity *ent = get_irg_entity(get_irn_irg(ret_val));
+ ir_type *tp = get_entity_type(ent);
+
+ if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg))
+ return NULL;
+
+ if (get_method_n_ress(tp) == 1) {
+ ir_type *res_type = get_method_res_type(tp, 0);
+ ir_mode *mode;
+
+ if (is_Primitive_type(res_type)) {
+ mode = get_type_mode(res_type);
+ if (mode_is_float(mode)) {
+ ir_node *frame;
+ entity *ent;
+ ir_node *sse_store, *fld, *mproj, *barrier;
+ int pn_ret_val = get_Proj_proj(ret_val);
+ int pn_ret_mem = get_Proj_proj(ret_mem);
+
+ /* get the Barrier */
+ barrier = get_Proj_pred(ret_val);
+
+ /* get result input of the Barrier */
+ ret_val = get_irn_n(barrier, pn_ret_val);
+
+ /* get memory input of the Barrier */
+ ret_mem = get_irn_n(barrier, pn_ret_mem);
+
+ frame = get_irg_frame(env->irg);
+ ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
+
+ /* store xmm0 onto stack */
+ sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem);
+ set_ia32_ls_mode(sse_store, mode);
+ set_ia32_op_type(sse_store, ia32_AddrModeD);
+ set_ia32_use_frame(sse_store);
+ set_ia32_frame_ent(sse_store, ent);
+ set_ia32_am_flavour(sse_store, ia32_B);
+ set_ia32_am_support(sse_store, ia32_am_Dest);
+ sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M);
+
+ /* load into st0 */
+ fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store);
+ set_ia32_ls_mode(fld, mode);
+ set_ia32_op_type(fld, ia32_AddrModeS);
+ set_ia32_use_frame(fld);
+ set_ia32_frame_ent(fld, ent);
+ set_ia32_am_flavour(fld, ia32_B);
+ set_ia32_am_support(fld, ia32_am_Source);
+ mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M);
+ fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res);
+ arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
+
+ /* set new return value */
+ set_irn_n(barrier, pn_ret_val, fld);
+ set_irn_n(barrier, pn_ret_mem, mproj);
+ }
+ }
+ }
+
+ return NULL;
+}
+
+/**
+ * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
+ */
+static ir_node *gen_be_AddSP(ia32_transform_env_t *env) {
+ ir_node *new_op;
+ const ir_edge_t *edge;
+ ir_node *sz = get_irn_n(env->irn, be_pos_AddSP_size);
+ ir_node *sp = get_irn_n(env->irn, be_pos_AddSP_old_sp);
+
+ new_op = new_rd_ia32_AddSP(env->dbg, env->irg, env->block, sp, sz);
+
+ if (is_ia32_Const(sz)) {
+ set_ia32_Immop_attr(new_op, sz);
+ set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
+ }
+ else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
+ set_ia32_immop_type(new_op, ia32_ImmSymConst);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
+ add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
+ set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
+ }
+
+ /* fix proj nums */
+ foreach_out_edge(env->irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+
+ assert(is_Proj(proj));
+
+ if (get_Proj_proj(proj) == pn_be_AddSP_res) {
+ /* the node is not yet exchanged: we need to set the register manually */
+ ia32_attr_t *attr = get_ia32_attr(new_op);
+ attr->slots[pn_ia32_AddSP_stack] = &ia32_gp_regs[REG_ESP];
+ set_Proj_proj(proj, pn_ia32_AddSP_stack);
+ }
+ else if (get_Proj_proj(proj) == pn_be_AddSP_M) {
+ set_Proj_proj(proj, pn_ia32_AddSP_M);
+ }
+ else {
+ assert(0);
+ }
+ }
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+
+ return new_op;
+}
+
+/**
+ * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
+ */
+static ir_node *gen_be_SubSP(ia32_transform_env_t *env) {
+ ir_node *new_op;
+ const ir_edge_t *edge;
+ ir_node *sz = get_irn_n(env->irn, be_pos_SubSP_size);
+ ir_node *sp = get_irn_n(env->irn, be_pos_SubSP_old_sp);
+
+ new_op = new_rd_ia32_SubSP(env->dbg, env->irg, env->block, sp, sz);
+
+ if (is_ia32_Const(sz)) {
+ set_ia32_Immop_attr(new_op, sz);
+ set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
+ }
+ else if (is_ia32_Load(sz) && get_ia32_am_flavour(sz) == ia32_O) {
+ set_ia32_immop_type(new_op, ia32_ImmSymConst);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_sc(new_op, get_ia32_am_sc(sz));
+ add_ia32_am_offs(new_op, get_ia32_am_offs(sz));
+ set_irn_n(new_op, 1, ia32_new_NoReg_gp(env->cg));
+ }
+
+ /* fix proj nums */
+ foreach_out_edge(env->irn, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+
+ assert(is_Proj(proj));
+
+ if (get_Proj_proj(proj) == pn_be_SubSP_res) {
+ /* the node is not yet exchanged: we need to set the register manually */
+ ia32_attr_t *attr = get_ia32_attr(new_op);
+ attr->slots[pn_ia32_SubSP_stack] = &ia32_gp_regs[REG_ESP];
+ set_Proj_proj(proj, pn_ia32_SubSP_stack);
+ }
+ else if (get_Proj_proj(proj) == pn_be_SubSP_M) {
+ set_Proj_proj(proj, pn_ia32_SubSP_M);
+ }
+ else {
+ assert(0);
+ }
+ }
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+
+ return new_op;
+}
+
/**
* This function just sets the register for the Unknown node
* as this is not done during register allocation because Unknown
else
arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
}
- else if (mode_is_int(mode) || mode_is_reference(mode)) {
+ else if (mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode)) {
arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
}
else {
IGN(SymConst);
IGN(Sync);
+ /* we should never see these nodes */
BAD(Raise);
BAD(Sel);
BAD(InstOf);
BAD(EndReg);
BAD(EndExcept);
+ /* handle generic backend nodes */
GEN(be_FrameAddr);
+ GEN(be_Call);
+ GEN(be_Return);
GEN(be_FrameLoad);
GEN(be_FrameStore);
GEN(be_StackParam);
+ GEN(be_AddSP);
+ GEN(be_SubSP);
/* set the register for all Unknown nodes */
GEN(Unknown);
ia32_transform_env_t tenv;
transform_func *transform = (transform_func *)op->ops.generic;
- tenv.block = get_nodes_block(node);
- tenv.dbg = get_irn_dbg_info(node);
- tenv.irg = current_ir_graph;
- tenv.irn = node;
- tenv.mode = get_irn_mode(node);
- tenv.cg = cg;
+ tenv.block = get_nodes_block(node);
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irg = current_ir_graph;
+ tenv.irn = node;
+ tenv.mode = get_irn_mode(node);
+ tenv.cg = cg;
DEBUG_ONLY(tenv.mod = cg->mod;)
asm_node = (*transform)(&tenv);
/* Psi is float, we need a floating point compare */
if (USE_SSE2(cg)) {
+ ir_mode *m = get_irn_mode(cmp_a);
/* SSE FPU */
- if (! mode_is_float(get_irn_mode(cmp_a))) {
+ if (! mode_is_float(m)) {
cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
- pnc |= 8;
+ }
+ else if (m == mode_F) {
+ /* we convert cmp values always to double, to get correct bitmask with cmpsd */
+ cmp_a = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_a, cmp_a);
+ cmp_b = gen_sse_conv_f2d(cg, dbg, irg, block, cmp_b, cmp_b);
}
new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
if (is_Proj(psi_sel))
return;
- mode = get_irn_mode(node);
+ //mode = get_irn_mode(node);
+ mode = mode_Iu;
transform_psi_cond(psi_sel, mode, cg);
block = get_nodes_block(node);
/* we need to compare the evaluated condition tree with 0 */
-
- /* BEWARE: new_r_Const_long works for floating point as well */
- new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
- new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
+ mode = get_irn_mode(node);
+ if (mode_is_float(mode)) {
+ psi_sel = gen_sse_conv_int2float(cg, NULL, irg, block, psi_sel, NULL, mode);
+ /* BEWARE: new_r_Const_long works for floating point as well */
+ new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
+ new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne);
+ }
+ else {
+ new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode_Iu, 0));
+ new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Gt | pn_Cmp_Lt);
+ }
set_Psi_cond(node, 0, new_cmp);
}
projects / libfirm / blobdiff