#include "irprintf.h"
#include "debug.h"
#include "irdom.h"
+#include "iropt.h"
#include "error.h"
#include "array_t.h"
#include "heights.h"
#include "ia32_new_nodes.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
-#include "ia32_util.h"
#include "ia32_address_mode.h"
#include "ia32_architecture.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
+static ir_node *old_initial_fpcw = NULL;
static ir_node *initial_fpcw = NULL;
int ia32_no_pic_adjust;
if (mode_is_float(mode)) {
ir_node *res = NULL;
ir_node *load;
- ir_node *base;
ir_entity *floatent;
if (ia32_cg_config.use_sse2) {
set_ia32_ls_mode(load, mode);
res = load;
} else {
+ ir_node *base;
#ifdef CONSTRUCT_SSE_CONST
if (mode == mode_D) {
unsigned val = get_tarval_sub_bits(tv, 0) |
panic("backend only support symconst_addr_ent (at %+F)", node);
}
entity = get_SymConst_entity(node);
- cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
+ if (get_entity_owner(entity) == get_tls_type()) {
+ ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
+ ir_node *lea = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP);
+ set_ia32_am_sc(lea, entity);
+ cnst = lea;
+ } else {
+ cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
+ }
}
SET_IA32_ORIG_NODE(cnst, node);
addr->index = noreg_GP;
addr->mem = nomem;
addr->symconst_ent = entity;
+ addr->tls_segment = false;
addr->use_frame = 1;
am->ls_mode = get_type_mode(get_entity_type(entity));
am->pinned = op_pin_state_floats;
set_ia32_am_scale(node, addr->scale);
set_ia32_am_sc(node, addr->symconst_ent);
set_ia32_am_offs_int(node, addr->offset);
+ set_ia32_am_tls_segment(node, addr->tls_segment);
if (addr->symconst_sign)
set_ia32_am_sc_sign(node);
if (addr->use_frame)
}
am->op_type = ia32_AddrModeS;
} else {
- ir_mode *mode;
am->op_type = ia32_Normal;
if (flags & match_try_am) {
static ir_node *get_fpcw(void)
{
- ir_node *fpcw;
if (initial_fpcw != NULL)
return initial_fpcw;
- fpcw = be_abi_get_ignore_irn(be_get_irg_abi(current_ir_graph),
- &ia32_registers[REG_FPCW]);
- initial_fpcw = be_transform_node(fpcw);
-
+ initial_fpcw = be_transform_node(old_initial_fpcw);
return initial_fpcw;
}
static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
ia32_address_t *addr)
{
- ir_node *base, *index, *res;
+ ir_node *base;
+ ir_node *idx;
+ ir_node *res;
base = addr->base;
if (base == NULL) {
base = be_transform_node(base);
}
- index = addr->index;
- if (index == NULL) {
- index = noreg_GP;
+ idx = addr->index;
+ if (idx == NULL) {
+ idx = noreg_GP;
} else {
- index = be_transform_node(index);
+ idx = be_transform_node(idx);
+ }
+
+ /* segment overrides are ineffective for Leas :-( so we have to patch
+ * around... */
+ if (addr->tls_segment) {
+ ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
+ assert(addr->symconst_ent != NULL);
+ if (base == noreg_GP)
+ base = tls_base;
+ else
+ base = new_bd_ia32_Lea(dbgi, block, tls_base, base);
+ addr->tls_segment = false;
}
- res = new_bd_ia32_Lea(dbgi, block, base, index);
+ res = new_bd_ia32_Lea(dbgi, block, base, idx);
set_address(res, addr);
return res;
match_commutative | match_mode_neutral | match_am | match_immediate);
}
+/**
+ * test wether 2 values result in 'x' and '32-x' when interpreted as a shift
+ * value.
+ */
+static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
+{
+ if (is_Const(value1) && is_Const(value2)) {
+ ir_tarval *tv1 = get_Const_tarval(value1);
+ ir_tarval *tv2 = get_Const_tarval(value2);
+ if (tarval_is_long(tv1) && tarval_is_long(tv2)) {
+ long v1 = get_tarval_long(tv1);
+ long v2 = get_tarval_long(tv2);
+ return v1 <= v2 && v2 == 32-v1;
+ }
+ }
+ return false;
+}
+typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block,
+ ir_node *high, ir_node *low,
+ ir_node *count);
+
+/**
+ * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
+ * op1 - target to be shifted
+ * op2 - contains bits to be shifted into target
+ * op3 - shift count
+ * Only op3 can be an immediate.
+ */
+static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block,
+ ir_node *high, ir_node *low, ir_node *count,
+ new_shiftd_func func)
+{
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_high = be_transform_node(high);
+ ir_node *new_low = be_transform_node(low);
+ ir_node *new_count;
+ ir_node *new_node;
+
+ /* the shift amount can be any mode that is bigger than 5 bits, since all
+ * other bits are ignored anyway */
+ while (is_Conv(count) &&
+ get_irn_n_edges(count) == 1 &&
+ mode_is_int(get_irn_mode(count))) {
+ assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
+ count = get_Conv_op(count);
+ }
+ new_count = create_immediate_or_transform(count, 0);
+
+ new_node = func(dbgi, new_block, new_high, new_low, new_count);
+ return new_node;
+}
+
+static ir_node *match_64bit_shift(ir_node *node)
+{
+ ir_node *op1 = get_Or_left(node);
+ ir_node *op2 = get_Or_right(node);
+
+ if (is_Shr(op1)) {
+ ir_node *tmp = op1;
+ op1 = op2;
+ op2 = tmp;
+ }
+
+ /* match ShlD operation */
+ if (is_Shl(op1) && is_Shr(op2)) {
+ ir_node *shl_right = get_Shl_right(op1);
+ ir_node *shl_left = get_Shl_left(op1);
+ ir_node *shr_right = get_Shr_right(op2);
+ ir_node *shr_left = get_Shr_left(op2);
+ /* constant ShlD operation */
+ if (is_complementary_shifts(shl_right, shr_right)) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right,
+ new_bd_ia32_ShlD);
+ }
+ /* constant ShrD operation */
+ if (is_complementary_shifts(shr_right, shl_right)) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right,
+ new_bd_ia32_ShrD);
+ }
+ /* lower_dw produces the following for ShlD:
+ * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */
+ if (is_Shr(shr_left) && is_Not(shr_right)
+ && is_Const_1(get_Shr_right(shr_left))
+ && get_Not_op(shr_right) == shl_right) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *val_h = get_Shr_left(shr_left);
+ return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right,
+ new_bd_ia32_ShlD);
+ }
+ /* lower_dw produces the following for ShrD:
+ * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */
+ if (is_Shl(shl_left) && is_Not(shl_right)
+ && is_Const_1(get_Shl_right(shl_left))
+ && get_Not_op(shl_right) == shr_right) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *val_h = get_Shl_left(shl_left);
+ return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right,
+ new_bd_ia32_ShrD);
+ }
+ }
+
+ return NULL;
+}
/**
* Creates an ia32 Or.
{
ir_node *op1 = get_Or_left(node);
ir_node *op2 = get_Or_right(node);
+ ir_node *res;
+
+ res = match_64bit_shift(node);
+ if (res != NULL)
+ return res;
assert (! mode_is_float(get_irn_mode(node)));
return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
*/
static ir_node *create_Div(ir_node *node)
{
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ int throws_exception = ir_throws_exception(node);
ir_node *mem;
ir_node *new_mem;
ir_node *op1;
addr->index, new_mem, am.new_op2,
am.new_op1, sign_extension);
}
+ ir_set_throws_exception(new_node, throws_exception);
set_irn_pinned(new_node, get_irn_pinned(node));
return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
}
-static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
- bool negate, ir_node *node)
+static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
+ bool negate, ir_node *node)
{
ir_node *new_block = be_transform_node(block);
ir_mode *mode = get_irn_mode(op);
- ir_node *new_op;
+ ir_node *new_op = be_transform_node(op);
ir_node *new_node;
int size;
ir_entity *ent;
- if (mode_is_float(mode)) {
- new_op = be_transform_node(op);
+ assert(mode_is_float(mode));
- if (ia32_cg_config.use_sse2) {
- ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
- new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
- noreg_GP, nomem, new_op, noreg_fp);
+ if (ia32_cg_config.use_sse2) {
+ ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
+ new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
+ noreg_GP, nomem, new_op, noreg_fp);
- size = get_mode_size_bits(mode);
- ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
+ size = get_mode_size_bits(mode);
+ ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_am_sc(new_node, ent);
+ set_ia32_am_sc(new_node, ent);
- SET_IA32_ORIG_NODE(new_node, node);
+ SET_IA32_ORIG_NODE(new_node, node);
- set_ia32_op_type(new_node, ia32_AddrModeS);
- set_ia32_ls_mode(new_node, mode);
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode);
- /* TODO, implement -Abs case */
- assert(!negate);
- } else {
- new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
- SET_IA32_ORIG_NODE(new_node, node);
- if (negate) {
- new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
- SET_IA32_ORIG_NODE(new_node, node);
- }
- }
+ /* TODO, implement -Abs case */
+ assert(!negate);
} else {
- ir_node *xorn;
- ir_node *sign_extension;
-
- if (get_mode_size_bits(mode) == 32) {
- new_op = be_transform_node(op);
- } else {
- new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
- }
-
- sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
-
- xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_op, sign_extension);
- SET_IA32_ORIG_NODE(xorn, node);
-
+ new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
+ SET_IA32_ORIG_NODE(new_node, node);
if (negate) {
- new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, sign_extension, xorn);
- } else {
- new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, xorn, sign_extension);
+ new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
+ SET_IA32_ORIG_NODE(new_node, node);
}
- SET_IA32_ORIG_NODE(new_node, node);
}
return new_node;
ir_node *new_mem = be_transform_node(mem);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_Load_mode(node);
+ int throws_exception = ir_throws_exception(node);
ir_node *base;
- ir_node *index;
+ ir_node *idx;
ir_node *new_node;
ia32_address_t addr;
/* construct load address */
memset(&addr, 0, sizeof(addr));
ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
- base = addr.base;
- index = addr.index;
+ base = addr.base;
+ idx = addr.index;
if (base == NULL) {
base = noreg_GP;
base = be_transform_node(base);
}
- if (index == NULL) {
- index = noreg_GP;
+ if (idx == NULL) {
+ idx = noreg_GP;
} else {
- index = be_transform_node(index);
+ idx = be_transform_node(idx);
}
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2) {
- new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
+ new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
mode);
} else {
- new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
+ new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem,
mode);
}
} else {
/* create a conv node with address mode for smaller modes */
if (get_mode_size_bits(mode) < 32) {
- new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
+ new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx,
new_mem, noreg_GP, mode);
} else {
- new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
+ new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem);
}
}
+ ir_set_throws_exception(new_node, throws_exception);
set_irn_pinned(new_node, get_irn_pinned(node));
set_ia32_op_type(new_node, ia32_AddrModeS);
be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
mem_proj = be_transform_node(am.mem_proj);
- be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
+ be_set_transformed_node(am.mem_proj, new_node);
+ be_set_transformed_node(mem_proj, new_node);
return new_node;
}
be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
mem_proj = be_transform_node(am.mem_proj);
- be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
+ be_set_transformed_node(am.mem_proj, new_node);
+ be_set_transformed_node(mem_proj, new_node);
return new_node;
}
dbg_info *dbgi = get_irn_dbg_info(node);
int ofs = 0;
int i = 0;
+ int throws_exception = ir_throws_exception(node);
ir_node *ins[4];
ia32_address_t addr;
ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, imm);
+ ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M);
+ ir_set_throws_exception(new_node, throws_exception);
set_irn_pinned(new_node, get_irn_pinned(node));
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode_Iu);
SET_IA32_ORIG_NODE(new_node, node);
assert(i < 4);
- ins[i++] = new_node;
+ ins[i++] = new_mem;
size -= 4;
ofs += 4;
if (i > 1) {
return new_rd_Sync(dbgi, new_block, i, ins);
} else {
- return ins[0];
+ return get_Proj_pred(ins[0]);
}
}
/**
* Generate a vfist or vfisttp instruction.
*/
-static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index,
- ir_node *mem, ir_node *val, ir_node **fist)
+static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base,
+ ir_node *index, ir_node *mem, ir_node *val)
{
- ir_node *new_node;
-
if (ia32_cg_config.use_fisttp) {
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res);
be_new_Keep(block, 1, &value);
- new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M);
- *fist = vfisttp;
+ return vfisttp;
} else {
ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
/* do a fist */
- new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
- *fist = new_node;
+ ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
+ return vfist;
}
- return new_node;
}
+
/**
* Transforms a general (no special case) Store.
*
ir_node *ptr = get_Store_ptr(node);
ir_node *mem = get_Store_mem(node);
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_val, *new_node, *store;
+ int throws_exception = ir_throws_exception(node);
+ ir_node *new_val;
+ ir_node *new_node;
ia32_address_t addr;
/* check for destination address mode */
new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
- store = new_node;
} else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
val = get_Conv_op(val);
/* TODO: is this optimisation still necessary at all (middleend)? */
- /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
+ /* We can skip ALL float->float up-Convs (and strict-up-Convs) before
+ * stores. */
while (is_Conv(val)) {
ir_node *op = get_Conv_op(val);
if (!mode_is_float(get_irn_mode(op)))
val = op;
}
new_val = be_transform_node(val);
- new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store);
+ new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
} else {
new_val = create_immediate_or_transform(val, 0);
assert(mode != mode_b);
new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val);
}
- store = new_node;
}
+ ir_set_throws_exception(new_node, throws_exception);
- set_irn_pinned(store, get_irn_pinned(node));
- set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_ls_mode(store, mode);
+ set_irn_pinned(new_node, get_irn_pinned(node));
+ set_ia32_op_type(new_node, ia32_AddrModeD);
+ set_ia32_ls_mode(new_node, mode);
- set_address(store, &addr);
- SET_IA32_ORIG_NODE(store, node);
+ set_address(new_node, &addr);
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
*/
static ir_node *create_Switch(ir_node *node)
{
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *sel = get_Cond_selector(node);
- ir_node *new_sel = be_transform_node(sel);
- long switch_min = LONG_MAX;
- long switch_max = LONG_MIN;
- long default_pn = get_Cond_default_proj(node);
- ir_node *new_node;
- const ir_edge_t *edge;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *sel = get_Cond_selector(node);
+ ir_node *new_sel = be_transform_node(sel);
+ long default_pn = get_Cond_default_proj(node);
+ ir_node *new_node;
+ ir_entity *entity;
assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
- /* determine the smallest switch case value */
- foreach_out_edge(node, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- long pn = get_Proj_proj(proj);
- if (pn == default_pn)
- continue;
-
- if (pn < switch_min)
- switch_min = pn;
- if (pn > switch_max)
- switch_max = pn;
- }
-
- if ((unsigned long) (switch_max - switch_min) > 128000) {
- panic("Size of switch %+F bigger than 128000", node);
- }
-
- if (switch_min != 0) {
- /* if smallest switch case is not 0 we need an additional sub */
- new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP);
- add_ia32_am_offs_int(new_sel, -switch_min);
- set_ia32_op_type(new_sel, ia32_AddrModeS);
-
- SET_IA32_ORIG_NODE(new_sel, node);
- }
+ entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
+ set_entity_visibility(entity, ir_visibility_private);
+ add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
- new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
+ /* TODO: we could perform some more matching here to also use the base
+ * register of the address mode */
+ new_node
+ = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, default_pn);
+ set_ia32_am_scale(new_node, 2);
+ set_ia32_am_sc(new_node, entity);
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode_Iu);
SET_IA32_ORIG_NODE(new_node, node);
+ // FIXME This seems wrong. GCC uses PIC for switch on OS X.
+ get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true;
return new_node;
}
match_commutative | match_am | match_16bit_am | match_mode_neutral);
if (am.ins_permuted)
- cc = ia32_invert_condition_code(cc);
+ cc = ia32_negate_condition_code(cc);
new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
addr->mem, am.new_op1, am.new_op2, new_flags,
++step;
res->steps[step].transform = SETCC_TR_NEG;
} else {
- int v = get_tarval_lowest_bit(t);
- assert(v >= 0);
+ int val = get_tarval_lowest_bit(t);
+ assert(val >= 0);
res->steps[step].transform = SETCC_TR_SHL;
- res->steps[step].scale = v;
+ res->steps[step].scale = val;
}
}
++step;
assert(get_irn_mode(sel) == mode_b);
- is_abs = be_mux_is_abs(sel, mux_true, mux_false);
+ is_abs = ir_mux_is_abs(sel, mux_true, mux_false);
if (is_abs != 0) {
- return create_abs(dbgi, block, be_get_abs_op(sel), is_abs < 0, node);
+ if (ia32_mode_needs_gp_reg(mode)) {
+ ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n",
+ node);
+ } else {
+ ir_node *op = ir_get_abs_op(sel, mux_true, mux_false);
+ return create_float_abs(dbgi, block, op, is_abs < 0, node);
+ }
}
/* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
am.addr.offset = 0;
am.addr.scale = scale;
am.addr.use_frame = 0;
+ am.addr.tls_segment = false;
am.addr.frame_entity = NULL;
am.addr.symconst_sign = 0;
am.mem_proj = am.addr.mem;
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_irn_mode(node);
+ ir_node *frame = get_irg_frame(irg);
ir_node *fist, *load, *mem;
- mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist);
+ fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op);
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
+ assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
+ mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
+
assert(get_mode_size_bits(mode) <= 32);
/* exception we can only store signed 32 bit integers, so for unsigned
we store a 64bit (signed) integer and load the lower bits */
ir_graph *irg = get_Block_irg(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *frame = get_irg_frame(irg);
+ ir_node *store_mem;
ir_node *store, *load;
ir_node *new_node;
set_ia32_op_type(store, ia32_AddrModeD);
SET_IA32_ORIG_NODE(store, node);
- load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode);
+ store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+
+ load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
SET_IA32_ORIG_NODE(load, node);
ir_mode *store_mode;
ir_node *fild;
ir_node *store;
+ ir_node *store_mem;
ir_node *new_node;
/* fild can use source AM if the operand is a signed 16bit or 32bit integer */
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Iu);
+ store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
+
/* exception for 32bit unsigned, do a 64bit spill+load */
if (!mode_is_signed(mode)) {
ir_node *in[2];
ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
noreg_GP, nomem, zero_const);
+ ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M);
set_ia32_use_frame(zero_store);
set_ia32_op_type(zero_store, ia32_AddrModeD);
add_ia32_am_offs_int(zero_store, 4);
set_ia32_ls_mode(zero_store, mode_Iu);
- in[0] = zero_store;
- in[1] = store;
+ in[0] = zero_store_mem;
+ in[1] = store_mem;
- store = new_rd_Sync(dbgi, block, 2, in);
+ store_mem = new_rd_Sync(dbgi, block, 2, in);
store_mode = mode_Ls;
} else {
store_mode = mode_Is;
}
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store);
+ fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
static ir_node *gen_be_Return(ir_node *node)
{
ir_graph *irg = current_ir_graph;
- ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
- ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
+ ir_node *ret_val = get_irn_n(node, n_be_Return_val);
+ ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
ir_node *new_ret_val = be_transform_node(ret_val);
ir_node *new_ret_mem = be_transform_node(ret_mem);
ir_entity *ent = get_irg_entity(irg);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_type *res_type;
ir_mode *mode;
- ir_node *frame, *sse_store, *fld, *mproj;
+ ir_node *frame;
+ ir_node *sse_store;
+ ir_node *store_mem;
+ ir_node *fld;
+ ir_node *mproj;
int i;
int arity;
unsigned pop;
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
+ store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
/* load into x87 register */
- fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode);
+ fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
*/
static ir_node *gen_be_AddSP(ir_node *node)
{
- ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
- ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
+ ir_node *sz = get_irn_n(node, n_be_AddSP_size);
+ ir_node *sp = get_irn_n(node, n_be_AddSP_old_sp);
ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP,
match_am | match_immediate);
*/
static ir_node *gen_be_SubSP(ir_node *node)
{
- ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
- ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
+ ir_node *sz = get_irn_n(node, n_be_SubSP_size);
+ ir_node *sp = get_irn_n(node, n_be_SubSP_old_sp);
ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP,
match_am | match_immediate);
return new_node;
}
-static ir_node *gen_ia32_l_ShlDep(ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
- ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
-
- return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
- match_immediate | match_mode_neutral);
-}
-
-static ir_node *gen_ia32_l_ShrDep(ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
- ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
- return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
- match_immediate);
-}
-
-static ir_node *gen_ia32_l_SarDep(ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
- ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
- return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
- match_immediate);
-}
-
static ir_node *gen_ia32_l_Add(ir_node *node)
{
ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
match_am | match_immediate | match_mode_neutral);
}
-/**
- * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
- * op1 - target to be shifted
- * op2 - contains bits to be shifted into target
- * op3 - shift count
- * Only op3 can be an immediate.
- */
-static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
- ir_node *low, ir_node *count)
-{
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_high = be_transform_node(high);
- ir_node *new_low = be_transform_node(low);
- ir_node *new_count;
- ir_node *new_node;
-
- /* the shift amount can be any mode that is bigger than 5 bits, since all
- * other bits are ignored anyway */
- while (is_Conv(count) &&
- get_irn_n_edges(count) == 1 &&
- mode_is_int(get_irn_mode(count))) {
- assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
- count = get_Conv_op(count);
- }
- new_count = create_immediate_or_transform(count, 0);
-
- if (is_ia32_l_ShlD(node)) {
- new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
- new_count);
- } else {
- new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
- new_count);
- }
- SET_IA32_ORIG_NODE(new_node, node);
-
- return new_node;
-}
-
-static ir_node *gen_ia32_l_ShlD(ir_node *node)
-{
- ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
- ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
- ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
- return gen_lowered_64bit_shifts(node, high, low, count);
-}
-
-static ir_node *gen_ia32_l_ShrD(ir_node *node)
-{
- ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
- ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
- ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
- return gen_lowered_64bit_shifts(node, high, low, count);
-}
-
static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
{
ir_node *src_block = get_nodes_block(node);
ir_node *new_val_high = be_transform_node(val_high);
ir_node *in[2];
ir_node *sync, *fild, *res;
- ir_node *store_low, *store_high;
+ ir_node *store_low;
+ ir_node *store_high;
+ ir_node *mem_low;
+ ir_node *mem_high;
if (ia32_cg_config.use_sse2) {
panic("ia32_l_LLtoFloat not implemented for SSE2");
SET_IA32_ORIG_NODE(store_low, node);
SET_IA32_ORIG_NODE(store_high, node);
+ mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M);
+ mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M);
+
set_ia32_use_frame(store_low);
set_ia32_use_frame(store_high);
set_ia32_op_type(store_low, ia32_AddrModeD);
set_ia32_ls_mode(store_high, mode_Is);
add_ia32_am_offs_int(store_high, 4);
- in[0] = store_low;
- in[1] = store_high;
+ in[0] = mem_low;
+ in[1] = mem_high;
sync = new_rd_Sync(dbgi, block, 2, in);
/* do a fild */
am.addr.offset = 0;
am.addr.scale = 2;
am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
+ am.addr.tls_segment = false;
am.addr.use_frame = 0;
am.addr.frame_entity = NULL;
am.addr.symconst_sign = 0;
ir_node *frame = get_irg_frame(irg);
ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
ir_node *new_val = be_transform_node(val);
- ir_node *fist, *mem;
+ ir_node *fist;
- mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist);
+ fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val);
SET_IA32_ORIG_NODE(fist, node);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
- return mem;
+ assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
+ return new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
}
static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
static ir_node *gen_Proj_Load(ir_node *node)
{
ir_node *new_pred;
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *pred = get_Proj_pred(node);
- dbg_info *dbgi = get_irn_dbg_info(node);
- long proj = get_Proj_proj(node);
+ ir_node *pred = get_Proj_pred(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
/* loads might be part of source address mode matches, so we don't
* transform the ProjMs yet (with the exception of loads whose result is
/* renumber the proj */
new_pred = be_transform_node(pred);
if (is_ia32_Load(new_pred)) {
- switch (proj) {
+ switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
- case pn_Load_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
}
} else if (is_ia32_Conv_I2I(new_pred) ||
is_ia32_Conv_I2I8Bit(new_pred)) {
set_irn_mode(new_pred, mode_T);
- if (proj == pn_Load_res) {
+ switch ((pn_Load)proj) {
+ case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
- } else if (proj == pn_Load_M) {
+ case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
+ case pn_Load_X_except:
+ /* This Load might raise an exception. Mark it. */
+ set_ia32_exc_label(new_pred, 1);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular);
}
} else if (is_ia32_xLoad(new_pred)) {
- switch (proj) {
+ switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
- case pn_Load_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
}
} else if (is_ia32_vfld(new_pred)) {
- switch (proj) {
+ switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
- case pn_Load_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular);
}
} else {
/* can happen for ProJMs when source address mode happened for the
return new_rd_Proj(dbgi, new_pred, mode_M, 1);
}
- panic("No idea how to transform proj");
+ panic("No idea how to transform Proj(Load) %+F", node);
+}
+
+static ir_node *gen_Proj_Store(ir_node *node)
+{
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long pn = get_Proj_proj(node);
+
+ if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
+ }
+ } else if (is_ia32_vfist(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular);
+ }
+ } else if (is_ia32_vfisttp(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular);
+ }
+ } else if (is_ia32_vfst(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular);
+ }
+ } else if (is_ia32_xStore(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular);
+ }
+ } else if (is_Sync(new_pred)) {
+ /* hack for the case that gen_float_const_Store produced a Sync */
+ if (pn == pn_Store_M) {
+ return new_pred;
+ }
+ panic("exception control flow for gen_float_const_Store not implemented yet");
+ } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) {
+ /* destination address mode */
+ if (pn == pn_Store_M) {
+ return new_pred;
+ }
+ panic("exception control flow for destination AM not implemented yet");
+ }
+
+ panic("No idea how to transform Proj(Store) %+F", node);
}
/**
*/
static ir_node *gen_Proj_Div(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
- long proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
- assert(pn_ia32_Div_M == pn_ia32_IDiv_M);
- assert(pn_ia32_Div_div_res == pn_ia32_IDiv_div_res);
+ assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
+ assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res);
- switch (proj) {
+ switch ((pn_Div)proj) {
case pn_Div_M:
if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
- case pn_Div_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Div_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
+ case pn_Div_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
}
panic("No idea how to transform proj->Div");
long proj = get_Proj_proj(node);
assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
- assert(pn_ia32_Div_M == pn_ia32_IDiv_M);
- assert(pn_ia32_Div_mod_res == pn_ia32_IDiv_mod_res);
+ assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
+ assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res);
- switch (proj) {
+ switch ((pn_Mod)proj) {
case pn_Mod_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
case pn_Mod_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
case pn_Mod_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
+ case pn_Mod_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
}
panic("No idea how to transform proj->Mod");
}
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
- switch (proj) {
+ switch ((pn_CopyB)proj) {
case pn_CopyB_M:
if (is_ia32_CopyB_i(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
}
break;
- default:
+ case pn_CopyB_X_regular:
+ if (is_ia32_CopyB_i(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular);
+ } else if (is_ia32_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular);
+ }
+ break;
+ case pn_CopyB_X_except:
+ if (is_ia32_CopyB_i(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except);
+ } else if (is_ia32_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except);
+ }
break;
}
dbg_info *const dbgi = get_irn_dbg_info(node);
ir_node *const src_block = get_nodes_block(node);
ir_node *const block = be_transform_node(src_block);
- ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
- ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp);
+ ir_node *const src_mem = get_irn_n(node, n_be_Call_mem);
+ ir_node *const src_sp = get_irn_n(node, n_be_Call_sp);
ir_node *const sp = be_transform_node(src_sp);
- ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr);
+ ir_node *const src_ptr = get_irn_n(node, n_be_Call_ptr);
ia32_address_mode_t am;
ia32_address_t *const addr = &am.addr;
ir_node * mem;
unsigned const pop = be_Call_get_pop(node);
ir_type *const call_tp = be_Call_get_type(node);
int old_no_pic_adjust;
+ int throws_exception = ir_throws_exception(node);
/* Run the x87 simulator if the call returns a float value */
if (get_method_n_ress(call_tp) > 0) {
i = get_irn_arity(node) - 1;
fpcw = be_transform_node(get_irn_n(node, i--));
- for (; i >= be_pos_Call_first_arg; --i) {
+ for (; i >= n_be_Call_first_arg; --i) {
arch_register_req_t const *const req = arch_get_register_req(node, i);
ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
+ ir_set_throws_exception(call, throws_exception);
set_am_attributes(call, &am);
call = fix_mem_proj(call, &am);
ir_node *frame = get_Builtin_param(node, 1);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_tarval *tv = get_Const_tarval(param);
+ ir_graph *irg = get_irn_irg(node);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
set_ia32_am_offs_int(load, 0);
set_ia32_use_frame(load);
- set_ia32_frame_ent(load, ia32_get_return_address_entity());
+ set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
if (get_irn_pinned(node) == op_pin_state_floats) {
assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
ir_node *frame = get_Builtin_param(node, 1);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_tarval *tv = get_Const_tarval(param);
+ ir_graph *irg = get_irn_irg(node);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_ls_mode(load, mode_Iu);
- ent = ia32_get_frame_address_entity();
+ ent = ia32_get_frame_address_entity(irg);
if (ent != NULL) {
set_ia32_am_offs_int(load, 0);
set_ia32_use_frame(load);
static ir_node *gen_prefetch(ir_node *node)
{
dbg_info *dbgi;
- ir_node *ptr, *block, *mem, *base, *index;
+ ir_node *ptr, *block, *mem, *base, *idx;
ir_node *param, *new_node;
long rw, locality;
ir_tarval *tv;
memset(&addr, 0, sizeof(addr));
ptr = get_Builtin_param(node, 0);
ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
- base = addr.base;
- index = addr.index;
+ base = addr.base;
+ idx = addr.index;
if (base == NULL) {
base = noreg_GP;
base = be_transform_node(base);
}
- if (index == NULL) {
- index = noreg_GP;
+ if (idx == NULL) {
+ idx = noreg_GP;
} else {
- index = be_transform_node(index);
+ idx = be_transform_node(idx);
}
dbgi = get_irn_dbg_info(node);
if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
/* we have 3DNow!, this was already checked above */
- new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem);
} else if (ia32_cg_config.use_sse_prefetch) {
/* note: rw == 1 is IGNORED in that case */
param = get_Builtin_param(node, 2);
/* SSE style prefetch */
switch (locality) {
case 0:
- new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem);
break;
case 1:
- new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem);
break;
case 2:
- new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem);
break;
default:
- new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem);
break;
}
} else {
assert(ia32_cg_config.use_3dnow_prefetch);
/* 3DNow! style prefetch */
- new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem);
}
set_irn_pinned(new_node, get_irn_pinned(node));
ir_mode *mode = get_irn_mode(node);
ir_node *res;
- if (proj == pn_be_Call_M_regular) {
+ if (proj == pn_be_Call_M) {
return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
}
/* transform call modes */
/* Map from be_Call to ia32_Call proj number */
if (proj == pn_be_Call_sp) {
proj = pn_ia32_Call_stack;
- } else if (proj == pn_be_Call_M_regular) {
+ } else if (proj == pn_be_Call_M) {
proj = pn_ia32_Call_M;
+ } else if (proj == pn_be_Call_X_except) {
+ proj = pn_ia32_Call_X_except;
+ } else if (proj == pn_be_Call_X_regular) {
+ proj = pn_ia32_Call_X_regular;
} else {
arch_register_req_t const *const req = arch_get_register_req_out(node);
int const n_outs = arch_irn_get_n_outs(new_call);
/* TODO arch_set_irn_register() only operates on Projs, need variant with index */
switch (proj) {
- case pn_ia32_Call_stack:
- arch_set_irn_register(res, &ia32_registers[REG_ESP]);
- break;
+ case pn_ia32_Call_stack:
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
+ break;
- case pn_ia32_Call_fpcw:
- arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
- break;
+ case pn_ia32_Call_fpcw:
+ arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
+ break;
}
return res;
long proj;
switch (get_irn_opcode(pred)) {
- case iro_Store:
- proj = get_Proj_proj(node);
- if (proj == pn_Store_M) {
- return be_transform_node(pred);
- } else {
- panic("No idea how to transform proj->Store");
- }
case iro_Load:
return gen_Proj_Load(node);
+ case iro_Store:
+ return gen_Proj_Store(node);
case iro_ASM:
return gen_Proj_ASM(node);
case iro_Builtin:
return jump;
}
-
- case pn_Start_P_tls:
- return ia32_gen_Proj_tls(node);
}
break;
be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
- be_set_transform_function(op_ia32_l_SarDep, gen_ia32_l_SarDep);
be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
- be_set_transform_function(op_ia32_l_ShlDep, gen_ia32_l_ShlDep);
- be_set_transform_function(op_ia32_l_ShlD, gen_ia32_l_ShlD);
- be_set_transform_function(op_ia32_l_ShrDep, gen_ia32_l_ShrDep);
- be_set_transform_function(op_ia32_l_ShrD, gen_ia32_l_ShrD);
be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
ir_graph *irg = current_ir_graph;
ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
- irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
- irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
- irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
- assert(irg_data->fpu_trunc_mode == NULL);
- assert(irg_data->get_eip == NULL);
+ irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
+ irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
+ irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
+ irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
+ irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
nomem = get_irg_no_mem(irg);
noreg_GP = ia32_new_NoReg_gp(irg);
-
- get_fpcw();
}
/**
ir_type *res_tp = get_method_res_type(mtp, j);
ir_node *res, *new_res;
const ir_edge_t *edge, *next;
- ir_mode *mode;
+ ir_mode *res_mode;
if (! is_atomic_type(res_tp)) {
/* no floating point return */
continue;
}
- mode = get_type_mode(res_tp);
- if (! mode_is_float(mode)) {
+ res_mode = get_type_mode(res_tp);
+ if (! mode_is_float(res_mode)) {
/* no floating point return */
continue;
}
dbg_info *db = get_irn_dbg_info(succ);
ir_node *block = get_nodes_block(succ);
ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
- ir_node *index = get_irn_n(succ, n_ia32_xStore_index);
+ ir_node *idx = get_irn_n(succ, n_ia32_xStore_index);
ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
ir_mode *mode = get_ia32_ls_mode(succ);
- ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode);
+ ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode);
+ //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M);
set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
if (is_ia32_use_frame(succ))
set_ia32_use_frame(st);
set_irn_pinned(st, get_irn_pinned(succ));
set_ia32_op_type(st, ia32_AddrModeD);
+ assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M);
+ assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular);
+ assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except);
+
exchange(succ, st);
- } else {
- if (new_res == NULL) {
- dbg_info *db = get_irn_dbg_info(call);
- ir_node *block = get_nodes_block(call);
- ir_node *frame = get_irg_frame(current_ir_graph);
- ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
- ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
- ir_node *vfst, *xld, *new_mem;
-
- /* store st(0) on stack */
- vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode);
- set_ia32_op_type(vfst, ia32_AddrModeD);
- set_ia32_use_frame(vfst);
-
- /* load into SSE register */
- xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode);
- set_ia32_op_type(xld, ia32_AddrModeS);
- set_ia32_use_frame(xld);
-
- new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res);
- new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
-
- if (old_mem != NULL) {
- edges_reroute(old_mem, new_mem, current_ir_graph);
- kill_node(old_mem);
- }
+ } else if (new_res == NULL) {
+ dbg_info *db = get_irn_dbg_info(call);
+ ir_node *block = get_nodes_block(call);
+ ir_node *frame = get_irg_frame(current_ir_graph);
+ ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
+ ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
+ ir_node *vfst, *xld, *new_mem;
+ ir_node *vfst_mem;
+
+ /* store st(0) on stack */
+ vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem,
+ res, res_mode);
+ set_ia32_op_type(vfst, ia32_AddrModeD);
+ set_ia32_use_frame(vfst);
+
+ vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M);
+
+ /* load into SSE register */
+ xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
+ res_mode);
+ set_ia32_op_type(xld, ia32_AddrModeS);
+ set_ia32_use_frame(xld);
+
+ new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res);
+ new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
+
+ if (old_mem != NULL) {
+ edges_reroute(old_mem, new_mem);
+ kill_node(old_mem);
}
- set_irn_n(succ, get_edge_src_pos(edge), new_res);
}
+ set_irn_n(succ, get_edge_src_pos(edge), new_res);
}
}
}
initial_fpcw = NULL;
ia32_no_pic_adjust = 0;
+ old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]);
+
be_timer_push(T_HEIGHTS);
ia32_heights = heights_new(irg);
be_timer_pop(T_HEIGHTS);
projects / libfirm / blobdiff