end:
#endif /* CONSTRUCT_SSE_CONST */
SET_IA32_ORIG_NODE(load, node);
-
- be_dep_on_frame(load);
return res;
} else { /* non-float mode */
ir_node *cnst;
cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, 0, val);
SET_IA32_ORIG_NODE(cnst, node);
- be_dep_on_frame(cnst);
return cnst;
}
}
SET_IA32_ORIG_NODE(cnst, node);
- be_dep_on_frame(cnst);
return cnst;
}
} else {
new_op1 = be_transform_node(op2);
new_op2 = noreg;
- am->ins_permuted = 1;
+ am->ins_permuted = true;
}
am->op_type = ia32_AddrModeS;
} else {
/* lowered shift instruction may have a dependency operand, handle it here */
if (get_irn_arity(node) == 3) {
/* we have a dependency */
- ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
- add_irn_dep(new_node, new_dep);
+ ir_node* dep = get_irn_n(node, 2);
+ if (get_irn_n_edges(dep) > 1) {
+ /* ... which has at least one user other than 'node' */
+ ir_node *new_dep = be_transform_node(dep);
+ add_irn_dep(new_node, new_dep);
+ }
}
return new_node;
if (addr.base == NULL && addr.index == NULL) {
new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
addr.symconst_sign, 0, addr.offset);
- be_dep_on_frame(new_node);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
ins[n++] = be_transform_node(pred);
}
- ins[n++] = am_mem;
+ if (n==1 && ins[0] == am_mem) {
+ return am_mem;
+ /* creating a new Sync and relying on CSE may fail,
+ * if am_mem is a ProjM, which does not yet verify. */
+ }
+ ins[n++] = am_mem;
return new_r_Sync(block, n, ins);
} else {
ir_node *ins[2];
(void)orig;
if (ia32_cg_config.use_short_sex_eax) {
ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
- be_dep_on_frame(pval);
res = new_bd_ia32_Cltd(dbgi, block, val, pval);
} else {
ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
} else {
sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0, 0);
- be_dep_on_frame(sign_extension);
new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
addr->index, new_mem, am.new_op2,
return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
}
-/**
- * Transform a node returning a "flag" result.
- *
- * @param node the node to transform
- * @param pnc_out the compare mode to use
- */
-static ir_node *get_flags_node(ir_node *node, int *pnc_out)
+static ia32_condition_code_t relation_to_condition_code(ir_relation relation,
+ ir_mode *mode)
{
- ir_node *flags;
- ir_node *new_op;
- ir_node *new_block;
- dbg_info *dbgi;
+ if (mode_is_float(mode)) {
+ switch (relation) {
+ case ir_relation_equal: return ia32_cc_float_equal;
+ case ir_relation_less: return ia32_cc_float_below;
+ case ir_relation_less_equal: return ia32_cc_float_below_equal;
+ case ir_relation_greater: return ia32_cc_float_above;
+ case ir_relation_greater_equal: return ia32_cc_float_above_equal;
+ case ir_relation_less_greater: return ia32_cc_not_equal;
+ case ir_relation_less_equal_greater: return ia32_cc_not_parity;
+ case ir_relation_unordered: return ia32_cc_parity;
+ case ir_relation_unordered_equal: return ia32_cc_equal;
+ case ir_relation_unordered_less: return ia32_cc_float_unordered_below;
+ case ir_relation_unordered_less_equal:
+ return ia32_cc_float_unordered_below_equal;
+ case ir_relation_unordered_greater:
+ return ia32_cc_float_unordered_above;
+ case ir_relation_unordered_greater_equal:
+ return ia32_cc_float_unordered_above_equal;
+ case ir_relation_unordered_less_greater:
+ return ia32_cc_float_not_equal;
+ case ir_relation_false:
+ case ir_relation_true:
+ /* should we introduce a jump always/jump never? */
+ break;
+ }
+ panic("Unexpected float pnc");
+ } else if (mode_is_signed(mode)) {
+ switch (relation) {
+ case ir_relation_unordered_equal:
+ case ir_relation_equal: return ia32_cc_equal;
+ case ir_relation_unordered_less:
+ case ir_relation_less: return ia32_cc_less;
+ case ir_relation_unordered_less_equal:
+ case ir_relation_less_equal: return ia32_cc_less_equal;
+ case ir_relation_unordered_greater:
+ case ir_relation_greater: return ia32_cc_greater;
+ case ir_relation_unordered_greater_equal:
+ case ir_relation_greater_equal: return ia32_cc_greater_equal;
+ case ir_relation_unordered_less_greater:
+ case ir_relation_less_greater: return ia32_cc_not_equal;
+ case ir_relation_less_equal_greater:
+ case ir_relation_unordered:
+ case ir_relation_false:
+ case ir_relation_true:
+ /* introduce jump always/jump never? */
+ break;
+ }
+ panic("Unexpected pnc");
+ } else {
+ switch (relation) {
+ case ir_relation_unordered_equal:
+ case ir_relation_equal: return ia32_cc_equal;
+ case ir_relation_unordered_less:
+ case ir_relation_less: return ia32_cc_below;
+ case ir_relation_unordered_less_equal:
+ case ir_relation_less_equal: return ia32_cc_below_equal;
+ case ir_relation_unordered_greater:
+ case ir_relation_greater: return ia32_cc_above;
+ case ir_relation_unordered_greater_equal:
+ case ir_relation_greater_equal: return ia32_cc_above_equal;
+ case ir_relation_unordered_less_greater:
+ case ir_relation_less_greater: return ia32_cc_not_equal;
+ case ir_relation_less_equal_greater:
+ case ir_relation_unordered:
+ case ir_relation_false:
+ case ir_relation_true:
+ /* introduce jump always/jump never? */
+ break;
+ }
+ panic("Unexpected pnc");
+ }
+}
- /* we have a Cmp as input */
- if (is_Proj(node)) {
- ir_node *pred = get_Proj_pred(node);
- if (is_Cmp(pred)) {
- int pnc = get_Proj_pn_cmp(node);
- if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
- ir_node *l = get_Cmp_left(pred);
- ir_node *r = get_Cmp_right(pred);
- if (is_And(l)) {
- ir_node *la = get_And_left(l);
- ir_node *ra = get_And_right(l);
- if (is_Shl(la)) {
- ir_node *c = get_Shl_left(la);
- if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
- /* (1 << n) & ra) */
- ir_node *n = get_Shl_right(la);
- flags = gen_bt(pred, ra, n);
- /* we must generate a Jc/Jnc jump */
- pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
- if (r == la)
- pnc ^= pn_Cmp_Leg;
- *pnc_out = ia32_pn_Cmp_unsigned | pnc;
- return flags;
- }
- }
- if (is_Shl(ra)) {
- ir_node *c = get_Shl_left(ra);
- if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
- /* la & (1 << n)) */
- ir_node *n = get_Shl_right(ra);
- flags = gen_bt(pred, la, n);
- /* we must generate a Jc/Jnc jump */
- pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
- if (r == ra)
- pnc ^= pn_Cmp_Leg;
- *pnc_out = ia32_pn_Cmp_unsigned | pnc;
- return flags;
- }
- }
- }
- }
- /* add ia32 compare flags */
- {
- ir_node *l = get_Cmp_left(pred);
- ir_mode *mode = get_irn_mode(l);
- if (mode_is_float(mode))
- pnc |= ia32_pn_Cmp_float;
- else if (! mode_is_signed(mode))
- pnc |= ia32_pn_Cmp_unsigned;
+static ir_node *get_flags_mode_b(ir_node *node, ia32_condition_code_t *cc_out)
+{
+ /* a mode_b value, we have to compare it against 0 */
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_block = be_transform_node(get_nodes_block(node));
+ ir_node *new_op = be_transform_node(node);
+ ir_node *flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, new_op, false);
+ *cc_out = ia32_cc_not_equal;
+ return flags;
+}
+
+static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out)
+{
+ /* must have a Cmp as input */
+ ir_relation relation = get_Cmp_relation(cmp);
+ ir_relation possible;
+ ir_node *l = get_Cmp_left(cmp);
+ ir_node *r = get_Cmp_right(cmp);
+ ir_mode *mode = get_irn_mode(l);
+ ir_node *flags;
+
+ /* check for bit-test */
+ if (ia32_cg_config.use_bt && (relation == ir_relation_equal
+ || (mode_is_signed(mode) && relation == ir_relation_less_greater)
+ || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))
+ && is_And(l)) {
+ ir_node *la = get_And_left(l);
+ ir_node *ra = get_And_right(l);
+ if (is_Shl(ra)) {
+ ir_node *tmp = la;
+ la = ra;
+ ra = tmp;
+ }
+ if (is_Shl(la)) {
+ ir_node *c = get_Shl_left(la);
+ if (is_Const_1(c) && is_Const_0(r)) {
+ /* (1 << n) & ra) */
+ ir_node *n = get_Shl_right(la);
+ flags = gen_bt(cmp, ra, n);
+ /* the bit is copied into the CF flag */
+ if (relation & ir_relation_equal)
+ *cc_out = ia32_cc_above_equal; /* test for CF=0 */
+ else
+ *cc_out = ia32_cc_below; /* test for CF=1 */
+ return flags;
}
- *pnc_out = pnc;
- flags = be_transform_node(pred);
- return flags;
}
}
- /* a mode_b value, we have to compare it against 0 */
- dbgi = get_irn_dbg_info(node);
- new_block = be_transform_node(get_nodes_block(node));
- new_op = be_transform_node(node);
- flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op,
- new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
- *pnc_out = pn_Cmp_Lg;
+ /* the middle-end tries to eliminate impossible relations, so a ptr != 0
+ * test becomes ptr > 0. But for x86 an equal comparison is preferable to
+ * a >0 (we can sometimes eliminate the cmp in favor of flags produced by
+ * a predecessor node). So add the < bit */
+ possible = ir_get_possible_cmp_relations(l, r);
+ if (((relation & ir_relation_less) && !(possible & ir_relation_greater))
+ || ((relation & ir_relation_greater) && !(possible & ir_relation_less)))
+ relation |= ir_relation_less_greater;
+
+ /* just do a normal transformation of the Cmp */
+ *cc_out = relation_to_condition_code(relation, mode);
+ flags = be_transform_node(cmp);
return flags;
}
+/**
+ * Transform a node returning a "flag" result.
+ *
+ * @param node the node to transform
+ * @param cc_out the compare mode to use
+ */
+static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out)
+{
+ if (is_Cmp(node))
+ return get_flags_node_cmp(node, cc_out);
+ assert(get_irn_mode(node) == mode_b);
+ return get_flags_mode_b(node, cc_out);
+}
+
/**
* Transforms a Load.
*
static ir_node *gen_Load(ir_node *node)
{
ir_node *old_block = get_nodes_block(node);
- ir_node *block = be_transform_node(old_block);
- ir_node *ptr = get_Load_ptr(node);
- ir_node *mem = get_Load_mem(node);
- ir_node *new_mem = be_transform_node(mem);
+ ir_node *block = be_transform_node(old_block);
+ ir_node *ptr = get_Load_ptr(node);
+ ir_node *mem = get_Load_mem(node);
+ ir_node *new_mem = be_transform_node(mem);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_Load_mode(node);
ir_node *base;
ir_node *index;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_Load_mode(node);
ir_node *new_node;
ia32_address_t addr;
SET_IA32_ORIG_NODE(new_node, node);
- be_dep_on_frame(new_node);
return new_node;
}
return new_node;
}
-static int ia32_get_negated_pnc(int pnc)
-{
- ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
- return get_negated_pnc(pnc, mode);
-}
-
static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
{
- ir_mode *mode = get_irn_mode(node);
- ir_node *mux_true = get_Mux_true(node);
- ir_node *mux_false = get_Mux_false(node);
- ir_node *cond;
- dbg_info *dbgi;
- ir_node *block;
- ir_node *new_block;
- ir_node *flags;
- ir_node *new_node;
- bool negated;
- int pnc;
- ia32_address_t addr;
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
+ ir_node *cond;
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_node *new_block;
+ ir_node *flags;
+ ir_node *new_node;
+ bool negated;
+ ia32_condition_code_t cc;
+ ia32_address_t addr;
if (get_mode_size_bits(mode) != 8)
return NULL;
}
cond = get_Mux_sel(node);
- flags = get_flags_node(cond, &pnc);
+ flags = get_flags_node(cond, &cc);
/* we can't handle the float special cases with SetM */
- if (pnc & ia32_pn_Cmp_float)
+ if (cc & ia32_cc_additional_float_cases)
return NULL;
if (negated)
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
build_address_ptr(&addr, ptr, mem);
block = get_nodes_block(node);
new_block = be_transform_node(block);
new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
- addr.index, addr.mem, flags, pnc);
+ addr.index, addr.mem, flags, cc);
set_address(new_node, &addr);
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode);
*/
static ir_node *gen_Cond(ir_node *node)
{
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *sel = get_Cond_selector(node);
- ir_mode *sel_mode = get_irn_mode(sel);
- ir_node *flags = NULL;
- ir_node *new_node;
- int pnc;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *sel = get_Cond_selector(node);
+ ir_mode *sel_mode = get_irn_mode(sel);
+ ir_node *flags = NULL;
+ ir_node *new_node;
+ ia32_condition_code_t cc;
if (sel_mode != mode_b) {
return create_Switch(node);
}
/* we get flags from a Cmp */
- flags = get_flags_node(sel, &pnc);
+ flags = get_flags_node(sel, &cc);
- new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc);
+ new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, cc);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
return new_node;
}
-/**
- * helper function: checks whether all Cmp projs are Lg or Eq which is needed
- * to fold an and into a test node
- */
-static bool can_fold_test_and(ir_node *node)
-{
- const ir_edge_t *edge;
-
- /** we can only have eq and lg projs */
- foreach_out_edge(node, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- pn_Cmp pnc = get_Proj_pn_cmp(proj);
- if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
- return false;
- }
-
- return true;
-}
-
/**
* returns true if it is assured, that the upper bits of a node are "clean"
* which means for a 16 or 8 bit value, that the upper bits in the register
ir_node *new_node;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
- int cmp_unsigned;
if (mode_is_float(cmp_mode)) {
if (ia32_cg_config.use_sse2) {
assert(ia32_mode_needs_gp_reg(cmp_mode));
/* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
- cmp_unsigned = !mode_is_signed(cmp_mode);
if (is_Const_0(right) &&
is_And(left) &&
- get_irn_n_edges(left) == 1 &&
- can_fold_test_and(node)) {
+ get_irn_n_edges(left) == 1) {
/* Test(and_left, and_right) */
ir_node *and_left = get_And_left(left);
ir_node *and_right = get_And_right(left);
if (get_mode_size_bits(cmp_mode) == 8) {
new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted,
- cmp_unsigned);
+ addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
} else {
new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
+ addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
}
} else {
/* Cmp(left, right) */
if (get_mode_size_bits(cmp_mode) == 8) {
new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted,
- cmp_unsigned);
+ am.new_op2, am.ins_permuted);
} else {
new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
+ addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
}
}
set_am_attributes(new_node, &am);
}
static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
- int pnc)
+ ia32_condition_code_t cc)
{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
match_commutative | match_am | match_16bit_am | match_mode_neutral);
if (am.ins_permuted)
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_invert_condition_code(cc);
new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
addr->mem, am.new_op1, am.new_op2, new_flags,
- pnc);
+ cc);
set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, node);
* Creates a ia32 Setcc instruction.
*/
static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
- ir_node *flags, int pnc,
+ ir_node *flags, ia32_condition_code_t cc,
ir_node *orig_node)
{
ir_mode *mode = get_irn_mode(orig_node);
ir_node *new_node;
- new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, pnc);
+ new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, cc);
SET_IA32_ORIG_NODE(new_node, orig_node);
/* we might need to conv the result up */
if (is_Proj(new_node)) {
sub = get_Proj_pred(new_node);
- assert(is_ia32_Sub(sub));
} else {
sub = new_node;
set_irn_mode(sub, mode_T);
new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res);
}
+ assert(is_ia32_Sub(sub));
eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
dbgi = get_irn_dbg_info(psi);
};
typedef struct setcc_transform {
- unsigned num_steps;
- int pnc;
+ unsigned num_steps;
+ ia32_condition_code_t cc;
struct {
enum setcc_transform_insn transform;
long val;
* Find a transformation that creates 0 and 1 from
* tv_t and tv_f.
*/
-static void find_const_transform(int pnc, ir_tarval *t, ir_tarval *f,
+static void find_const_transform(ia32_condition_code_t cc,
+ ir_tarval *t, ir_tarval *f,
setcc_transform_t *res)
{
unsigned step = 0;
ir_tarval *tmp = t;
t = f;
f = tmp;
- pnc = ia32_get_negated_pnc(pnc);
- } else if (tarval_cmp(t, f) == pn_Cmp_Lt) {
+ cc = ia32_negate_condition_code(cc);
+ } else if (tarval_cmp(t, f) == ir_relation_less) {
// now, t is the bigger one
ir_tarval *tmp = t;
t = f;
f = tmp;
- pnc = ia32_get_negated_pnc(pnc);
+ cc = ia32_negate_condition_code(cc);
}
- res->pnc = pnc;
+ res->cc = cc;
if (! tarval_is_null(f)) {
ir_tarval *t_sub = tarval_sub(t, f, NULL);
*/
static ir_node *gen_Mux(ir_node *node)
{
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- ir_node *mux_true = get_Mux_true(node);
- ir_node *mux_false = get_Mux_false(node);
- ir_node *cond = get_Mux_sel(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *flags;
- ir_node *new_node;
- int is_abs;
- int pnc;
-
- assert(get_irn_mode(cond) == mode_b);
-
- is_abs = be_mux_is_abs(cond, mux_true, mux_false);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
+ ir_node *sel = get_Mux_sel(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *flags;
+ ir_node *new_node;
+ int is_abs;
+ ia32_condition_code_t cc;
+
+ assert(get_irn_mode(sel) == mode_b);
+
+ is_abs = be_mux_is_abs(sel, mux_true, mux_false);
if (is_abs != 0) {
- return create_abs(dbgi, block, be_get_abs_op(cond), is_abs < 0, node);
+ return create_abs(dbgi, block, be_get_abs_op(sel), is_abs < 0, node);
}
/* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
if (mode_is_float(mode)) {
- ir_node *cmp = get_Proj_pred(cond);
- ir_node *cmp_left = get_Cmp_left(cmp);
- ir_node *cmp_right = get_Cmp_right(cmp);
- int pnc = get_Proj_proj(cond);
+ ir_node *cmp_left = get_Cmp_left(sel);
+ ir_node *cmp_right = get_Cmp_right(sel);
+ ir_relation relation = get_Cmp_relation(sel);
if (ia32_cg_config.use_sse2) {
- if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
+ if (relation == ir_relation_less || relation == ir_relation_less_equal) {
if (cmp_left == mux_true && cmp_right == mux_false) {
/* Mux(a <= b, a, b) => MIN */
return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
match_commutative | match_am | match_two_users);
}
- } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
+ } else if (relation == ir_relation_greater || relation == ir_relation_greater_equal) {
if (cmp_left == mux_true && cmp_right == mux_false) {
/* Mux(a >= b, a, b) => MAX */
return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
ir_mode *new_mode;
unsigned scale;
- flags = get_flags_node(cond, &pnc);
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
+ flags = get_flags_node(sel, &cc);
+ new_node = create_set_32bit(dbgi, new_block, flags, cc, node);
if (ia32_cg_config.use_sse2) {
/* cannot load from different mode on SSE */
case 16:
/* arg, shift 16 NOT supported */
scale = 3;
- new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, new_node);
+ new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
break;
default:
panic("Unsupported constant size");
am.new_op2 = NULL;
am.pinned = op_pin_state_floats;
am.commutative = 1;
- am.ins_permuted = 0;
+ am.ins_permuted = false;
if (ia32_cg_config.use_sse2)
load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
} else {
assert(ia32_mode_needs_gp_reg(mode));
- if (is_Proj(cond)) {
- ir_node *cmp = get_Proj_pred(cond);
- if (is_Cmp(cmp)) {
- ir_node *cmp_left = get_Cmp_left(cmp);
- ir_node *cmp_right = get_Cmp_right(cmp);
- ir_node *val_true = mux_true;
- ir_node *val_false = mux_false;
- int pnc = get_Proj_proj(cond);
-
- if (is_Const(val_true) && is_Const_null(val_true)) {
- ir_node *tmp = val_false;
- val_false = val_true;
- val_true = tmp;
- pnc = ia32_get_negated_pnc(pnc);
+ if (is_Cmp(sel)) {
+ ir_node *cmp_left = get_Cmp_left(sel);
+ ir_node *cmp_right = get_Cmp_right(sel);
+ ir_relation relation = get_Cmp_relation(sel);
+ ir_node *val_true = mux_true;
+ ir_node *val_false = mux_false;
+
+ if (is_Const(val_true) && is_Const_null(val_true)) {
+ ir_node *tmp = val_false;
+ val_false = val_true;
+ val_true = tmp;
+ relation = get_negated_relation(relation);
+ }
+ if (is_Const_0(val_false) && is_Sub(val_true)) {
+ if ((relation & ir_relation_greater)
+ && get_Sub_left(val_true) == cmp_left
+ && get_Sub_right(val_true) == cmp_right) {
+ return create_doz(node, cmp_left, cmp_right);
}
- if (is_Const_0(val_false) && is_Sub(val_true)) {
- if ((pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge)
- && get_Sub_left(val_true) == cmp_left
- && get_Sub_right(val_true) == cmp_right) {
- return create_doz(node, cmp_left, cmp_right);
- }
- if ((pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le)
- && get_Sub_left(val_true) == cmp_right
- && get_Sub_right(val_true) == cmp_left) {
- return create_doz(node, cmp_right, cmp_left);
- }
+ if ((relation & ir_relation_less)
+ && get_Sub_left(val_true) == cmp_right
+ && get_Sub_right(val_true) == cmp_left) {
+ return create_doz(node, cmp_right, cmp_left);
}
}
}
- flags = get_flags_node(cond, &pnc);
+ flags = get_flags_node(sel, &cc);
if (is_Const(mux_true) && is_Const(mux_false)) {
/* both are const, good */
setcc_transform_t res;
int step;
- find_const_transform(pnc, tv_true, tv_false, &res);
+ find_const_transform(cc, tv_true, tv_false, &res);
new_node = node;
for (step = (int)res.num_steps - 1; step >= 0; --step) {
ir_node *imm;
switch (res.steps[step].transform) {
case SETCC_TR_ADD:
- imm = ia32_immediate_from_long(res.steps[step].val);
- new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
+ new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, noreg_GP);
+ add_ia32_am_offs_int(new_node, res.steps[step].val);
break;
case SETCC_TR_ADDxx:
new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
break;
case SETCC_TR_SET:
- new_node = create_set_32bit(dbgi, new_block, flags, res.pnc, node);
+ new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
break;
case SETCC_TR_SBB:
new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
}
}
} else {
- new_node = create_CMov(node, cond, flags, pnc);
+ new_node = create_CMov(node, sel, flags, cc);
}
return new_node;
}
*/
static ir_node *gen_be_Return(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
- ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
- ir_entity *ent = get_irg_entity(irg);
- ir_type *tp = get_entity_type(ent);
- dbg_info *dbgi;
- ir_node *block;
+ ir_graph *irg = current_ir_graph;
+ ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
+ ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
+ ir_node *new_ret_val = be_transform_node(ret_val);
+ ir_node *new_ret_mem = be_transform_node(ret_mem);
+ ir_entity *ent = get_irg_entity(irg);
+ ir_type *tp = get_entity_type(ent);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
ir_type *res_type;
ir_mode *mode;
- ir_node *frame, *sse_store, *fld, *mproj, *barrier;
- ir_node *new_barrier, *new_ret_val, *new_ret_mem;
- ir_node **in;
- int pn_ret_val, pn_ret_mem, arity, i;
+ ir_node *frame, *sse_store, *fld, *mproj;
+ int i;
+ int arity;
+ unsigned pop;
+ ir_node **in;
+ ir_node *new_node;
assert(ret_val != NULL);
if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
assert(get_method_n_ress(tp) == 1);
- pn_ret_val = get_Proj_proj(ret_val);
- pn_ret_mem = get_Proj_proj(ret_mem);
-
- /* get the Barrier */
- barrier = get_Proj_pred(ret_val);
-
- /* get result input of the Barrier */
- ret_val = get_irn_n(barrier, pn_ret_val);
- new_ret_val = be_transform_node(ret_val);
-
- /* get memory input of the Barrier */
- ret_mem = get_irn_n(barrier, pn_ret_mem);
- new_ret_mem = be_transform_node(ret_mem);
-
frame = get_irg_frame(irg);
- dbgi = get_irn_dbg_info(barrier);
- block = be_transform_node(get_nodes_block(barrier));
-
/* store xmm0 onto stack */
sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg_GP,
new_ret_mem, new_ret_val);
mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
- /* create a new barrier */
- arity = get_irn_arity(barrier);
+ /* create a new return */
+ arity = get_irn_arity(node);
in = ALLOCAN(ir_node*, arity);
+ pop = be_Return_get_pop(node);
for (i = 0; i < arity; ++i) {
- ir_node *new_in;
-
- if (i == pn_ret_val) {
- new_in = fld;
- } else if (i == pn_ret_mem) {
- new_in = mproj;
+ ir_node *op = get_irn_n(node, i);
+ if (op == ret_val) {
+ in[i] = fld;
+ } else if (op == ret_mem) {
+ in[i] = mproj;
} else {
- ir_node *in = get_irn_n(barrier, i);
- new_in = be_transform_node(in);
+ in[i] = be_transform_node(op);
}
- in[i] = new_in;
}
+ new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
+ copy_node_attr(irg, node, new_node);
- new_barrier = new_ir_node(dbgi, irg, block,
- get_irn_op(barrier), get_irn_mode(barrier),
- arity, in);
- copy_node_attr(irg, barrier, new_barrier);
- be_duplicate_deps(barrier, new_barrier);
- be_set_transformed_node(barrier, new_barrier);
-
- /* transform normally */
- return be_duplicate_node(node);
+ return new_node;
}
/**
*/
static ir_node *gen_be_AddSP(ir_node *node)
{
- ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
- ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
+ ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
+ ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
- return gen_binop(node, sp, sz, new_bd_ia32_SubSP,
- match_am | match_immediate);
+ ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP,
+ match_am | match_immediate);
+ assert(is_ia32_SubSP(new_node));
+ arch_irn_set_register(new_node, pn_ia32_SubSP_stack,
+ &ia32_registers[REG_ESP]);
+ return new_node;
}
/**
*/
static ir_node *gen_be_SubSP(ir_node *node)
{
- ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
- ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
+ ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
+ ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
- return gen_binop(node, sp, sz, new_bd_ia32_AddSP,
- match_am | match_immediate);
+ ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP,
+ match_am | match_immediate);
+ assert(is_ia32_AddSP(new_node));
+ arch_irn_set_register(new_node, pn_ia32_AddSP_stack,
+ &ia32_registers[REG_ESP]);
+ return new_node;
}
/**
return new_node;
}
-/**
- * Transform a Bound node.
- */
-static ir_node *gen_Bound(ir_node *node)
-{
- ir_node *new_node;
- ir_node *lower = get_Bound_lower(node);
- dbg_info *dbgi = get_irn_dbg_info(node);
-
- if (is_Const_0(lower)) {
- /* typical case for Java */
- ir_node *sub, *res, *flags, *block;
-
- res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
- new_bd_ia32_Sub,
- match_mode_neutral | match_am | match_immediate);
-
- block = get_nodes_block(res);
- if (! is_Proj(res)) {
- sub = res;
- set_irn_mode(sub, mode_T);
- res = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_res);
- } else {
- sub = get_Proj_pred(res);
- }
- flags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
- new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
- SET_IA32_ORIG_NODE(new_node, node);
- } else {
- panic("generic Bound not supported in ia32 Backend");
- }
- return new_node;
-}
-
-
static ir_node *gen_ia32_l_ShlDep(ir_node *node)
{
ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
am.pinned = op_pin_state_floats;
am.commutative = 1;
- am.ins_permuted = 0;
+ am.ins_permuted = false;
fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
am.new_op1, am.new_op2, get_fpcw());
SET_IA32_ORIG_NODE(new_node, node);
- be_dep_on_frame(new_node);
return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M);
}
ir_node *real = skip_Proj(bsf);
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
- ir_node *flag, *set, *conv, *neg, *orn;
+ ir_node *flag, *set, *conv, *neg, *orn, *add;
/* bsf x */
if (get_irn_mode(real) != mode_T) {
flag = new_r_Proj(real, mode_b, pn_ia32_flags);
/* sete */
- set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq);
+ set = new_bd_ia32_Setcc(dbgi, block, flag, ia32_cc_equal);
SET_IA32_ORIG_NODE(set, node);
/* conv to 32bit */
set_ia32_commutative(orn);
/* add 1 */
- return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, orn, ia32_create_Immediate(NULL, 0, 1));
+ add = new_bd_ia32_Lea(dbgi, block, orn, noreg_GP);
+ add_ia32_am_offs_int(add, 1);
+ return add;
}
/**
*/
static ir_node *gen_parity(ir_node *node)
{
- ir_node *param = get_Builtin_param(node, 0);
dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *param = get_Builtin_param(node, 0);
+ ir_node *new_param = be_transform_node(param);
+ ir_node *new_node;
- ir_node *block = get_nodes_block(node);
-
- ir_node *new_block = be_transform_node(block);
- ir_node *imm, *cmp, *new_node;
-
- ia32_address_mode_t am;
- ia32_address_t *addr = &am.addr;
-
-
- /* cmp param, 0 */
- match_arguments(&am, block, NULL, param, NULL, match_am);
- imm = ia32_create_Immediate(NULL, 0, 0);
- cmp = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, imm, am.new_op2, am.ins_permuted, 0);
- set_am_attributes(cmp, &am);
- set_ia32_ls_mode(cmp, mode_Iu);
-
- SET_IA32_ORIG_NODE(cmp, node);
+ /* the x86 parity bit is stupid: it only looks at the lowest byte,
+ * so we have to do complicated xoring first.
+ * (we should also better lower this before the backend so we still have a
+ * chance for CSE, constant folding and other goodies for some of these
+ * operations)
+ */
+ ir_node *count = ia32_create_Immediate(NULL, 0, 16);
+ ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
+ ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
+ shr, new_param);
+ ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor);
+ ir_node *flags;
- cmp = fix_mem_proj(cmp, &am);
+ set_irn_mode(xor2, mode_T);
+ flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
/* setp */
- new_node = new_bd_ia32_Setcc(dbgi, new_block, cmp, ia32_pn_Cmp_parity);
+ new_node = new_bd_ia32_Setcc(dbgi, new_block, flags, ia32_cc_not_parity);
SET_IA32_ORIG_NODE(new_node, node);
/* conv to 32bit */
new_param = be_transform_node(param);
/* do the standard popcount algo */
+ /* TODO: This is stupid, we should transform this before the backend,
+ * to get CSE, localopts, etc. for the operations
+ * TODO: This is also not the optimal algorithm (it is just the starting
+ * example in hackers delight, they optimize it more on the following page)
+ * But I'm too lazy to fix this now, as the code should get lowered before
+ * the backend anyway.
+ */
/* m1 = x & 0x55555555 */
imm = ia32_create_Immediate(NULL, 0, 0x55555555);
/* s1 = x >> 1 */
simm = ia32_create_Immediate(NULL, 0, 1);
- s1 = new_bd_ia32_Shl(dbgi, new_block, new_param, simm);
+ s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
/* m2 = s1 & 0x55555555 */
m2 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s1, imm);
/* s2 = m3 >> 2 */
simm = ia32_create_Immediate(NULL, 0, 2);
- s2 = new_bd_ia32_Shl(dbgi, new_block, m3, simm);
+ s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
/* m5 = s2 & 0x33333333 */
m5 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, imm);
/* s3 = m6 >> 4 */
simm = ia32_create_Immediate(NULL, 0, 4);
- s3 = new_bd_ia32_Shl(dbgi, new_block, m6, simm);
+ s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
/* m8 = s3 & 0x0F0F0F0F */
m8 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, imm);
/* s4 = m9 >> 8 */
simm = ia32_create_Immediate(NULL, 0, 8);
- s4 = new_bd_ia32_Shl(dbgi, new_block, m9, simm);
+ s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
/* m11 = s4 & 0x00FF00FF */
m11 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s4, imm);
/* s5 = m12 >> 16 */
simm = ia32_create_Immediate(NULL, 0, 16);
- s5 = new_bd_ia32_Shl(dbgi, new_block, m12, simm);
+ s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
/* res = m13 + s5 */
return new_bd_ia32_Lea(dbgi, new_block, m13, s5);
if (is_SymConst(callee)) {
rel = new_bd_ia32_Const(dbgi, new_block, get_SymConst_entity(callee), 0, 0, -10);
} else {
- rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), ia32_create_Immediate(NULL, 0, -10));
+ rel = new_bd_ia32_Lea(dbgi, new_block, be_transform_node(callee), noreg_GP);
+ add_ia32_am_offs_int(rel, -10);
}
rel = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP, nomem, rel, trampoline);
node);
}
-/**
- * Transform the Projs from a Bound.
- */
-static ir_node *gen_Proj_Bound(ir_node *node)
-{
- ir_node *new_node;
- ir_node *pred = get_Proj_pred(node);
-
- switch (get_Proj_proj(node)) {
- case pn_Bound_M:
- return be_transform_node(get_Bound_mem(pred));
- case pn_Bound_X_regular:
- new_node = be_transform_node(pred);
- return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_true);
- case pn_Bound_X_except:
- new_node = be_transform_node(pred);
- return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_false);
- case pn_Bound_res:
- return be_transform_node(get_Bound_index(pred));
- default:
- panic("unsupported Proj from Bound");
- }
-}
-
static ir_node *gen_Proj_ASM(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
return gen_Proj_be_Call(node);
case iro_Cmp:
return gen_Proj_Cmp(node);
- case iro_Bound:
- return gen_Proj_Bound(node);
case iro_Start:
proj = get_Proj_proj(node);
switch (proj) {
be_set_transform_function(op_be_IncSP, gen_be_IncSP);
be_set_transform_function(op_be_Return, gen_be_Return);
be_set_transform_function(op_be_SubSP, gen_be_SubSP);
- be_set_transform_function(op_Bound, gen_Bound);
be_set_transform_function(op_Builtin, gen_Builtin);
be_set_transform_function(op_Cmp, gen_Cmp);
be_set_transform_function(op_Cond, gen_Cond);
irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
+ assert(irg_data->fpu_trunc_mode == NULL);
+ assert(irg_data->get_eip == NULL);
nomem = get_irg_no_mem(irg);
noreg_GP = ia32_new_NoReg_gp(irg);
projects / libfirm / blobdiff