#include "ia32_map_regs.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
+#include "ia32_util.h"
#include "gen_ia32_regalloc_if.h"
* Returns 1 if irn is a Const representing 0, 0 otherwise
*/
static INLINE int is_ia32_Const_0(ir_node *irn) {
- return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
+ return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
+ classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
}
/**
* Returns 1 if irn is a Const representing 1, 0 otherwise
*/
static INLINE int is_ia32_Const_1(ir_node *irn) {
- return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
+ return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
+ classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
}
/**
* @return The constructed ia32 node.
*/
static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
- ir_node *new_op = NULL;
- ir_mode *mode = env->mode;
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
- ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
- ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
- ir_node *nomem = new_NoMem();
- ir_node *expr_op, *imm_op;
+ ir_node *new_op = NULL;
+ ir_mode *mode = env->mode;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
+ ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
+ ir_node *nomem = new_NoMem();
+ int is_mul = 0;
+ ir_node *expr_op, *imm_op;
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
+ /* Mul/MulS/Mulh don't support immediates */
+ if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
+ func == new_rd_ia32_Mul ||
+ func == new_rd_ia32_Mulh ||
+ func == new_rd_ia32_MulS)
+ {
expr_op = op1;
imm_op = NULL;
+ /* immediate operations are requested, but we are here: it a mul */
+ if (env->cg->opt & IA32_OPT_IMMOPS)
+ is_mul = 1;
}
else if (is_op_commutative(get_irn_op(env->irn))) {
imm_op = get_immediate_op(op1, op2);
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
}
+
+ /* Muls can only have AM source */
+ if (is_mul)
+ set_ia32_am_support(new_op, ia32_am_Source);
}
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
set_ia32_am_flavour(new_op, ia32_am_OB);
- DBG_OPT_LEA1(op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- DBG_OPT_LEA2(op1, op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
}
else {
/* integer SUB */
- if (!expr_op) {
+ if (! expr_op) {
/* No expr_op means, that we have two const - one symconst and */
/* one tarval or another symconst - because this case is not */
/* covered by constant folding */
/* We need to check for: */
- /* 1) symconst + const -> becomes a LEA */
- /* 2) symconst + symconst -> becomes a const + LEA as the elf */
+ /* 1) symconst - const -> becomes a LEA */
+ /* 2) symconst - symconst -> becomes a const - LEA as the elf */
/* linker doesn't support two symconsts */
if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
set_ia32_am_sc_sign(new_op);
set_ia32_am_flavour(new_op, ia32_am_OB);
- DBG_OPT_LEA1(op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- DBG_OPT_LEA2(op1, op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
ir_mode *mode = env->mode;
ir_node *irn = env->irn;
ir_node *mem;
+ int n;
switch (dm_flav) {
case flavour_Div:
/* Only one proj is used -> We must add a second proj and */
/* connect this one to a Keep node to eat up the second */
/* destroyed register. */
- if (get_irn_n_edges(irn) == 1) {
- proj = get_edge_src_irn(get_irn_out_edge_first(irn));
- assert(is_Proj(proj) && "non-Proj to Div/Mod node");
+ n = get_irn_n_edges(irn);
+ proj = NULL;
+ if (n == 2)
+ proj = ia32_get_proj_for_mode(irn, mode_M);
+
+ /* in case of two projs, one must be the memory proj */
+ if (n == 1 || (n == 2 && proj)) {
+ proj = ia32_get_res_proj(irn);
+ assert(proj && "Result proj expected");
if (get_irn_op(irn) == op_Div) {
set_Proj_proj(proj, pn_DivMod_res_div);
- in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
+ in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
}
else {
set_Proj_proj(proj, pn_DivMod_res_mod);
- in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
+ in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
}
be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
- set_ia32_res_mode(res, mode_Is);
+ set_ia32_res_mode(res, mode);
return res;
}
* @param op The Minus operand
* @return The created ia32 Minus node
*/
-static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
+ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
ident *name;
ir_node *new_op;
int size;
size = get_mode_size_bits(env->mode);
name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
- set_ia32_sc(new_op, name);
+ set_ia32_am_sc(new_op, name);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, env->mode);
- set_ia32_immop_type(new_op, ia32_ImmSymConst);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_ls_mode(new_op, env->mode);
new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
}
size = get_mode_size_bits(mode);
name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_sc(res, name);
+ set_ia32_am_sc(res, name);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
- set_ia32_immop_type(res, ia32_ImmSymConst);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ set_ia32_ls_mode(res, env->mode);
res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
}
* @return the created ia32 Load node
*/
static ir_node *gen_Load(ia32_transform_env_t *env) {
- ir_node *node = env->irn;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *ptr = get_Load_ptr(node);
- ir_node *lptr = ptr;
- ir_mode *mode = get_Load_mode(node);
- int is_imm = 0;
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *ptr = get_Load_ptr(node);
+ ir_node *lptr = ptr;
+ ir_mode *mode = get_Load_mode(node);
+ int is_imm = 0;
ir_node *new_op;
- ia32_am_flavour_t am_flav = ia32_B;
+ ia32_am_flavour_t am_flav = ia32_am_B;
/* address might be a constant (symconst or absolute address) */
if (is_ia32_Const(ptr)) {
/* base is an constant address */
if (is_imm) {
- if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
+ if (get_ia32_op_type(ptr) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
+ am_flav = ia32_am_N;
}
else {
add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
+ am_flav = ia32_am_O;
}
-
- am_flav = ia32_O;
}
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_am_flavour(new_op, am_flav);
set_ia32_ls_mode(new_op, mode);
+ /*
+ check for special case: the loaded value might not be used (optimized, volatile, ...)
+ we add a Proj + Keep for volatile loads and ignore all other cases
+ */
+ if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
+ /* add a result proj and a Keep to produce a pseudo use */
+ ir_node *proj = new_r_Proj(env->irg, env->block, new_op, mode, pn_ia32_Load_res);
+ be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), env->irg, env->block, 1, &proj);
+ }
+
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
ir_node *ptr = get_Store_ptr(node);
ir_node *sptr = ptr;
ir_node *mem = get_Store_mem(node);
- ir_mode *mode = get_irn_mode(val);
+ ir_mode *mode = get_irn_link(node);
ir_node *sval = val;
int is_imm = 0;
ir_node *new_op;
- ia32_am_flavour_t am_flav = ia32_B;
+ ia32_am_flavour_t am_flav = ia32_am_B;
ia32_immop_type_t immop = ia32_ImmNone;
if (! mode_is_float(mode)) {
if (is_imm) {
if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
+ am_flav = ia32_am_N;
}
else {
add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
+ am_flav = ia32_am_O;
}
-
- am_flav = ia32_O;
}
set_ia32_am_support(new_op, ia32_am_Dest);
set_ia32_op_type(new_op, ia32_AddrModeD);
set_ia32_am_flavour(new_op, am_flav);
- set_ia32_ls_mode(new_op, get_irn_mode(val));
+ set_ia32_ls_mode(new_op, mode);
set_ia32_immop_type(new_op, immop);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
pn_Cmp pnc = get_Proj_proj(sel);
if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
- if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
+ if (get_ia32_op_type(cnst) == ia32_Const &&
+ classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
+ {
/* a Cmp A =/!= 0 */
ir_node *op1 = expr;
ir_node *op2 = expr;
* @return The transformed node.
*/
static ir_node *gen_CopyB(ia32_transform_env_t *env) {
- ir_node *res = NULL;
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_mode *mode = env->mode;
- ir_node *block = env->block;
- ir_node *node = env->irn;
- ir_node *src = get_CopyB_src(node);
- ir_node *dst = get_CopyB_dst(node);
- ir_node *mem = get_CopyB_mem(node);
- int size = get_type_size_bytes(get_CopyB_type(node));
- int rem;
+ ir_node *res = NULL;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *node = env->irn;
+ ir_node *src = get_CopyB_src(node);
+ ir_node *dst = get_CopyB_dst(node);
+ ir_node *mem = get_CopyB_mem(node);
+ int size = get_type_size_bytes(get_CopyB_type(node));
+ ir_mode *dst_mode = get_irn_mode(dst);
+ ir_mode *src_mode = get_irn_mode(src);
+ int rem;
+ ir_node *in[3], *tmp;
/* If we have to copy more than 16 bytes, we use REP MOVSx and */
/* then we need the size explicitly in ECX. */
set_ia32_op_type(res, ia32_Const);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
- res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
+ res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
+
+ /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
+ in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
+ in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
+ in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
+
+ tmp = ia32_get_proj_for_mode(node, mode_M);
+ set_Proj_proj(tmp, pn_ia32_CopyB_M);
}
else {
- res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
+ res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
set_ia32_immop_type(res, ia32_ImmConst);
+
+ /* ok: now attach Proj's because movsd will destroy esi and edi */
+ in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
+ in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
+
+ tmp = ia32_get_proj_for_mode(node, mode_M);
+ set_Proj_proj(tmp, pn_ia32_CopyB_i_M);
}
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
- set_ia32_am_support(and1, ia32_am_Source);
+ set_ia32_am_support(and1, ia32_am_None);
set_ia32_res_mode(and1, mode);
SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
- set_ia32_am_support(and2, ia32_am_Source);
+ set_ia32_am_support(and2, ia32_am_None);
set_ia32_res_mode(and2, mode);
SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
- set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_am_support(new_op, ia32_am_None);
set_ia32_res_mode(new_op, mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
/* second case for SETcc: default is 1, set to 0 iff condition is true: */
/* we invert condition and set default to 0 */
new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
- set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
+ set_ia32_pncode(new_op, get_inversed_pnc(pnc));
}
else {
/* otherwise: use CMOVcc */
/* second case for SETcc: default is 1, set to 0 iff condition is true: */
/* we invert condition and set default to 0 */
new_op = gen_binop(env, cmp_a, cmp_b, set_func);
- set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
+ set_ia32_pncode(get_Proj_pred(new_op), get_inversed_pnc(pnc));
set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
}
else {
set_ia32_am_support(fist, ia32_am_Dest);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_am_flavour(fist, ia32_B);
- set_ia32_ls_mode(fist, mode_E);
+ set_ia32_ls_mode(fist, mode_F);
mem = new_r_Proj(irg, block, fist, mode_M, pn_ia32_vfist_M);
set_ia32_am_support(fild, ia32_am_Source);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_am_flavour(fild, ia32_B);
- set_ia32_ls_mode(fild, mode_E);
+ set_ia32_ls_mode(fild, mode_F);
- return new_r_Proj(irg, block, fild, mode_E, 0);
+ return new_r_Proj(irg, block, fild, mode_F, 0);
}
/**
return new_op;
}
+/**
+ * In case SSE is used we need to copy the result from FPU TOS.
+ */
+static ir_node *gen_be_Call(ia32_transform_env_t *env) {
+ ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
+ ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
+ ir_mode *mode;
+
+ if (! call_res || ! USE_SSE2(env->cg))
+ return NULL;
+
+ mode = get_irn_mode(call_res);
+
+ if (mode_is_float(mode)) {
+ /* store st(0) onto stack */
+ ir_node *frame = get_irg_frame(env->irg);
+ ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
+ ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
+ entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
+ ir_node *sse_load;
+
+ set_ia32_ls_mode(fstp, mode);
+ set_ia32_op_type(fstp, ia32_AddrModeD);
+ set_ia32_use_frame(fstp);
+ set_ia32_frame_ent(fstp, ent);
+ set_ia32_am_flavour(fstp, ia32_B);
+ set_ia32_am_support(fstp, ia32_am_Dest);
+
+ /* load into SSE register */
+ sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
+ set_ia32_ls_mode(sse_load, mode);
+ set_ia32_op_type(sse_load, ia32_AddrModeS);
+ set_ia32_use_frame(sse_load);
+ set_ia32_frame_ent(sse_load, ent);
+ set_ia32_am_flavour(sse_load, ia32_B);
+ set_ia32_am_support(sse_load, ia32_am_Source);
+ sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
+
+ /* reroute all users of the result proj to the sse load */
+ edges_reroute(call_res, sse_load, env->irg);
+ }
+
+ return NULL;
+}
+
/**
* This function just sets the register for the Unknown node
* as this is not done during register allocation because Unknown
/* These nodes are created in intrinsic lowering (64bit -> 32bit) */
+typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
+ ir_node *mem);
+
+typedef ir_node *construct_store_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
+ ir_node *val, ir_node *mem);
+
+/**
+ * Transforms a lowered Load into a "real" one.
+ */
+static ir_node *gen_lowered_Load(ia32_transform_env_t *env, construct_load_func func, char fp_unit) {
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *new_op;
+ char *am_offs;
+ ia32_am_flavour_t am_flav = ia32_B;
+
+ /*
+ Could be that we have SSE2 unit, but due to 64Bit Div/Conv
+ lowering we have x87 nodes, so we need to enforce simulation.
+ */
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (fp_unit == fp_x87)
+ FORCE_x87(env->cg);
+ }
+
+ new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+ am_offs = get_ia32_am_offs(node);
+
+ if (am_offs) {
+ am_flav |= ia32_O;
+ add_ia32_am_offs(new_op, am_offs);
+ }
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, am_flav);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+/**
+* Transforms a lowered Store into a "real" one.
+*/
+static ir_node *gen_lowered_Store(ia32_transform_env_t *env, construct_store_func func, char fp_unit) {
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_mode *mode = get_ia32_ls_mode(node);
+ ir_node *new_op;
+ char *am_offs;
+ ia32_am_flavour_t am_flav = ia32_B;
+
+ /*
+ Could be that we have SSE2 unit, but due to 64Bit Div/Conv
+ lowering we have x87 nodes, so we need to enforce simulation.
+ */
+ if (mode_is_float(mode)) {
+ FP_USED(env->cg);
+ if (fp_unit == fp_x87)
+ FORCE_x87(env->cg);
+ }
+
+ new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
+
+ if ((am_offs = get_ia32_am_offs(node)) != NULL) {
+ am_flav |= ia32_O;
+ add_ia32_am_offs(new_op, am_offs);
+ }
+
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, am_flav);
+ set_ia32_ls_mode(new_op, mode);
+ set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
+ set_ia32_use_frame(new_op);
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+
+ return new_op;
+}
+
+
/**
* Transforms an ia32_l_XXX into a "real" XXX node
*
* @param env The transformation environment
* @return the created ia32 XXX node
*/
-#define GEN_LOWERED_OP(op) \
+#define GEN_LOWERED_OP(op) \
static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
+ if (mode_is_float(env->mode)) \
+ FP_USED(env->cg); \
return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
- } \
+ }
-#define GEN_LOWERED_SHIFT_OP(op) \
+#define GEN_LOWERED_x87_OP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
+ ir_node *new_op; \
+ FORCE_x87(env->cg); \
+ new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
+ set_ia32_am_support(get_Proj_pred(new_op), ia32_am_None); \
+ return new_op; \
+ }
+
+#define GEN_LOWERED_UNOP(op) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
+ return gen_unop(env, get_unop_op(env->irn), new_rd_ia32_##op); \
+ }
+
+#define GEN_LOWERED_SHIFT_OP(op) \
static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
return gen_shift_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_##op); \
- } \
+ }
+
+#define GEN_LOWERED_LOAD(op, fp_unit) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
+ return gen_lowered_Load(env, new_rd_ia32_##op, fp_unit); \
+ }
+
+#define GEN_LOWERED_STORE(op, fp_unit) \
+ static ir_node *gen_ia32_l_##op(ia32_transform_env_t *env) { \
+ return gen_lowered_Store(env, new_rd_ia32_##op, fp_unit); \
+}
GEN_LOWERED_OP(AddC)
GEN_LOWERED_OP(Add)
GEN_LOWERED_OP(SubC)
GEN_LOWERED_OP(Sub)
GEN_LOWERED_OP(Mul)
+GEN_LOWERED_OP(Eor)
+GEN_LOWERED_x87_OP(vfdiv)
+GEN_LOWERED_x87_OP(vfmul)
+GEN_LOWERED_x87_OP(vfsub)
+
+GEN_LOWERED_UNOP(Minus)
+
+GEN_LOWERED_LOAD(vfild, fp_x87)
+GEN_LOWERED_LOAD(Load, fp_none)
+GEN_LOWERED_STORE(vfist, fp_x87)
+GEN_LOWERED_STORE(Store, fp_none)
/**
* Transforms a l_MulS into a "real" MulS node.
/* and then skip the result Proj, because all needed Projs are already there. */
ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
- return get_Proj_pred(new_op);
+ ir_node *muls = get_Proj_pred(new_op);
+
+ /* MulS cannot have AM for destination */
+ if (get_ia32_am_support(muls) != ia32_am_None)
+ set_ia32_am_support(muls, ia32_am_Source);
+
+ return muls;
}
GEN_LOWERED_SHIFT_OP(Shl)
return gen_lowered_64bit_shifts(env, get_irn_n(env->irn, 0), get_irn_n(env->irn, 1), get_irn_n(env->irn, 2));
}
-
-
-/*********************************************************
- * _ _ _
- * (_) | | (_)
- * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
- * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
- * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
- * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
- *
- *********************************************************/
-
/**
- * Transforms a Sub or xSub into Neg--Add iff OUT_REG == SRC2_REG.
- * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
+ * In case SSE Unit is used, the node is transformed into a vfst + xLoad.
*/
-void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
- ia32_transform_env_t tenv;
- ir_node *in1, *in2, *noreg, *nomem, *res;
- const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
-
- /* Return if AM node or not a Sub or xSub */
- if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_xSub(irn)))
- return;
-
- noreg = ia32_new_NoReg_gp(cg);
- nomem = new_rd_NoMem(cg->irg);
- in1 = get_irn_n(irn, 2);
- in2 = get_irn_n(irn, 3);
- in1_reg = arch_get_irn_register(cg->arch_env, in1);
- in2_reg = arch_get_irn_register(cg->arch_env, in2);
- out_reg = get_ia32_out_reg(irn, 0);
-
- tenv.block = get_nodes_block(irn);
- tenv.dbg = get_irn_dbg_info(irn);
- tenv.irg = cg->irg;
- tenv.irn = irn;
- tenv.mode = get_ia32_res_mode(irn);
- tenv.cg = cg;
- DEBUG_ONLY(tenv.mod = cg->mod;)
-
- /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
- if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
- /* generate the neg src2 */
- res = gen_Minus_ex(&tenv, in2);
- arch_set_irn_register(cg->arch_env, res, in2_reg);
-
- /* add to schedule */
- sched_add_before(irn, res);
-
- /* generate the add */
- if (mode_is_float(tenv.mode)) {
- res = new_rd_ia32_xAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
- set_ia32_am_support(res, ia32_am_Source);
- }
- else {
- res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem);
- set_ia32_am_support(res, ia32_am_Full);
- set_ia32_commutative(res);
- }
- set_ia32_res_mode(res, tenv.mode);
-
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
- /* copy register */
- slots = get_ia32_slots(res);
- slots[0] = in2_reg;
-
- /* add to schedule */
- sched_add_before(irn, res);
-
- /* remove the old sub */
- sched_remove(irn);
-
- DBG_OPT_SUB2NEGADD(irn, res);
+static ir_node *gen_ia32_l_X87toSSE(ia32_transform_env_t *env) {
+ ia32_code_gen_t *cg = env->cg;
+ ir_node *res = NULL;
+ ir_node *ptr = get_irn_n(env->irn, 0);
+ ir_node *val = get_irn_n(env->irn, 1);
+ ir_node *mem = get_irn_n(env->irn, 2);
+
+ if (USE_SSE2(cg)) {
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+
+ /* Store x87 -> MEM */
+ res = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
+ set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
+ set_ia32_am_support(res, ia32_am_Dest);
+ set_ia32_am_flavour(res, ia32_B);
+ res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_vfst_M);
+
+ /* Load MEM -> SSE */
+ res = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, ptr, noreg, res);
+ set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
+ set_ia32_am_support(res, ia32_am_Source);
+ set_ia32_am_flavour(res, ia32_B);
+ res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_xLoad_res);
+ }
+ else {
+ /* SSE unit is not used -> skip this node. */
+ int i;
- /* exchange the add and the sub */
- exchange(irn, res);
+ edges_reroute(env->irn, val, env->irg);
+ for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
+ set_irn_n(env->irn, i, get_irg_bad(env->irg));
}
+
+ return res;
}
/**
- * Transforms a LEA into an Add if possible
- * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
+ * In case SSE Unit is used, the node is transformed into a xStore + vfld.
*/
-void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
- ia32_am_flavour_t am_flav;
- int imm = 0;
- ir_node *res = NULL;
- ir_node *nomem, *noreg, *base, *index, *op1, *op2;
- char *offs;
- ia32_transform_env_t tenv;
- const arch_register_t *out_reg, *base_reg, *index_reg;
-
- /* must be a LEA */
- if (! is_ia32_Lea(irn))
- return;
-
- am_flav = get_ia32_am_flavour(irn);
-
- /* only some LEAs can be transformed to an Add */
- if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
- return;
-
- noreg = ia32_new_NoReg_gp(cg);
- nomem = new_rd_NoMem(cg->irg);
- op1 = noreg;
- op2 = noreg;
- base = get_irn_n(irn, 0);
- index = get_irn_n(irn,1);
-
- offs = get_ia32_am_offs(irn);
-
- /* offset has a explicit sign -> we need to skip + */
- if (offs && offs[0] == '+')
- offs++;
-
- out_reg = arch_get_irn_register(cg->arch_env, irn);
- base_reg = arch_get_irn_register(cg->arch_env, base);
- index_reg = arch_get_irn_register(cg->arch_env, index);
-
- tenv.block = get_nodes_block(irn);
- tenv.dbg = get_irn_dbg_info(irn);
- tenv.irg = cg->irg;
- tenv.irn = irn;
- DEBUG_ONLY(tenv.mod = cg->mod;)
- tenv.mode = get_irn_mode(irn);
- tenv.cg = cg;
-
- switch(get_ia32_am_flavour(irn)) {
- case ia32_am_B:
- /* out register must be same as base register */
- if (! REGS_ARE_EQUAL(out_reg, base_reg))
- return;
-
- op1 = base;
- break;
- case ia32_am_OB:
- /* out register must be same as base register */
- if (! REGS_ARE_EQUAL(out_reg, base_reg))
- return;
-
- op1 = base;
- imm = 1;
- break;
- case ia32_am_OI:
- /* out register must be same as index register */
- if (! REGS_ARE_EQUAL(out_reg, index_reg))
- return;
-
- op1 = index;
- imm = 1;
- break;
- case ia32_am_BI:
- /* out register must be same as one in register */
- if (REGS_ARE_EQUAL(out_reg, base_reg)) {
- op1 = base;
- op2 = index;
- }
- else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
- op1 = index;
- op2 = base;
- }
- else {
- /* in registers a different from out -> no Add possible */
- return;
- }
- default:
- break;
+static ir_node *gen_ia32_l_SSEtoX87(ia32_transform_env_t *env) {
+ ia32_code_gen_t *cg = env->cg;
+ ir_node *res = NULL;
+ ir_node *ptr = get_irn_n(env->irn, 0);
+ ir_node *val = get_irn_n(env->irn, 1);
+ ir_node *mem = get_irn_n(env->irn, 2);
+
+ if (USE_SSE2(cg)) {
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+
+ /* Store SSE -> MEM */
+ res = new_rd_ia32_xStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem);
+ set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
+ set_ia32_am_support(res, ia32_am_Dest);
+ set_ia32_am_flavour(res, ia32_B);
+ res = new_rd_Proj(env->dbg, env->irg, env->block, res, mode_M, pn_ia32_xStore_M);
+
+ /* Load MEM -> x87 */
+ res = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem);
+ set_ia32_frame_ent(res, get_ia32_frame_ent(env->irn));
+ set_ia32_use_frame(res);
+ set_ia32_ls_mode(res, get_ia32_ls_mode(env->irn));
+ set_ia32_am_support(res, ia32_am_Source);
+ set_ia32_am_flavour(res, ia32_B);
+ res = new_rd_Proj(env->dbg, env->irg, env->block, res, get_ia32_ls_mode(env->irn), pn_ia32_vfld_res);
}
+ else {
+ /* SSE unit is not used -> skip this node. */
+ int i;
- res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem);
- arch_set_irn_register(cg->arch_env, res, out_reg);
- set_ia32_op_type(res, ia32_Normal);
- set_ia32_commutative(res);
- set_ia32_res_mode(res, tenv.mode);
-
- if (imm) {
- set_ia32_cnst(res, offs);
- set_ia32_immop_type(res, ia32_ImmConst);
+ edges_reroute(env->irn, val, env->irg);
+ for (i = get_irn_arity(env->irn) - 1; i >= 0; i--)
+ set_irn_n(env->irn, i, get_irg_bad(env->irg));
}
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
-
- /* add Add to schedule */
- sched_add_before(irn, res);
-
- DBG_OPT_LEA2ADD(irn, res);
-
- res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
-
- /* add result Proj to schedule */
- sched_add_before(irn, res);
-
- /* remove the old LEA */
- sched_remove(irn);
-
- /* exchange the Add and the LEA */
- exchange(irn, res);
+ return res;
}
+/*********************************************************
+ * _ _ _
+ * (_) | | (_)
+ * _ __ ___ __ _ _ _ __ __| |_ __ ___ _____ _ __
+ * | '_ ` _ \ / _` | | '_ \ / _` | '__| \ \ / / _ \ '__|
+ * | | | | | | (_| | | | | | | (_| | | | |\ V / __/ |
+ * |_| |_| |_|\__,_|_|_| |_| \__,_|_| |_| \_/ \___|_|
+ *
+ *********************************************************/
+
/**
* the BAD transformer.
*/
GEN(Mux);
GEN(Psi);
+ /* transform ops from intrinsic lowering */
GEN(ia32_l_Add);
GEN(ia32_l_AddC);
GEN(ia32_l_Sub);
GEN(ia32_l_SubC);
+ GEN(ia32_l_Minus);
GEN(ia32_l_Mul);
+ GEN(ia32_l_Eor);
GEN(ia32_l_MulS);
GEN(ia32_l_Shl);
GEN(ia32_l_Shr);
GEN(ia32_l_Shrs);
GEN(ia32_l_ShlD);
GEN(ia32_l_ShrD);
+ GEN(ia32_l_vfdiv);
+ GEN(ia32_l_vfmul);
+ GEN(ia32_l_vfsub);
+ GEN(ia32_l_vfild);
+ GEN(ia32_l_Load);
+ GEN(ia32_l_vfist);
+ GEN(ia32_l_Store);
+ GEN(ia32_l_X87toSSE);
+ GEN(ia32_l_SSEtoX87);
IGN(Call);
IGN(Alloc);
IGN(SymConst);
IGN(Sync);
+ /* we should never see these nodes */
BAD(Raise);
BAD(Sel);
BAD(InstOf);
BAD(EndReg);
BAD(EndExcept);
+ /* handle generic backend nodes */
GEN(be_FrameAddr);
+ GEN(be_Call);
GEN(be_FrameLoad);
GEN(be_FrameStore);
GEN(be_StackParam);
static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
int i;
+ /* if the mode is target mode, we have already seen this part of the tree */
+ if (get_irn_mode(cond) == mode)
+ return;
+
assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
+
set_irn_mode(cond, mode);
for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
}
- /* exchange with old compare */
- exchange(in, new_op);
+ /* the the new compare as in */
+ set_irn_n(cond, i, new_op);
}
else {
/* another complex condition */
* "And"s and "Or"s are transformed later, we just have to set their mode right.
*/
void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
- ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
+ ia32_code_gen_t *cg = env;
ir_node *psi_sel, *new_cmp, *block;
ir_graph *irg;
ir_mode *mode;
/* BEWARE: new_r_Const_long works for floating point as well */
new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
- /* transform the const */
- ia32_place_consts_set_modes(new_cmp, cg);
new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
set_Psi_cond(node, 0, new_cmp);