if (get_irn_op(irn) == op_Div) {
set_Proj_proj(proj, pn_DivMod_res_div);
- in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
+ in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_mod);
}
else {
set_Proj_proj(proj, pn_DivMod_res_mod);
- in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
+ in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode, pn_DivMod_res_div);
}
be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
- set_ia32_res_mode(res, mode_Is);
+ set_ia32_res_mode(res, mode);
return res;
}
FORCE_x87(env->cg);
}
- new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+ new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1));
+ am_offs = get_ia32_am_offs(node);
- if (am_offs = get_ia32_am_offs(node)) {
+ if (am_offs) {
am_flav |= ia32_O;
add_ia32_am_offs(new_op, am_offs);
}
/* and then skip the result Proj, because all needed Projs are already there. */
ir_node *new_op = gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_MulS);
- return get_Proj_pred(new_op);
+ ir_node *muls = get_Proj_pred(new_op);
+
+ /* MulS cannot have AM for destination */
+ if (get_ia32_am_support(muls) != ia32_am_None)
+ set_ia32_am_support(muls, ia32_am_Source);
+
+ return muls;
}
GEN_LOWERED_SHIFT_OP(Shl)