extern ir_op *get_op_Mulh(void);
-/* this is a struct to minimize the number of parameters
- passed to each gen_xxx function */
-typedef struct _transform_env_t {
- const arch_env_t *arch_env; /**<< The arch_env */
- firm_dbg_module_t *mod; /**<< The firm debugger */
- dbg_info *dbg; /**<< The node debug info */
- ir_graph *irg; /**<< The irg, the node should be created in */
- ir_node *block; /**<< The block, the node should belong to */
- ir_node *irn; /**<< The irn, to be transformed */
- ir_mode *mode; /**<< The mode of the irn */
- ia32_code_gen_t *cg; /**<< The code generator */
-} transform_env_t;
/****************************************************************************************************
* @param mode node mode
* @return the created ia23 Add_i node
*/
-static ir_node *gen_imm_Add(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
ir_node *new_op;
tarval *tv = get_ia32_Immop_tarval(const_op);
int normal_add = 0;
class_negtv = classify_tarval(tarval_neg(tv));
if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
- DBG((env->mod, LEVEL_2, "optimizing Add(1) to Inc ... "));
+ DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode);
}
else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
- DBG((mod, LEVEL_2, "optimizing Add(-1) to Dec ... "));
+ DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode);
}
else
* @param mode node mode
* @return the created ia32 Add node
*/
-static ir_node *gen_Add(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
ir_node *shli_op;
ir_node *expr_op;
ir_node *new_op;
int normal_add = 0;
- firm_dbg_module_t *mod = env->mod;
- dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
+ dbg_info *dbg = env->dbg;
+ ir_mode *mode = env->mode;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
if (mode_is_float(mode)) {
return new_rd_ia32_fAdd(dbg, irg, block, op1, op2, mode);
* @param mul_flav flavour_Mul/Mulh
* @return The ready-to-go Mul node
*/
-ir_node *generate_Mul(transform_env_t *env, ir_node *op1, ir_node *op2, op_flavour_t mul_flav, int is_imm_op) {
+ir_node *generate_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, op_flavour_t mul_flav, int is_imm_op) {
ir_node *in_keep[1], *res;
long pn_good, pn_bad;
dbg_info *dbg = env->dbg;
* @param mode node mode
* @return the created ia23 Mul_i node
*/
-static ir_node *gen_imm_Mul(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Mul(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
/* Mul with immediate only possible with int, so we don't need to check for float */
return generate_Mul(env, expr_op, const_op, flavour_Mul, 1);
}
* @param mode node mode
* @return the created ia32 Mul node
*/
-ir_node *gen_Mul(transform_env_t *env, ir_node *op1, ir_node *op2) {
+ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
if (mode_is_float(env->mode)) {
return new_rd_ia32_fMul(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Mulh_i node
*/
-static ir_node *gen_imm_Mulh(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Mulh(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return generate_Mul(env, expr_op, const_op, flavour_Mulh, 1);
}
* @param mode node mode
* @return the created ia32 Mulh node
*/
-static ir_node *gen_Mulh(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return generate_Mul(env, op1, op2, flavour_Mulh, 0);
}
* @param mode node mode
* @return the created ia23 And_i node
*/
-static ir_node *gen_imm_And(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_And(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_And_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 And node
*/
-static ir_node *gen_And(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_And(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Or_i node
*/
-static ir_node *gen_imm_Or(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Or(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_Or_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 Or node
*/
-static ir_node *gen_Or(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Or(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Eor_i node
*/
-static ir_node *gen_imm_Eor(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Eor(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_Eor_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 Eor node
*/
-static ir_node *gen_Eor(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Eor(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Max node
*/
-static ir_node *gen_Max(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Min node
*/
-static ir_node *gen_Min(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Sub_i node
*/
-static ir_node *gen_imm_Sub(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
ir_node *new_op;
tarval *tv = get_ia32_Immop_tarval(const_op);
int normal_sub = 0;
class_negtv = classify_tarval(tarval_neg(tv));
if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
- DBG((mod, LEVEL_2, "optimizing Sub(1) to Dec ... "));
+ DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode);
}
else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
- DBG((mod, LEVEL_2, "optimizing Sub(-1) to Inc ... "));
+ DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode);
}
else
* @param mode node mode
* @return the created ia32 Sub node
*/
-static ir_node *gen_Sub(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
if (mode_is_float(env->mode)) {
return new_rd_ia32_fSub(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param dm_flav flavour_Div/Mod/DivMod
* @return The created ia32 DivMod node
*/
-static ir_node *generate_DivMod(transform_env_t *env, ir_node *dividend, ir_node *divisor, op_flavour_t dm_flav) {
+static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir_node *divisor, op_flavour_t dm_flav) {
ir_node *res, *proj;
ir_node *edx_node, *cltd;
ir_node *in_keep[1];
/**
* Wrapper for generate_DivMod. Sets flavour_Mod.
*/
-static ir_node *gen_Mod(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return generate_DivMod(env, op1, op2, flavour_Mod);
}
/**
* Wrapper for generate_DivMod. Sets flavour_Div.
*/
-static ir_node *gen_Div(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return generate_DivMod(env, op1, op2, flavour_Div);
}
/**
* Wrapper for generate_DivMod. Sets flavour_DivMod.
*/
-static ir_node *gen_DivMod(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return generate_DivMod(env, op1, op2, flavour_DivMod);
}
* @param mode node mode
* @return the created ia32 fDiv node
*/
-static ir_node *gen_Quot(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_fDiv(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Shl_i node
*/
-static ir_node *gen_imm_Shl(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Shl(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_Shl_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 Shl node
*/
-static ir_node *gen_Shl(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Shl(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Shr_i node
*/
-static ir_node *gen_imm_Shr(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Shr(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_Shr_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 Shr node
*/
-static ir_node *gen_Shr(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Shr(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia23 Shrs_i node
*/
-static ir_node *gen_imm_Shrs(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Shrs(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_Shrs_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 Shrs node
*/
-static ir_node *gen_Shrs(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_Shrs(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia32 RotL node
*/
-static ir_node *gen_RotL(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_RotL(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia32 RotR node
*/
-static ir_node *gen_RotR(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
return new_rd_ia32_RotR(env->dbg, env->irg, env->block, op1, op2, env->mode);
}
* @param mode node mode
* @return the created ia32 RotL node
*/
-static ir_node *gen_imm_Rot(transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
+static ir_node *gen_imm_Rot(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
return new_rd_ia32_RotL_i(env->dbg, env->irg, env->block, expr_op, env->mode);
}
* @param mode node mode
* @return the created ia32 RotL or RotR node
*/
-static ir_node *gen_Rot(transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
ir_node *rotate = NULL;
/* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
long bits = get_mode_size_bits(env->mode);
if (tarval_is_long(tv) && get_tarval_long(tv) == bits) {
- DBG((env->mod, LEVEL_1, "optimizing RotL into RotR ... "));
+ DB((env->mod, LEVEL_1, "RotL into RotR ... "));
rotate = gen_RotR(env, op1, get_irn_n(minus, 0));
}
}
* @param com flag if op is commutative
* @return the created assembler node
*/
-static ir_node *gen_arith_Op(transform_env_t *env, ir_node *op1, ir_node *op2, int com) {
+static ir_node *gen_arith_Op(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, int com) {
firm_dbg_module_t *mod = env->mod;
- dbg_info *dbg = env->dbg;
ir_node *node = env->irn;
ir_node *imm_op = NULL;
ir_node *expr_op = NULL;
/* TODO: Op(Const, Const) support */
if (is_ia32_Const(op1) && is_ia32_Const(op2)) {
- DBG((mod, LEVEL_2, "found unexpected %s(Const, Const), creating binop ... ", get_irn_opname(node)));
+ DB((mod, LEVEL_2, "%+F(Const, Const) -> binop ... ", get_irn_opname(node)));
imm_op = NULL;
}
case iro_Div:
case iro_Mod:
case iro_DivMod:
- DBG((mod, LEVEL_2, "Div/Mod/DivMod imm not available, creating binop ... "));
+ DB((mod, LEVEL_2, "Div/Mod/DivMod imm -> binop ... "));
imm_op = NULL;
break;
default:
if (op == get_op_Min() || op == get_op_Max()) {
- DBG((mod, LEVEL_2, "MIN/MAX imm not available, creating binop ... "));
+ DB((mod, LEVEL_2, "MIN/MAX imm -> binop ... "));
imm_op = NULL;
}
break;
}
- DBG((mod, LEVEL_1, "(op1: %s -- op2: %s) ... ", get_irn_opname(op1), get_irn_opname(op2)));
+ DB((mod, LEVEL_1, "(%+F -- %+F) ... ", op1, op2));
if (!mode_is_float(env->mode) && imm_op) {
- DBG((mod, LEVEL_1, "%s with imm ... ", get_irn_opname(node)));
+ DB((mod, LEVEL_1, "immop ... "));
switch(opc) {
GENOPI_SETATTR(Add);
}
}
else {
- DBG((mod, LEVEL_1, "%s as binop ... ", get_irn_opname(node)));
+ DB((mod, LEVEL_1, "binop ... "));
switch(opc) {
GENOP(Add);
* @param mode node mode
* @return the created ia32 Minus node
*/
-static ir_node *gen_Minus(transform_env_t *env, ir_node *op) {
+static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
if (is_ia32_Minus(op) || is_ia32_fMinus(op)) {
- DBG((env->mod, LEVEL_1, "optimizing --(e) to e ..."));
+ DB((env->mod, LEVEL_1, "--(e) to e ..."));
return get_irn_n(op, 0);
}
else {
* @param mode node mode
* @return the created ia32 Conv node
*/
-static ir_node *gen_Conv(transform_env_t *env, ir_node *op) {
+static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
return new_rd_ia32_Conv(env->dbg, env->irg, env->block, op, env->mode);
}
* @param mode node mode
* @return the created ia32 Not node
*/
-static ir_node *gen_Not(transform_env_t *env, ir_node *op) {
+static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
return new_rd_ia32_Not(env->dbg, env->irg, env->block, op, env->mode);
}
* @param mode node mode
* @return the created ia32 Abs node
*/
-static ir_node *gen_Abs(transform_env_t *env, ir_node *op) {
- ir_node *res, *p_eax, *p_edx;
- firm_dbg_module_t *mod = env->mod;
- dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
+static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
+ ir_node *res, *p_eax, *p_edx;
+ dbg_info *dbg = env->dbg;
+ ir_mode *mode = env->mode;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
res = new_rd_ia32_Cltd(dbg, irg, block, op, mode_T);
p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
* @param mode node mode
* @return the created ia32 Load node
*/
-static ir_node *gen_Load(transform_env_t *env) {
+static ir_node *gen_Load(ia32_transform_env_t *env) {
ir_node *node = env->irn;
if (mode_is_float(env->mode)) {
* @param mode node mode
* @return the created ia32 Store node
*/
-ir_node *gen_Store(transform_env_t *env) {
+ir_node *gen_Store(ia32_transform_env_t *env) {
ir_node *node = env->irn;
if (mode_is_float(env->mode)) {
* @param dummy mode doesn't matter
* @return the created ia32 Call node
*/
-static ir_node *gen_Call(transform_env_t *env) {
+static ir_node *gen_Call(ia32_transform_env_t *env) {
const ia32_register_req_t **in_req;
ir_node **in;
ir_node *new_call, *sync;
int i, j, n_new_call_in, ignore = 0;
asmop_attr *attr;
- firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
/* do we need to pass arguments on stack? */
if (biggest_n + 1 < n)
- stack_param = calloc(n - biggest_n - 1, sizeof(ir_node *));
+ stack_param = xcalloc(n - biggest_n - 1, sizeof(ir_node *));
/* we need at least one in, either for the stack params or the call_Mem */
n_new_call_in = biggest_n + 2;
/* the call has one IN for all stack parameter and one IN for each reg param */
- in = calloc(n_new_call_in, sizeof(ir_node *));
- in_req = calloc(n_new_call_in, sizeof(arch_register_req_t *));
+ in = xcalloc(n_new_call_in, sizeof(ir_node *));
+ in_req = xcalloc(n_new_call_in, sizeof(arch_register_req_t *));
/* loop over all parameters and set the register requirements */
for (i = 0; i <= biggest_n && (cc & cc_reg_param); i++) {
/* set register requirements for in and out */
attr = get_ia32_attr(new_call);
attr->in_req = in_req;
- attr->out_req = calloc(2, sizeof(ia32_register_req_t *));
+ attr->out_req = xcalloc(2, sizeof(ia32_register_req_t *));
attr->out_req[0] = &ia32_default_req_ia32_general_purpose_eax;
attr->out_req[1] = &ia32_default_req_ia32_general_purpose_edx;
- attr->slots = calloc(2, sizeof(arch_register_t *));
+ attr->slots = xcalloc(2, sizeof(arch_register_t *));
/* stack parameter has no OUT register */
attr->in_req[n_new_call_in - 1] = &ia32_default_req_none;
-/**
- * creates a unique ident by adding a number to a tag
- *
- * @param tag the tag string, must contain a %d if a number
- * should be added
- */
-static ident *unique_id(const char *tag)
-{
- static unsigned id = 0;
- char str[256];
-
- snprintf(str, sizeof(str), tag, ++id);
- return new_id_from_str(str);
-}
-
-/**
- * Transforms a SymConst.
- *
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir SymConst node
- * @param mode mode of the SymConst
- * @return the created ia32 Const node
- */
-static ir_node *gen_SymConst(transform_env_t *env) {
- ir_node *cnst;
- firm_dbg_module_t *mod = env->mod;
- dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
-
- if (mode_is_float(mode)) {
- cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
-
- }
- else {
- cnst = new_rd_ia32_Const(dbg, irg, block, mode);
- }
-
- set_ia32_Const_attr(cnst, env->irn);
- return cnst;
-}
-
-/**
- * Transforms a Const.
- *
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir Const node
- * @param mode mode of the Const
- * @return the created ia32 Const node
- */
-static ir_node *gen_Const(transform_env_t *env) {
- ir_node *cnst;
- entity *ent;
- ir_type *tp;
- symconst_symbol sym;
- firm_dbg_module_t *mod = env->mod;
- dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
- ir_node *node = env->irn;
-
- if (mode_is_float(mode)) {
- tp = get_Const_type(node);
- if (tp == firm_unknown_type) {
- tp = new_type_primitive(unique_id("tp_ia32_float_%u"), mode);
- }
-
- ent = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
-
- set_entity_ld_ident(ent, get_entity_ident(ent));
- set_entity_visibility(ent, visibility_local);
- set_entity_variability(ent, variability_constant);
- set_entity_allocation(ent, allocation_static);
-
- set_atomic_ent_value(ent, node);
-
- sym.entity_p = ent;
-
- cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
- env->irn = cnst;
- cnst = gen_SymConst(env);
- }
- else {
- cnst = new_rd_ia32_Const(dbg, irg, block, mode);
- set_ia32_Const_attr(cnst, node);
- }
-
- return cnst;
-}
-
-
-
/**
* Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
*
* @param mode mode of the Cond
* @return The transformed node.
*/
-static ir_node *gen_Cond(transform_env_t *env) {
- firm_dbg_module_t *mod = env->mod;
+static ir_node *gen_Cond(ia32_transform_env_t *env) {
dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *node = env->irn;
* @param start the Start node
* @return Should be always NULL
*/
-static ir_node *gen_Proj_Start(transform_env_t *env, ir_node *proj, ir_node *start) {
+static ir_node *gen_Proj_Start(ia32_transform_env_t *env, ir_node *proj, ir_node *start) {
const ia32_register_req_t *temp_req;
const ir_edge_t *edge;
ir_node *succ, *irn;
entity *irg_ent = get_irg_entity(current_ir_graph);
ir_type *tp = get_entity_type(irg_ent);
int cur_pn = 0;
- firm_dbg_module_t *mod = env->mod;
- dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
n = get_irn_n_edges(proj);
/* Allocate memory for all non variadic parameters in advance to be on the save side */
- env->cg->reg_param_req = calloc(get_method_n_params(tp), sizeof(ia32_register_req_t *));
+ env->cg->reg_param_req = xcalloc(get_method_n_params(tp), sizeof(ia32_register_req_t *));
/* we are done here when there are no parameters */
if (n < 1)
break;
/* temporary remember all proj arg x */
- projargs = calloc(n, sizeof(ir_node *));
+ projargs = xcalloc(n, sizeof(ir_node *));
i = 0;
foreach_out_edge((const ir_node *)proj, edge) {
* @param mode mode of the Proj
* @return The transformed node.
*/
-static ir_node *gen_Proj(transform_env_t *env) {
+static ir_node *gen_Proj(ia32_transform_env_t *env) {
ir_node *new_node = NULL;
ir_node *pred = get_Proj_pred(env->irn);
+/**
+ * Transforms an Alloc node into either ia32_Alloca or ia32_Malloc.
+ */
+static ir_node *gen_Alloc(ia32_transform_env_t *env) {
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *irn = env->irn;
+ ir_mode *mode = env->mode;
+ ir_node *size = get_Alloc_size(irn);
+ ir_node *mem = get_Alloc_mem(irn);
+ ir_node *res;
+
+ if (get_Alloc_where(irn) == stack_alloc) {
+ if (is_ia32_Const(size)) {
+ res = new_rd_ia32_Alloca_i(dbg, irg, block, mem, mode);
+ set_ia32_Immop_attr(res, size);
+ }
+ else {
+ res = new_rd_ia32_Alloca(dbg, irg, block, size, mem, mode);
+ }
+ }
+ else {
+ assert(0 && "malloc should be already lowered");
+ res = NULL;
+ }
+
+ return res;
+}
+
/*********************************************************
* _ _ _
* (_) | | (_)
ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
opcode code = get_irn_opcode(node);
ir_node *asm_node = NULL;
- transform_env_t tenv;
+ ia32_transform_env_t tenv;
if (is_Block(node))
return;
#define IGN(a) case iro_##a: break
#define BAD(a) case iro_##a: goto bad
- DBG((tenv.mod, LEVEL_1, "transforming node %s (%ld) ... ", get_irn_opname(node), get_irn_node_nr(node)));
+ DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
switch (code) {
BINOP_COM(Add);
GEN(Load);
GEN(Store);
GEN(Call);
- GEN(Const);
- GEN(SymConst);
GEN(Cond);
-
GEN(Proj);
+ GEN(Alloc);
IGN(Block);
IGN(Start);
IGN(IJmp);
IGN(Break);
IGN(Cmp);
+ IGN(Unknown);
+ /* constant transformation happens earlier */
+ IGN(Const);
+ IGN(SymConst);
- BAD(Alloc);
BAD(Raise);
BAD(Sel);
BAD(InstOf);
BAD(Id);
BAD(Bad);
BAD(Confirm);
- BAD(Unknown);
BAD(Filter);
BAD(CallBegin);
BAD(EndReg);
if (asm_node) {
exchange(node, asm_node);
- DBG((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
+ DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
}
else {
- DBG((tenv.mod, LEVEL_1, "ignored\n"));
+ DB((tenv.mod, LEVEL_1, "ignored\n"));
}
}
projects / libfirm / blobdiff