class_negtv = classify_tarval(tarval_neg(tv));
if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
- DBG((env->mod, LEVEL_2, "optimizing Add(1) to Inc ... "));
+ DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode);
}
else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
- DBG((mod, LEVEL_2, "optimizing Add(-1) to Dec ... "));
+ DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode);
}
else
class_negtv = classify_tarval(tarval_neg(tv));
if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
- DBG((mod, LEVEL_2, "optimizing Sub(1) to Dec ... "));
+ DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
new_op = new_rd_ia32_Dec(dbg, irg, block, expr_op, mode);
}
else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
- DBG((mod, LEVEL_2, "optimizing Sub(-1) to Inc ... "));
+ DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
new_op = new_rd_ia32_Inc(dbg, irg, block, expr_op, mode);
}
else
long bits = get_mode_size_bits(env->mode);
if (tarval_is_long(tv) && get_tarval_long(tv) == bits) {
- DBG((env->mod, LEVEL_1, "optimizing RotL into RotR ... "));
+ DB((env->mod, LEVEL_1, "RotL into RotR ... "));
rotate = gen_RotR(env, op1, get_irn_n(minus, 0));
}
}
/* TODO: Op(Const, Const) support */
if (is_ia32_Const(op1) && is_ia32_Const(op2)) {
- DBG((mod, LEVEL_2, "found unexpected %s(Const, Const), creating binop ... ", get_irn_opname(node)));
+ DB((mod, LEVEL_2, "%+F(Const, Const) -> binop ... ", get_irn_opname(node)));
imm_op = NULL;
}
case iro_Div:
case iro_Mod:
case iro_DivMod:
- DBG((mod, LEVEL_2, "Div/Mod/DivMod imm not available, creating binop ... "));
+ DB((mod, LEVEL_2, "Div/Mod/DivMod imm -> binop ... "));
imm_op = NULL;
break;
default:
if (op == get_op_Min() || op == get_op_Max()) {
- DBG((mod, LEVEL_2, "MIN/MAX imm not available, creating binop ... "));
+ DB((mod, LEVEL_2, "MIN/MAX imm -> binop ... "));
imm_op = NULL;
}
break;
}
- DBG((mod, LEVEL_1, "(op1: %s -- op2: %s) ... ", get_irn_opname(op1), get_irn_opname(op2)));
+ DB((mod, LEVEL_1, "(%+F -- %+F) ... ", op1, op2));
if (!mode_is_float(env->mode) && imm_op) {
- DBG((mod, LEVEL_1, "%s with imm ... ", get_irn_opname(node)));
+ DB((mod, LEVEL_1, "immop ... "));
switch(opc) {
GENOPI_SETATTR(Add);
}
}
else {
- DBG((mod, LEVEL_1, "%s as binop ... ", get_irn_opname(node)));
+ DB((mod, LEVEL_1, "binop ... "));
switch(opc) {
GENOP(Add);
*/
static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
if (is_ia32_Minus(op) || is_ia32_fMinus(op)) {
- DBG((env->mod, LEVEL_1, "optimizing --(e) to e ..."));
+ DB((env->mod, LEVEL_1, "--(e) to e ..."));
return get_irn_n(op, 0);
}
else {
/* do we need to pass arguments on stack? */
if (biggest_n + 1 < n)
- stack_param = calloc(n - biggest_n - 1, sizeof(ir_node *));
+ stack_param = xcalloc(n - biggest_n - 1, sizeof(ir_node *));
/* we need at least one in, either for the stack params or the call_Mem */
n_new_call_in = biggest_n + 2;
/* the call has one IN for all stack parameter and one IN for each reg param */
- in = calloc(n_new_call_in, sizeof(ir_node *));
- in_req = calloc(n_new_call_in, sizeof(arch_register_req_t *));
+ in = xcalloc(n_new_call_in, sizeof(ir_node *));
+ in_req = xcalloc(n_new_call_in, sizeof(arch_register_req_t *));
/* loop over all parameters and set the register requirements */
for (i = 0; i <= biggest_n && (cc & cc_reg_param); i++) {
/* set register requirements for in and out */
attr = get_ia32_attr(new_call);
attr->in_req = in_req;
- attr->out_req = calloc(2, sizeof(ia32_register_req_t *));
+ attr->out_req = xcalloc(2, sizeof(ia32_register_req_t *));
attr->out_req[0] = &ia32_default_req_ia32_general_purpose_eax;
attr->out_req[1] = &ia32_default_req_ia32_general_purpose_edx;
- attr->slots = calloc(2, sizeof(arch_register_t *));
+ attr->slots = xcalloc(2, sizeof(arch_register_t *));
/* stack parameter has no OUT register */
attr->in_req[n_new_call_in - 1] = &ia32_default_req_none;
n = get_irn_n_edges(proj);
/* Allocate memory for all non variadic parameters in advance to be on the save side */
- env->cg->reg_param_req = calloc(get_method_n_params(tp), sizeof(ia32_register_req_t *));
+ env->cg->reg_param_req = xcalloc(get_method_n_params(tp), sizeof(ia32_register_req_t *));
/* we are done here when there are no parameters */
if (n < 1)
break;
/* temporary remember all proj arg x */
- projargs = calloc(n, sizeof(ir_node *));
+ projargs = xcalloc(n, sizeof(ir_node *));
i = 0;
foreach_out_edge((const ir_node *)proj, edge) {
+/**
+ * Transforms an Alloc node into either ia32_Alloca or ia32_Malloc.
+ */
+static ir_node *gen_Alloc(ia32_transform_env_t *env) {
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *irn = env->irn;
+ ir_mode *mode = env->mode;
+ ir_node *size = get_Alloc_size(irn);
+ ir_node *mem = get_Alloc_mem(irn);
+ ir_node *res;
+
+ if (get_Alloc_where(irn) == stack_alloc) {
+ if (is_ia32_Const(size)) {
+ res = new_rd_ia32_Alloca_i(dbg, irg, block, mem, mode);
+ set_ia32_Immop_attr(res, size);
+ }
+ else {
+ res = new_rd_ia32_Alloca(dbg, irg, block, size, mem, mode);
+ }
+ }
+ else {
+ assert(0 && "malloc should be already lowered");
+ res = NULL;
+ }
+
+ return res;
+}
+
/*********************************************************
* _ _ _
* (_) | | (_)
#define IGN(a) case iro_##a: break
#define BAD(a) case iro_##a: goto bad
- DBG((tenv.mod, LEVEL_1, "transforming node %s (%ld) ... ", get_irn_opname(node), get_irn_node_nr(node)));
+ DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
switch (code) {
BINOP_COM(Add);
GEN(Store);
GEN(Call);
GEN(Cond);
-
GEN(Proj);
+ GEN(Alloc);
IGN(Block);
IGN(Start);
IGN(Const);
IGN(SymConst);
- BAD(Alloc);
BAD(Raise);
BAD(Sel);
BAD(InstOf);
if (asm_node) {
exchange(node, asm_node);
- DBG((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
+ DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
}
else {
- DBG((tenv.mod, LEVEL_1, "ignored\n"));
+ DB((tenv.mod, LEVEL_1, "ignored\n"));
}
}
projects / libfirm / blobdiff