#include "irprintf.h"
#include "debug.h"
#include "irdom.h"
+#include "type.h"
+#include "entity.h"
#include "archop.h" /* we need this for Min and Max nodes */
#include "../benode_t.h"
#include "ia32_map_regs.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
+#include "ia32_util.h"
#include "gen_ia32_regalloc_if.h"
* Returns 1 if irn is a Const representing 0, 0 otherwise
*/
static INLINE int is_ia32_Const_0(ir_node *irn) {
- return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
+ return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
+ classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
}
/**
* Returns 1 if irn is a Const representing 1, 0 otherwise
*/
static INLINE int is_ia32_Const_1(ir_node *irn) {
- return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
+ return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
+ classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
}
/**
* @return The constructed ia32 node.
*/
static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2, construct_binop_func *func) {
- ir_node *new_op = NULL;
- ir_mode *mode = env->mode;
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_node *block = env->block;
- ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
- ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
- ir_node *nomem = new_NoMem();
- ir_node *expr_op, *imm_op;
+ ir_node *new_op = NULL;
+ ir_mode *mode = env->mode;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
+ ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
+ ir_node *nomem = new_NoMem();
+ int is_mul = 0;
+ ir_node *expr_op, *imm_op;
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- /* MulS and Mulh don't support immediates */
+ /* Mul/MulS/Mulh don't support immediates */
if (! (env->cg->opt & IA32_OPT_IMMOPS) ||
+ func == new_rd_ia32_Mul ||
func == new_rd_ia32_Mulh ||
func == new_rd_ia32_MulS)
{
expr_op = op1;
imm_op = NULL;
+ /* immediate operations are requested, but we are here: it a mul */
+ if (env->cg->opt & IA32_OPT_IMMOPS)
+ is_mul = 1;
}
else if (is_op_commutative(get_irn_op(env->irn))) {
imm_op = get_immediate_op(op1, op2);
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
}
+
+ /* Muls can only have AM source */
+ if (is_mul)
+ set_ia32_am_support(new_op, ia32_am_Source);
}
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
set_ia32_am_flavour(new_op, ia32_am_OB);
- DBG_OPT_LEA1(op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- DBG_OPT_LEA2(op1, op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
}
else {
/* integer SUB */
- if (!expr_op) {
+ if (! expr_op) {
/* No expr_op means, that we have two const - one symconst and */
/* one tarval or another symconst - because this case is not */
/* covered by constant folding */
/* We need to check for: */
- /* 1) symconst + const -> becomes a LEA */
- /* 2) symconst + symconst -> becomes a const + LEA as the elf */
+ /* 1) symconst - const -> becomes a LEA */
+ /* 2) symconst - symconst -> becomes a const - LEA as the elf */
/* linker doesn't support two symconsts */
if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
set_ia32_am_sc_sign(new_op);
set_ia32_am_flavour(new_op, ia32_am_OB);
- DBG_OPT_LEA1(op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- DBG_OPT_LEA2(op1, op2, new_op);
+ DBG_OPT_LEA3(op1, op2, env->irn, new_op);
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
ir_mode *mode = env->mode;
ir_node *irn = env->irn;
ir_node *mem;
+ int n;
switch (dm_flav) {
case flavour_Div:
/* Only one proj is used -> We must add a second proj and */
/* connect this one to a Keep node to eat up the second */
/* destroyed register. */
- if (get_irn_n_edges(irn) == 1) {
- proj = get_edge_src_irn(get_irn_out_edge_first(irn));
- assert(is_Proj(proj) && "non-Proj to Div/Mod node");
+ n = get_irn_n_edges(irn);
+ proj = NULL;
+ if (n == 2)
+ proj = ia32_get_proj_for_mode(irn, mode_M);
+
+ /* in case of two projs, one must be the memory proj */
+ if (n == 1 || (n == 2 && proj)) {
+ proj = ia32_get_res_proj(irn);
+ assert(proj && "Result proj expected");
if (get_irn_op(irn) == op_Div) {
set_Proj_proj(proj, pn_DivMod_res_div);
size = get_mode_size_bits(env->mode);
name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
- set_ia32_sc(new_op, name);
+ set_ia32_am_sc(new_op, name);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, env->mode);
- set_ia32_immop_type(new_op, ia32_ImmSymConst);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_ls_mode(new_op, env->mode);
new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, pn_ia32_xEor_res);
}
size = get_mode_size_bits(mode);
name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_sc(res, name);
+ set_ia32_am_sc(res, name);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
- set_ia32_immop_type(res, ia32_ImmSymConst);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ set_ia32_ls_mode(res, env->mode);
res = new_rd_Proj(dbg, irg, block, res, mode, pn_ia32_xAnd_res);
}
* @return The transformed node.
*/
static ir_node *gen_CopyB(ia32_transform_env_t *env) {
- ir_node *res = NULL;
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_mode *mode = env->mode;
- ir_node *block = env->block;
- ir_node *node = env->irn;
- ir_node *src = get_CopyB_src(node);
- ir_node *dst = get_CopyB_dst(node);
- ir_node *mem = get_CopyB_mem(node);
- int size = get_type_size_bytes(get_CopyB_type(node));
- int rem;
+ ir_node *res = NULL;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *node = env->irn;
+ ir_node *src = get_CopyB_src(node);
+ ir_node *dst = get_CopyB_dst(node);
+ ir_node *mem = get_CopyB_mem(node);
+ int size = get_type_size_bytes(get_CopyB_type(node));
+ ir_mode *dst_mode = get_irn_mode(dst);
+ ir_mode *src_mode = get_irn_mode(src);
+ int rem;
+ ir_node *in[3], *tmp;
/* If we have to copy more than 16 bytes, we use REP MOVSx and */
/* then we need the size explicitly in ECX. */
set_ia32_op_type(res, ia32_Const);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
- res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem, mode);
+ res = new_rd_ia32_CopyB(dbg, irg, block, dst, src, res, mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
+
+ /* ok: now attach Proj's because rep movsd will destroy esi, edi and ecx */
+ in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_DST);
+ in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_SRC);
+ in[2] = new_r_Proj(irg, block, res, mode_Is, pn_ia32_CopyB_CNT);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 3, in);
+
+ tmp = ia32_get_proj_for_mode(node, mode_M);
+ set_Proj_proj(tmp, pn_ia32_CopyB_M);
}
else {
- res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem, mode);
+ res = new_rd_ia32_CopyB_i(dbg, irg, block, dst, src, mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
set_ia32_immop_type(res, ia32_ImmConst);
+
+ /* ok: now attach Proj's because movsd will destroy esi and edi */
+ in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
+ in[1] = new_r_Proj(irg, block, res, src_mode, pn_ia32_CopyB_i_SRC);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 2, in);
+
+ tmp = ia32_get_proj_for_mode(node, mode_M);
+ set_Proj_proj(tmp, pn_ia32_CopyB_i_M);
}
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
- set_ia32_am_support(and1, ia32_am_Source);
+ set_ia32_am_support(and1, ia32_am_None);
set_ia32_res_mode(and1, mode);
SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
- set_ia32_am_support(and2, ia32_am_Source);
+ set_ia32_am_support(and2, ia32_am_None);
set_ia32_res_mode(and2, mode);
SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
- set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_am_support(new_op, ia32_am_None);
set_ia32_res_mode(new_op, mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
return new_op;
}
+/**
+ * In case SSE is used we need to copy the result from FPU TOS.
+ */
+static ir_node *gen_be_Call(ia32_transform_env_t *env) {
+ ir_node *call_res = get_proj_for_pn(env->irn, pn_be_Call_first_res);
+ ir_node *call_mem = get_proj_for_pn(env->irn, pn_be_Call_M_regular);
+ ir_mode *mode;
+
+ if (! call_res || ! USE_SSE2(env->cg))
+ return NULL;
+
+ mode = get_irn_mode(call_res);
+
+ if (mode_is_float(mode)) {
+ /* store st(0) onto stack */
+ ir_node *frame = get_irg_frame(env->irg);
+ ir_node *fstp = new_rd_ia32_GetST0(env->dbg, env->irg, env->block, frame, call_mem);
+ ir_node *mproj = new_r_Proj(env->irg, env->block, fstp, mode_M, pn_ia32_GetST0_M);
+ entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
+ ir_node *sse_load;
+
+ set_ia32_ls_mode(fstp, mode);
+ set_ia32_op_type(fstp, ia32_AddrModeD);
+ set_ia32_use_frame(fstp);
+ set_ia32_frame_ent(fstp, ent);
+ set_ia32_am_flavour(fstp, ia32_B);
+ set_ia32_am_support(fstp, ia32_am_Dest);
+
+ /* load into SSE register */
+ sse_load = new_rd_ia32_xLoad(env->dbg, env->irg, env->block, frame, ia32_new_NoReg_gp(env->cg), mproj);
+ set_ia32_ls_mode(sse_load, mode);
+ set_ia32_op_type(sse_load, ia32_AddrModeS);
+ set_ia32_use_frame(sse_load);
+ set_ia32_frame_ent(sse_load, ent);
+ set_ia32_am_flavour(sse_load, ia32_B);
+ set_ia32_am_support(sse_load, ia32_am_Source);
+ sse_load = new_r_Proj(env->irg, env->block, sse_load, mode, pn_ia32_xLoad_res);
+
+ /* reroute all users of the result proj to the sse load */
+ edges_reroute(call_res, sse_load, env->irg);
+ }
+
+ return NULL;
+}
+
+/**
+ * In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
+ */
+static ir_node *gen_be_Return(ia32_transform_env_t *env) {
+ ir_node *ret_val = get_irn_n(env->irn, be_pos_Return_val);
+ ir_node *ret_mem = get_irn_n(env->irn, be_pos_Return_mem);
+ entity *ent = get_irg_entity(get_irn_irg(ret_val));
+ ir_type *tp = get_entity_type(ent);
+
+ if (be_Return_get_n_rets(env->irn) < 1 || ! ret_val || ! USE_SSE2(env->cg))
+ return NULL;
+
+
+ if (get_method_n_ress(tp) == 1) {
+ ir_type *res_type = get_method_res_type(tp, 0);
+ ir_mode *mode;
+
+ if(is_Primitive_type(res_type)) {
+ mode = get_type_mode(res_type);
+ if(mode_is_float(mode)) {
+ ir_node *frame = get_irg_frame(env->irg);
+ entity *ent = frame_alloc_area(get_irg_frame_type(env->irg), get_mode_size_bytes(mode), 16, 0);
+ ir_node *sse_store, *fld, *mproj;
+
+ /* store xmm0 onto stack */
+ sse_store = new_rd_ia32_xStoreSimple(env->dbg, env->irg, env->block, frame, ret_val, ret_mem);
+ set_ia32_ls_mode(sse_store, mode);
+ set_ia32_op_type(sse_store, ia32_AddrModeD);
+ set_ia32_use_frame(sse_store);
+ set_ia32_frame_ent(sse_store, ent);
+ set_ia32_am_flavour(sse_store, ia32_B);
+ set_ia32_am_support(sse_store, ia32_am_Dest);
+ sse_store = new_r_Proj(env->irg, env->block, sse_store, mode_M, pn_ia32_xStore_M);
+
+ /* load into st0 */
+ fld = new_rd_ia32_SetST0(env->dbg, env->irg, env->block, frame, sse_store);
+ set_ia32_ls_mode(fld, mode);
+ set_ia32_op_type(fld, ia32_AddrModeS);
+ set_ia32_use_frame(fld);
+ set_ia32_frame_ent(fld, ent);
+ set_ia32_am_flavour(fld, ia32_B);
+ set_ia32_am_support(fld, ia32_am_Source);
+ mproj = new_r_Proj(env->irg, env->block, fld, mode_M, pn_ia32_SetST0_M);
+ fld = new_r_Proj(env->irg, env->block, fld, mode, pn_ia32_SetST0_res);
+
+ /* set new return value */
+ set_irn_n(env->irn, be_pos_Return_val, fld);
+ set_irn_n(env->irn, be_pos_Return_mem, mproj);
+ }
+ }
+ }
+
+ return NULL;
+}
+
+
/**
* This function just sets the register for the Unknown node
* as this is not done during register allocation because Unknown
new_op = func(env->dbg, env->irg, env->block, get_irn_n(node, 0), noreg, get_irn_n(node, 1), get_irn_n(node, 2));
- if (am_offs = get_ia32_am_offs(node)) {
+ if ((am_offs = get_ia32_am_offs(node)) != NULL) {
am_flav |= ia32_O;
add_ia32_am_offs(new_op, am_offs);
}
IGN(SymConst);
IGN(Sync);
+ /* we should never see these nodes */
BAD(Raise);
BAD(Sel);
BAD(InstOf);
BAD(EndReg);
BAD(EndExcept);
+ /* handle generic backend nodes */
GEN(be_FrameAddr);
+ GEN(be_Call);
+ GEN(be_Return);
GEN(be_FrameLoad);
GEN(be_FrameStore);
GEN(be_StackParam);
* "And"s and "Or"s are transformed later, we just have to set their mode right.
*/
void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
- ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
+ ia32_code_gen_t *cg = env;
ir_node *psi_sel, *new_cmp, *block;
ir_graph *irg;
ir_mode *mode;
/* BEWARE: new_r_Const_long works for floating point as well */
new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
- /* transform the const */
- ia32_place_consts_set_modes(new_cmp, cg);
new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
set_Psi_cond(node, 0, new_cmp);
projects / libfirm / blobdiff