#include "gen_ia32_regalloc_if.h"
-#define SFP_SIGN "0x80000000"
-#define DFP_SIGN "0x8000000000000000"
-#define SFP_ABS "0x7FFFFFFF"
-#define DFP_ABS "0x7FFFFFFFFFFFFFFF"
+#define SFP_SIGN "0x80000000"
+#define DFP_SIGN "0x8000000000000000"
+#define SFP_ABS "0x7FFFFFFF"
+#define DFP_ABS "0x7FFFFFFFFFFFFFFF"
+#define DFP_INTMAX "9223372036854775807"
#define TP_SFP_SIGN "ia32_sfp_sign"
#define TP_DFP_SIGN "ia32_dfp_sign"
#define TP_SFP_ABS "ia32_sfp_abs"
#define TP_DFP_ABS "ia32_dfp_abs"
+#define TP_INT_MAX "ia32_int_max"
#define ENT_SFP_SIGN "IA32_SFP_SIGN"
#define ENT_DFP_SIGN "IA32_DFP_SIGN"
#define ENT_SFP_ABS "IA32_SFP_ABS"
#define ENT_DFP_ABS "IA32_DFP_ABS"
+#define ENT_INT_MAX "IA32_INT_MAX"
#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
extern ir_op *get_op_Mulh(void);
typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
- ir_node *op2, ir_node *mem);
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op1, ir_node *op2);
typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
ir_node *block, ir_node *op1, ir_node *op2);
typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *op,
- ir_node *mem);
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op);
typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
- ir_node *op2, ir_node *mem, ir_node *fpcw);
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op1, ir_node *op2, ir_node *fpcw);
typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
ir_node *block, ir_node *op);
char immediate_constraint_type);
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
- dbg_info *dbgi, ir_node *new_block,
- ir_node *new_op);
+ dbg_info *dbgi, ir_node *block,
+ ir_node *op, ir_node *orig_node);
/**
* Return true if a mode can be stored in the GP register set
static INLINE int mode_needs_gp_reg(ir_mode *mode) {
if(mode == mode_fpcw)
return 0;
+ if(get_mode_size_bits(mode) > 32)
+ return 0;
return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
}
}
static int is_Const_0(ir_node *node) {
- if(!is_Const(node))
- return 0;
-
- return classify_Const(node) == CNST_NULL;
+ return is_Const(node) && is_Const_null(node);
}
static int is_Const_1(ir_node *node) {
- if(!is_Const(node))
- return 0;
-
- return classify_Const(node) == CNST_ONE;
+ return is_Const(node) && is_Const_one(node);
}
static int is_Const_Minus_1(ir_node *node) {
- tarval *tv;
- ir_mode *mode;
- if(!is_Const(node))
- return 0;
-
- mode = get_irn_mode(node);
- if(!mode_is_signed(mode))
- return 0;
-
- tv = get_Const_tarval(node);
- tv = tarval_neg(tv);
-
- return classify_tarval(tv) == CNST_ONE;
+ return is_Const(node) && is_Const_all_one(node);
}
/**
ir_node *nomem = new_NoMem();
ir_node *load;
ir_entity *floatent;
- cnst_classify_t clss = classify_Const(node);
if (USE_SSE2(env_cg)) {
- if (clss == CNST_NULL) {
+ if (is_Const_null(node)) {
load = new_rd_ia32_xZero(dbgi, irg, block);
set_ia32_ls_mode(load, mode);
res = load;
res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
}
} else {
- if (clss == CNST_NULL) {
+ if (is_Const_null(node)) {
load = new_rd_ia32_vfldz(dbgi, irg, block);
res = load;
- } else if (clss == CNST_ONE) {
+ } else if (is_Const_one(node)) {
load = new_rd_ia32_vfld1(dbgi, irg, block);
res = load;
} else {
cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
+ if(val == 0) {
+ set_ia32_flags(cnst,
+ get_ia32_flags(cnst) | arch_irn_flags_modify_flags);
+ }
/* see above */
if (get_irg_start_block(irg) == block) {
else
cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
set_ia32_am_sc(cnst, get_SymConst_entity(node));
+ set_ia32_use_frame(cnst);
} else {
ir_entity *entity;
const char *tp_name;
const char *ent_name;
const char *cnst_str;
+ char mode;
+ char align;
} names [ia32_known_const_max] = {
- { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
- { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
- { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
- { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
+ { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
+ { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
+ { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
+ { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
+ { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
};
static ir_entity *ent_cache[ia32_known_const_max];
tp_name = names[kct].tp_name;
cnst_str = names[kct].cnst_str;
- mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
- //mode = mode_xmm;
+ switch (names[kct].mode) {
+ case 0: mode = mode_Iu; break;
+ case 1: mode = mode_Lu; break;
+ default: mode = mode_F; break;
+ }
tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
tp = new_type_primitive(new_id_from_str(tp_name), mode);
- /* these constants are loaded as part of an instruction, so they must be aligned
- to 128 bit. */
- set_type_alignment_bytes(tp, 16);
+ /* set the specified alignment */
+ set_type_alignment_bytes(tp, names[kct].align);
+
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
set_entity_ld_ident(ent, get_entity_ident(ent));
mode = get_irn_mode(node);
if(!mode_needs_gp_reg(mode))
return 0;
- if(get_mode_size_bits(mode) != 32)
+ if(other != NULL && get_Load_mode(load) != get_irn_mode(other))
return 0;
/* don't do AM if other node inputs depend on the load (via mem-proj) */
set_ia32_commutative(node);
}
+typedef enum {
+ match_commutative = 1 << 0,
+ match_am_and_immediates = 1 << 1,
+ match_no_am = 1 << 2,
+ match_8_16_bit_am = 1 << 3
+} match_flags_t;
+
static void match_arguments(ia32_address_mode_t *am, ir_node *block,
- ir_node *op1, ir_node *op2, int commutative,
- int use_am_and_immediates, int use_am)
+ ir_node *op1, ir_node *op2, match_flags_t flags)
{
ia32_address_t *addr = &am->addr;
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ir_node *new_op1;
ir_node *new_op2;
+ int use_am;
+ int commutative;
+ int use_am_and_immediates;
memset(am, 0, sizeof(am[0]));
+ commutative = (flags & match_commutative) != 0;
+ use_am_and_immediates = (flags & match_am_and_immediates) != 0;
+ use_am = ! (flags & match_no_am);
+ if(!(flags & match_8_16_bit_am)
+ && get_mode_size_bits(get_irn_mode(op1)) < 32)
+ use_am = 0;
+
new_op2 = try_create_Immediate(op2, 0);
if(new_op2 == NULL && use_am && use_source_address_mode(block, op2, op1)) {
build_address(am, op2);
if(mode != mode_T) {
set_irn_mode(node, mode_T);
- return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, 0);
+ return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
} else {
return node;
}
ir_node *new_node;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
+ match_flags_t flags = 0;
+
+ if(commutative)
+ flags |= match_commutative;
- match_arguments(&am, src_block, op1, op2, commutative, 0, 1);
+ match_arguments(&am, src_block, op1, op2, flags);
- new_node = func(dbgi, irg, block, addr->base, addr->index, am.new_op1,
- am.new_op2, addr->mem);
+ new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
+ am.new_op1, am.new_op2);
set_am_attributes(new_node, &am);
/* we can't use source address mode anymore when using immediates */
if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
- new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
- nomem);
+ new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1,
+ new_op2);
if (is_op_commutative(get_irn_op(node))) {
set_ia32_commutative(new_node);
}
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ir_node *nomem = new_NoMem();
- new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
- nomem, get_fpcw());
+ new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op1, new_op2,
+ get_fpcw());
if (is_op_commutative(get_irn_op(node))) {
set_ia32_commutative(new_node);
}
/* construct an Add with source address mode */
if(new_op1 != NULL) {
ia32_address_t *am_addr = &am.addr;
- new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base,
- am_addr->index, new_op1, noreg, am_addr->mem);
+ new_op = new_rd_ia32_Add(dbgi, irg, block, am_addr->base, am_addr->index,
+ am_addr->mem, new_op1, noreg);
set_address(new_op, am_addr);
set_ia32_op_type(new_op, ia32_AddrModeS);
set_ia32_ls_mode(new_op, am.ls_mode);
assert(!mode_is_float(mode) && "Mulh with float not supported");
if (mode_is_signed(mode)) {
- res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
- new_op2, new_NoMem());
+ res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_NoMem(),
+ new_op1, new_op2);
} else {
- res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
- new_NoMem());
+ res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(), new_op1,
+ new_op2);
}
set_ia32_commutative(res);
if (v == 0xFF || v == 0xFFFF) {
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op = be_transform_node(op1);
+ ir_node *block = get_nodes_block(node);
ir_mode *src_mode;
ir_node *res;
assert(v == 0xFFFF);
src_mode = mode_Hu;
}
- res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
return res;
}
produceval);
} else {
sign_extension = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, 0);
+ set_ia32_flags(sign_extension, get_ia32_flags(sign_extension) | arch_irn_flags_modify_flags);
add_irn_dep(sign_extension, get_irg_frame(irg));
}
if (mode_is_signed(mode)) {
- res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
- sign_extension, new_divisor, new_mem, dm_flav);
+ res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_mem,
+ new_dividend, sign_extension, new_divisor, dm_flav);
} else {
- res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
- sign_extension, new_divisor, new_mem, dm_flav);
+ res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_mem, new_dividend,
+ sign_extension, new_divisor, dm_flav);
}
set_ia32_exc_label(res, has_exc);
if (USE_SSE2(env_cg)) {
ir_mode *mode = get_irn_mode(op1);
- new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1,
- new_op2, nomem);
+ new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
+ new_op2);
set_ia32_ls_mode(new_op, mode);
} else {
- new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
- new_op2, nomem, get_fpcw());
+ new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, nomem, new_op1,
+ new_op2, get_fpcw());
}
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
return new_op;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *base = ia32_new_NoReg_gp(env_cg);
ir_node *index = be_transform_node(get_Shl_left(node));
-
- ir_node *res
- = new_rd_ia32_Lea(dbgi, irg, block, base, index);
+ ir_node *res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
set_ia32_am_scale(res, val);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
return res;
long val = get_tarval_long(tv1);
if(val == 16 || val == 24) {
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op = be_transform_node(shl_left);
+ ir_node *block = get_nodes_block(node);
ir_mode *src_mode;
ir_node *res;
src_mode = mode_Hs;
}
res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
- new_op);
- SET_IA32_ORIG_NODE(res,
- ia32_get_old_node_name(env_cg, node));
+ shl_left, node);
return res;
}
ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
ir_node *nomem = new_rd_NoMem(irg);
- res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
+ res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
+ new_op, noreg_fp);
size = get_mode_size_bits(mode);
ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
ir_node *nomem = new_NoMem();
ir_node *one = create_Immediate_from_int(1);
- return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
+ return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, nomem, new_op, one);
}
/**
if (mode_is_float(mode)) {
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
+ res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, nomem, new_op, noreg_fp);
size = get_mode_size_bits(mode);
ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
SET_IA32_ORIG_NODE(sign_extension,
ia32_get_old_node_name(env_cg, node));
- xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
- sign_extension, nomem);
+ xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem, new_op,
+ sign_extension);
SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
- res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
- sign_extension, nomem);
+ res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem, xor,
+ sign_extension);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
}
/* create a conv node with address mode for smaller modes */
if(get_mode_size_bits(mode) < 32) {
- new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, noreg,
- new_mem, mode);
+ new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index, new_mem,
+ noreg, mode);
} else {
new_op = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
}
static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
ir_node *mem, ir_node *ptr, ir_mode *mode,
- construct_binop_dest_func *func, int commutative)
+ construct_binop_dest_func *func,
+ construct_binop_dest_func *func8bit,
+ int commutative)
{
ir_node *src_block = get_nodes_block(node);
ir_node *block;
dbgi = get_irn_dbg_info(node);
block = be_transform_node(src_block);
- new_node = func(dbgi, irg, block, addr->base, addr->index, new_op,
- addr->mem);
+ if(get_mode_size_bits(mode) == 8) {
+ new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
+ addr->mem, new_op);
+ } else {
+ new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
+ new_op);
+ }
set_address(new_node, addr);
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode);
/* handle only GP modes for now... */
if(!mode_needs_gp_reg(mode))
return NULL;
- if(get_mode_size_bits(mode) != 32)
- return NULL;
/* store must be the only user of the val node */
if(get_irn_n_edges(val) > 1)
break;
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_AddMem, 1);
+ new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit, 1);
break;
case iro_Sub:
op1 = get_Sub_left(val);
op2 = get_Sub_right(val);
+ if(is_Const(op2)) {
+ ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
+ "found\n");
+ }
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_SubMem, 0);
+ new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit, 0);
break;
case iro_And:
op1 = get_And_left(val);
op2 = get_And_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_AndMem, 1);
+ new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit, 1);
break;
case iro_Or:
op1 = get_Or_left(val);
op2 = get_Or_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_OrMem, 1);
+ new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit, 1);
break;
case iro_Eor:
op1 = get_Eor_left(val);
op2 = get_Eor_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_XorMem, 1);
+ new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit, 1);
break;
case iro_Shl:
op1 = get_Shl_left(val);
op2 = get_Shl_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_ShlMem, 0);
+ new_rd_ia32_ShlMem, new_rd_ia32_ShlMem, 0);
break;
case iro_Shr:
op1 = get_Shr_left(val);
op2 = get_Shr_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_ShrMem, 0);
+ new_rd_ia32_ShrMem, new_rd_ia32_ShrMem, 0);
break;
case iro_Shrs:
op1 = get_Shrs_left(val);
op2 = get_Shrs_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_SarMem, 0);
+ new_rd_ia32_SarMem, new_rd_ia32_SarMem, 0);
break;
case iro_Rot:
op1 = get_Rot_left(val);
op2 = get_Rot_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_RolMem, 0);
+ new_rd_ia32_RolMem, new_rd_ia32_RolMem, 0);
break;
/* TODO: match ROR patterns... */
case iro_Minus:
new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
break;
case iro_Not:
- /* TODO this would be ^ 1 with DestAM */
- if(mode == mode_b)
- return NULL;
+ /* should be lowered already */
+ assert(mode != mode_b);
op1 = get_Not_op(val);
new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
break;
if(new_op != NULL)
return new_op;
- /* construct load address */
+ /* construct store address */
memset(&addr, 0, sizeof(addr));
ia32_create_address_mode(&addr, ptr, 0);
base = addr.base;
if (mode_is_float(mode)) {
new_val = be_transform_node(val);
if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_val,
- new_mem);
+ new_op = new_rd_ia32_xStore(dbgi, irg, block, base, index, new_mem,
+ new_val);
} else {
- new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_val,
- new_mem, mode);
+ new_op = new_rd_ia32_vfst(dbgi, irg, block, base, index, new_mem, new_val,
+ mode);
}
} else {
new_val = create_immediate_or_transform(val, 0);
mode = mode_Iu;
if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index,
- new_val, new_mem);
+ new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, base, index, new_mem,
+ new_val);
} else {
- new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_val,
- new_mem);
+ new_op = new_rd_ia32_Store(dbgi, irg, block, base, index, new_mem,
+ new_val);
}
}
return new_op;
}
-static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
- ir_node *cmp_left, ir_node *cmp_right,
- int use_am)
-{
- ir_node *arg_left;
- ir_node *arg_right;
- ir_node *res;
- ir_mode *mode;
- long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
- ia32_address_mode_t am;
- ia32_address_t *addr = &am.addr;
-
- if(cmp_right != NULL && !is_Const_0(cmp_right))
- return NULL;
-
- if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
- mode = get_irn_mode(cmp_left);
- arg_left = get_And_left(cmp_left);
- arg_right = get_And_right(cmp_left);
- } else {
- mode = get_irn_mode(cmp_left);
- arg_left = cmp_left;
- arg_right = cmp_left;
- }
-
- if(mode == mode_b)
- mode = mode_Iu;
-
- assert(get_mode_size_bits(mode) <= 32);
- match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
- if(am.flipped)
- pnc = get_inversed_pnc(pnc);
-
- if(get_mode_size_bits(mode) == 8) {
- res = new_rd_ia32_TestJmp8Bit(dbgi, current_ir_graph, block, addr->base,
- addr->index, am.new_op1, am.new_op2,
- addr->mem, pnc);
- } else {
- res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, addr->base,
- addr->index, am.new_op1, am.new_op2,
- addr->mem, pnc);
- }
- set_am_attributes(res, &am);
- set_ia32_ls_mode(res, mode);
-
- res = fix_mem_proj(res, &am);
-
- return res;
-}
-
static ir_node *create_Switch(ir_node *node)
{
ir_graph *irg = current_ir_graph;
return res;
}
-/**
- * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
- *
- * @return The transformed node.
- */
+static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *flags;
+ ir_node *new_op;
+ ir_node *noreg;
+ ir_node *nomem;
+ ir_node *new_block;
+ dbg_info *dbgi;
+
+ /* we have a Cmp as input */
+ if(is_Proj(node)) {
+ ir_node *pred = get_Proj_pred(node);
+ if(is_Cmp(pred)) {
+ flags = be_transform_node(pred);
+ *pnc_out = get_Proj_proj(node);
+ return flags;
+ }
+ }
+
+ /* a mode_b value, we have to compare it against 0 */
+ dbgi = get_irn_dbg_info(node);
+ new_block = be_transform_node(get_nodes_block(node));
+ new_op = be_transform_node(node);
+ noreg = ia32_new_NoReg_gp(env_cg);
+ nomem = new_NoMem();
+ flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
+ new_op, new_op, 0, 0);
+ *pnc_out = pn_Cmp_Lg;
+ return flags;
+}
+
static ir_node *gen_Cond(ir_node *node) {
- ir_node *src_block = get_nodes_block(node);
- ir_node *block = be_transform_node(src_block);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *sel = get_Cond_selector(node);
ir_mode *sel_mode = get_irn_mode(sel);
- ir_node *res = NULL;
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *cmp;
- ir_node *cmp_a;
- ir_node *cmp_b;
- ir_node *new_cmp_a;
- ir_node *new_cmp_b;
- ir_mode *cmp_mode;
- long pnc;
- int use_am;
+ ir_node *res;
+ ir_node *flags = NULL;
+ pn_Cmp pnc;
if (sel_mode != mode_b) {
return create_Switch(node);
}
- if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
- /* it's some mode_b value but not a direct comparison -> create a
- * testjmp */
- res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL, 1);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
- return res;
- }
-
- /* address mode makes only sense when we're the only user of the cmp */
- use_am = get_irn_n_edges(node) <= 1;
-
- cmp = get_Proj_pred(sel);
- cmp_a = get_Cmp_left(cmp);
- cmp_b = get_Cmp_right(cmp);
- cmp_mode = get_irn_mode(cmp_a);
- pnc = get_Proj_proj(sel);
- if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
- pnc |= ia32_pn_Cmp_Unsigned;
- }
-
- if(mode_needs_gp_reg(cmp_mode)) {
- res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b, use_am);
- if(res != NULL) {
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
- return res;
- }
- }
-
- if (mode_is_float(cmp_mode)) {
- new_cmp_a = be_transform_node(cmp_a);
- new_cmp_b = create_immediate_or_transform(cmp_b, 0);
- if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_xCmpJmp(dbgi, irg, block, noreg, noreg, cmp_a,
- cmp_b, nomem, pnc);
- set_ia32_commutative(res);
- set_ia32_ls_mode(res, cmp_mode);
- } else {
- res = new_rd_ia32_vfCmpJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
- set_ia32_commutative(res);
- }
- } else {
- ia32_address_mode_t am;
- ia32_address_t *addr = &am.addr;
- match_arguments(&am, src_block, cmp_a, cmp_b, 1, 1, use_am);
- if(am.flipped)
- pnc = get_inversed_pnc(pnc);
-
- if(get_mode_size_bits(cmp_mode) == 8) {
- res = new_rd_ia32_CmpJmp8Bit(dbgi, irg, block, addr->base,
- addr->index, am.new_op1, am.new_op2,
- addr->mem, pnc);
- } else {
- res = new_rd_ia32_CmpJmp(dbgi, irg, block, addr->base, addr->index,
- am.new_op1, am.new_op2, addr->mem, pnc);
- }
- set_am_attributes(res, &am);
- assert(cmp_mode != NULL);
- set_ia32_ls_mode(res, cmp_mode);
-
- res = fix_mem_proj(res, &am);
- }
+ /* we get flags from a cmp */
+ flags = get_flags_node(sel, &pnc);
+ res = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
return res;
size >>= 2;
res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
- add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
+ if(size == 0) {
+ ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
+ node);
+ set_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);
+ }
+ add_irn_dep(res, get_irg_frame(irg));
res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
/* we misuse the pncode field for the copyb size */
return res;
}
-static
-ir_node *gen_be_Copy(ir_node *node)
+static ir_node *gen_be_Copy(ir_node *node)
{
ir_node *result = be_duplicate_node(node);
ir_mode *mode = get_irn_mode(result);
return result;
}
+/**
+ * helper function: checks wether all Cmp projs are Lg or Eq which is needed
+ * to fold an and into a test node
+ */
+static int can_fold_test_and(ir_node *node)
+{
+ const ir_edge_t *edge;
-static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
- dbg_info *dbgi, ir_node *block, int use_am)
+ /** we can only have eq and lg projs */
+ foreach_out_edge(node, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ pn_Cmp pnc = get_Proj_proj(proj);
+ if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
+ return 0;
+ }
+
+ return 1;
+}
+
+static ir_node *try_create_Test(ir_node *node)
{
ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *cmp_left = get_Cmp_left(node);
+ ir_node *cmp_right = get_Cmp_right(node);
ir_mode *mode;
- ir_node *arg_left;
- ir_node *arg_right;
+ ir_node *left;
+ ir_node *right;
ir_node *res;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
+ int cmp_unsigned;
/* can we use a test instruction? */
- if(cmp_right == NULL || is_Const_0(cmp_right)) {
- long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
- if(is_And(cmp_left) &&
- (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
- ir_node *and_left = get_And_left(cmp_left);
- ir_node *and_right = get_And_right(cmp_left);
-
- mode = get_irn_mode(and_left);
- arg_left = and_left;
- arg_right = and_right;
- } else {
- mode = get_irn_mode(cmp_left);
- arg_left = cmp_left;
- arg_right = cmp_left;
- }
-
- assert(get_mode_size_bits(mode) <= 32);
-
- match_arguments(&am, block, arg_left, arg_right, 1, 1, use_am);
- if(am.flipped)
- pnc = get_inversed_pnc(pnc);
-
- if(get_mode_size_bits(mode) == 8) {
- res = new_rd_ia32_TestSet8Bit(dbgi, irg, new_block, addr->base,
- addr->index, am.new_op1, am.new_op2,
- addr->mem, pnc);
- } else {
- res = new_rd_ia32_TestSet(dbgi, irg, new_block, addr->base,
- addr->index, am.new_op1, am.new_op2,
- addr->mem, pnc);
- }
- set_am_attributes(res, &am);
- set_ia32_ls_mode(res, mode);
-
- res = fix_mem_proj(res, &am);
+ if(!is_Const_0(cmp_right))
+ return NULL;
- res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
- nomem, mode_Bu);
+ if(is_And(cmp_left) && can_fold_test_and(node)) {
+ ir_node *and_left = get_And_left(cmp_left);
+ ir_node *and_right = get_And_right(cmp_left);
- return res;
+ mode = get_irn_mode(and_left);
+ left = and_left;
+ right = and_right;
+ } else {
+ mode = get_irn_mode(cmp_left);
+ left = cmp_left;
+ right = cmp_left;
}
- mode = get_irn_mode(cmp_left);
assert(get_mode_size_bits(mode) <= 32);
- match_arguments(&am, block, cmp_left, cmp_right, 1, 1, use_am);
- if(am.flipped)
- pnc = get_inversed_pnc(pnc);
+ match_arguments(&am, block, left, right, match_commutative |
+ match_8_16_bit_am | match_am_and_immediates);
+ cmp_unsigned = !mode_is_signed(mode);
if(get_mode_size_bits(mode) == 8) {
- res = new_rd_ia32_CmpSet8Bit(dbgi, irg, new_block, addr->base,
- addr->index, am.new_op1, am.new_op2,
- addr->mem, pnc);
+ res = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.flipped, cmp_unsigned);
} else {
- res = new_rd_ia32_CmpSet(dbgi, irg, new_block, addr->base, addr->index,
- am.new_op1, am.new_op2, addr->mem, pnc);
+ res = new_rd_ia32_Test(dbgi, irg, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, am.flipped,
+ cmp_unsigned);
}
set_am_attributes(res, &am);
+ assert(mode != NULL);
set_ia32_ls_mode(res, mode);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+
res = fix_mem_proj(res, &am);
+ return res;
+}
- res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg, res,
- nomem, mode_Bu);
+static ir_node *create_Fucom(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *left = get_Cmp_left(node);
+ ir_node *new_left = be_transform_node(left);
+ ir_node *right = get_Cmp_right(node);
+ ir_node *new_right = be_transform_node(right);
+ ir_node *res;
+
+ res = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left, new_right,
+ 0);
+ set_ia32_commutative(res);
+
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+
+ res = new_rd_ia32_Sahf(dbgi, irg, new_block, res);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
return res;
}
-static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
- ir_node *val_true, ir_node *val_false,
- dbg_info *dbgi, ir_node *block)
+static ir_node *create_Ucomi(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- ir_node *new_block = be_transform_node(block);
- ir_node *new_val_true = be_transform_node(val_true);
- ir_node *new_val_false = be_transform_node(val_false);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *new_cmp_left;
- ir_node *new_cmp_right;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *left = get_Cmp_left(node);
+ ir_node *new_left = be_transform_node(left);
+ ir_node *right = get_Cmp_right(node);
+ ir_node *new_right = be_transform_node(right);
+ ir_mode *mode = get_irn_mode(left);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
ir_node *res;
- ir_mode *mode;
- /* cmovs with unknowns are pointless... */
- if(is_Unknown(val_true)) {
-#ifdef DEBUG_libfirm
- ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
-#endif
- return new_val_false;
- }
- if(is_Unknown(val_false)) {
-#ifdef DEBUG_libfirm
- ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
-#endif
- return new_val_true;
- }
+ res = new_rd_ia32_Ucomi(dbgi, irg, new_block, noreg, noreg, nomem, new_left,
+ new_right, 0);
+ set_ia32_commutative(res);
+ set_ia32_ls_mode(res, mode);
- /* can we use a test instruction? */
- if(is_Const_0(cmp_right)) {
- long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
- if(is_And(cmp_left) &&
- (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
- ir_node *and_left = get_And_left(cmp_left);
- ir_node *and_right = get_And_right(cmp_left);
-
- mode = get_irn_mode(and_left);
- new_cmp_left = be_transform_node(and_left);
- new_cmp_right = create_immediate_or_transform(and_right, 0);
- } else {
- mode = get_irn_mode(cmp_left);
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = be_transform_node(cmp_left);
- }
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
- assert(get_mode_size_bits(mode) <= 32);
+ return res;
+}
+
+static ir_node *gen_Cmp(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *left = get_Cmp_left(node);
+ ir_node *right = get_Cmp_right(node);
+ ir_mode *cmp_mode = get_irn_mode(left);
+ ir_node *res;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+ int cmp_unsigned;
- if(get_mode_size_bits(mode) == 8) {
- res = new_rd_ia32_TestCMov8Bit(dbgi, current_ir_graph, new_block,
- noreg, noreg, new_cmp_left,
- new_cmp_right, nomem, new_val_true,
- new_val_false, pnc);
+ if(mode_is_float(cmp_mode)) {
+ if (USE_SSE2(env_cg)) {
+ return create_Ucomi(node);
} else {
- res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, new_block, noreg,
- noreg, new_cmp_left, new_cmp_right,
- nomem, new_val_true, new_val_false, pnc);
+ return create_Fucom(node);
}
- set_ia32_ls_mode(res, mode);
-
- return res;
}
- mode = get_irn_mode(cmp_left);
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = create_immediate_or_transform(cmp_right, 0);
+ assert(mode_needs_gp_reg(cmp_mode));
- /* no support for 8,16 bit modes yet */
- assert(get_mode_size_bits(mode) <= 32);
+ /* we prefer the Test instruction where possible except cases where
+ * we can use SourceAM */
+ if(!use_source_address_mode(block, left, right) &&
+ !use_source_address_mode(block, right, left)) {
+ res = try_create_Test(node);
+ if(res != NULL)
+ return res;
+ }
- if(get_mode_size_bits(mode) == 8) {
- res = new_rd_ia32_CmpCMov8Bit(dbgi, irg, new_block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem,
- new_val_true, new_val_false, pnc);
+ match_arguments(&am, block, left, right,
+ match_commutative | match_8_16_bit_am |
+ match_am_and_immediates);
+
+ cmp_unsigned = !mode_is_signed(get_irn_mode(left));
+ if(get_mode_size_bits(cmp_mode) == 8) {
+ res = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2,
+ am.flipped, cmp_unsigned);
} else {
- res = new_rd_ia32_CmpCMov(dbgi, irg, new_block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem,
- new_val_true, new_val_false, pnc);
+ res = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, am.flipped,
+ cmp_unsigned);
}
- set_ia32_ls_mode(res, mode);
+ set_am_attributes(res, &am);
+ assert(cmp_mode != NULL);
+ set_ia32_ls_mode(res, cmp_mode);
+
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+
+ res = fix_mem_proj(res, &am);
+
+ return res;
+}
+
+static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *val_true = get_Psi_val(node, 0);
+ ir_node *new_val_true = be_transform_node(val_true);
+ ir_node *val_false = get_Psi_default(node);
+ ir_node *new_val_false = be_transform_node(val_false);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *res;
+
+ assert(mode_needs_gp_reg(mode));
+
+ res = new_rd_ia32_CMov(dbgi, irg, new_block, noreg, noreg, nomem,
+ new_val_false, new_val_true, new_flags, pnc);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
return res;
}
+
+static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
+ ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
+ ir_node *res;
+
+ res = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
+ res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
+ nomem, res, mode_Bu);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, orig_node));
+
+ return res;
+}
+
/**
* Transforms a Psi node into CMov.
*
* @return The transformed node.
*/
-static ir_node *gen_Psi(ir_node *node) {
+static ir_node *gen_Psi(ir_node *node)
+{
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
ir_node *psi_true = get_Psi_val(node, 0);
ir_node *psi_default = get_Psi_default(node);
- ia32_code_gen_t *cg = env_cg;
ir_node *cond = get_Psi_cond(node, 0);
- ir_node *block = get_nodes_block(node);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_op;
- ir_node *cmp_left;
- ir_node *cmp_right;
+ ir_node *flags = NULL;
+ ir_node *res;
ir_mode *cmp_mode;
- long pnc;
+ pn_Cmp pnc;
assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
assert(mode_needs_gp_reg(get_irn_mode(node)));
- if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
- /* a mode_b value, we have to compare it against 0 */
- cmp_left = cond;
- cmp_right = new_Const_long(mode_Iu, 0);
- pnc = pn_Cmp_Lg;
- cmp_mode = mode_Iu;
- } else {
- ir_node *cmp = get_Proj_pred(cond);
-
- cmp_left = get_Cmp_left(cmp);
- cmp_right = get_Cmp_right(cmp);
- cmp_mode = get_irn_mode(cmp_left);
- pnc = get_Proj_proj(cond);
-
- assert(!mode_is_float(cmp_mode));
-
- if (!mode_is_signed(cmp_mode)) {
- pnc |= ia32_pn_Cmp_Unsigned;
- }
- }
+ flags = get_flags_node(cond, &pnc);
if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
- new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
+ res = create_set_32bit(dbgi, new_block, flags, pnc, node);
} else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
pnc = get_negated_pnc(pnc, cmp_mode);
- new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block, 1);
+ res = create_set_32bit(dbgi, new_block, flags, pnc, node);
} else {
- new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
- dbgi, block);
+ res = create_CMov(node, flags, pnc);
}
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
- return new_op;
+ return res;
}
ir_node *fist, *load;
/* do a fist */
- fist = new_rd_ia32_vfist(dbgi, irg, block,
- get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
+ fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
+ new_NoMem(), new_op, trunc_mode);
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
ir_node *store, *load;
ir_node *res;
- store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
+ store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
/* first convert to 32 bit signed if necessary */
src_bits = get_mode_size_bits(src_mode);
if (src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
- src_mode);
+ new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
+ new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
mode = mode_Is;
} else if (src_bits < 32) {
- new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
+ new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
+ new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
mode = mode_Is;
}
assert(get_mode_size_bits(mode) == 32);
/* do a store */
- store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
+ store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
+ new_op);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
/* store a zero */
ir_node *zero_const = create_Immediate_from_int(0);
- ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
- zero_const, nomem);
+ ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
+ get_irg_frame(irg), noreg, nomem,
+ zero_const);
set_ia32_use_frame(zero_store);
set_ia32_op_type(zero_store, ia32_AddrModeD);
* Crete a conversion from one integer mode into another one
*/
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
- dbg_info *dbgi, ir_node *new_block,
- ir_node *new_op)
+ dbg_info *dbgi, ir_node *block, ir_node *op,
+ ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
+ ir_graph *irg = current_ir_graph;
+ int src_bits = get_mode_size_bits(src_mode);
+ int tgt_bits = get_mode_size_bits(tgt_mode);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *new_op;
ir_node *res;
ir_mode *smaller_mode;
int smaller_bits;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
if (src_bits < tgt_bits) {
smaller_mode = src_mode;
smaller_bits = tgt_bits;
}
+ memset(&am, 0, sizeof(am));
+ if(use_source_address_mode(block, op, NULL)) {
+ build_address(&am, op);
+ new_op = noreg;
+ am.op_type = ia32_AddrModeS;
+ } else {
+ new_op = be_transform_node(op);
+ am.op_type = ia32_Normal;
+ }
+ if(addr->base == NULL)
+ addr->base = noreg;
+ if(addr->index == NULL)
+ addr->index = noreg;
+ if(addr->mem == NULL)
+ addr->mem = new_NoMem();
+
DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
if (smaller_bits == 8) {
- res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
- new_op, nomem, smaller_mode);
+ res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, new_op,
+ smaller_mode);
} else {
- res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
- nomem, smaller_mode);
+ res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, new_op,
+ smaller_mode);
}
+ set_am_attributes(res, &am);
+ set_ia32_ls_mode(res, smaller_mode);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ res = fix_mem_proj(res, &am);
+
return res;
}
* @return The created ia32 Conv node
*/
static ir_node *gen_Conv(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = get_Conv_op(node);
- ir_node *new_op = be_transform_node(op);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *src_mode = get_irn_mode(op);
- ir_mode *tgt_mode = get_irn_mode(node);
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
- ir_node *res;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *op = get_Conv_op(node);
+ ir_node *new_op = NULL;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *src_mode = get_irn_mode(op);
+ ir_mode *tgt_mode = get_irn_mode(node);
+ int src_bits = get_mode_size_bits(src_mode);
+ int tgt_bits = get_mode_size_bits(tgt_mode);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *res = NULL;
if (src_mode == mode_b) {
assert(mode_is_int(tgt_mode));
/* nothing to do, we already model bools as 0/1 ints */
- return new_op;
+ return be_transform_node(op);
}
if (src_mode == tgt_mode) {
if (get_Conv_strict(node)) {
if (USE_SSE2(env_cg)) {
/* when we are in SSE mode, we can kill all strict no-op conversion */
- return new_op;
+ return be_transform_node(op);
}
} else {
/* this should be optimized already, but who knows... */
DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
- return new_op;
+ return be_transform_node(op);
}
}
if (mode_is_float(src_mode)) {
+ new_op = be_transform_node(op);
/* we convert from float ... */
if (mode_is_float(tgt_mode)) {
if(src_mode == mode_E && tgt_mode == mode_D
/* ... to float */
if (USE_SSE2(env_cg)) {
DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
- res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
if(get_Conv_strict(node)) {
/* ... to int */
DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_op);
set_ia32_ls_mode(res, src_mode);
} else {
return gen_x87_fp_to_gp(node);
/* ... to float */
DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ new_op = be_transform_node(op);
+ res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
res = gen_x87_gp_to_fp(node, src_mode);
/* mode_b lowering already took care that we only have 0/1 values */
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
- return new_op;
+ return be_transform_node(op);
} else {
/* to int */
if (src_bits == tgt_bits) {
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
- return new_op;
+ return be_transform_node(op);
}
- res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
+ res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
+ return res;
}
}
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
-
return res;
}
-static
-int check_immediate_constraint(long val, char immediate_constraint_type)
+static int check_immediate_constraint(long val, char immediate_constraint_type)
{
switch (immediate_constraint_type) {
case 0:
return 0;
}
-static
-ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
+static ir_node *try_create_Immediate(ir_node *node,
+ char immediate_constraint_type)
{
int minus = 0;
tarval *offset = NULL;
offset = get_Const_tarval(cnst);
if(tarval_is_long(offset)) {
val = get_tarval_long(offset);
- } else if(tarval_is_null(offset)) {
- val = 0;
} else {
ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
"long?\n", cnst);
return NULL;
}
+ /* unfortunately the assembler/linker doesn't support -symconst */
+ if(symconst_sign)
+ return NULL;
+
if(get_SymConst_kind(symconst) != symconst_addr_ent)
return NULL;
symconst_ent = get_SymConst_entity(symconst);
return res;
}
-static
-ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
+static ir_node *create_immediate_or_transform(ir_node *node,
+ char immediate_constraint_type)
{
ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
if (new_node == NULL) {
constraint->immediate_type = immediate_type;
}
-static
-void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
- const char *c)
+static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
+ const char *c)
{
(void) node;
(void) pos;
/* store xmm0 onto stack */
sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
- new_ret_val, new_ret_mem);
+ new_ret_mem, new_ret_val);
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
new_sz = create_immediate_or_transform(sz, 0);
/* ia32 stack grows in reverse direction, make a SubSP */
- new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
- nomem);
+ new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
+ new_sz);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
return new_op;
new_sz = create_immediate_or_transform(sz, 0);
/* ia32 stack grows in reverse direction, make an AddSP */
- new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
+ new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, nomem, new_sp,
+ new_sz);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
return new_op;
get_irn_n(node, 1), new_rd_ia32_##op); \
}
-GEN_LOWERED_OP(Adc)
-GEN_LOWERED_OP(Add)
-GEN_LOWERED_OP(Sbb)
-GEN_LOWERED_OP(Sub)
-GEN_LOWERED_OP(Xor)
GEN_LOWERED_x87_OP(vfprem)
GEN_LOWERED_x87_OP(vfmul)
GEN_LOWERED_x87_OP(vfsub)
GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
+static ir_node *gen_ia32_l_Add(ir_node *node) {
+ ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
+ ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
+ ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add, 1);
+
+ if(is_Proj(lowered)) {
+ lowered = get_Proj_pred(lowered);
+ } else {
+ assert(is_ia32_Add(lowered));
+ set_irn_mode(lowered, mode_T);
+ }
+
+ return lowered;
+}
+
+static ir_node *gen_ia32_l_Adc(ir_node *node) {
+ ir_node *src_block = get_nodes_block(node);
+ ir_node *block = be_transform_node(src_block);
+ ir_node *op1 = get_irn_n(node, n_ia32_l_Adc_left);
+ ir_node *op2 = get_irn_n(node, n_ia32_l_Adc_right);
+ ir_node *flags = get_irn_n(node, n_ia32_l_Adc_eflags);
+ ir_node *new_flags = be_transform_node(flags);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+
+ match_arguments(&am, src_block, op1, op2, match_commutative);
+
+ new_node = new_rd_ia32_Adc(dbgi, irg, block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, new_flags);
+ set_am_attributes(new_node, &am);
+ /* we can't use source address mode anymore when using immediates */
+ if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
+ set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ new_node = fix_mem_proj(new_node, &am);
+
+ return new_node;
+}
/**
* Transforms an ia32_l_Neg into a "real" ia32_Neg node
ir_node *new_op;
long am_offs;
- new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val,
- trunc_mode, new_mem);
+ new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
+ new_val, trunc_mode);
am_offs = get_ia32_am_offs_int(node);
add_ia32_am_offs_int(new_op, am_offs);
ir_node *fpcw = get_fpcw();
ir_node *vfdiv;
- vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
- new_right, new_NoMem(), fpcw);
+ vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_NoMem(),
+ new_left, new_right, fpcw);
clear_ia32_commutative(vfdiv);
SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
/* l_Mul is already a mode_T node, so we create the Mul in the normal way */
/* and then skip the result Proj, because all needed Projs are already there. */
- ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
- new_right, new_NoMem());
+ ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_NoMem(),
+ new_left, new_right);
clear_ia32_commutative(muls);
SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
/* l_IMul is already a mode_T node, so we create the IMul1OP in the normal way */
/* and then skip the result Proj, because all needed Projs are already there. */
- ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_left,
- new_right, new_NoMem());
+ ir_node *muls = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg,
+ new_NoMem(), new_left, new_right);
clear_ia32_commutative(muls);
- set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
return new_op;
}
+static ir_node *gen_ia32_Sub64Bit(ir_node *node)
+{
+ ir_node *a_l = be_transform_node(get_irn_n(node, 0));
+ ir_node *a_h = be_transform_node(get_irn_n(node, 1));
+ ir_node *b_l = create_immediate_or_transform(get_irn_n(node, 2), 0);
+ ir_node *b_h = create_immediate_or_transform(get_irn_n(node, 3), 0);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_graph *irg = current_ir_graph;
+ ir_node *new_op = new_rd_ia32_Sub64Bit(dbgi, irg, block, a_l, a_h, b_l, b_h);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ return new_op;
+}
+
/**
* Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
* op1 - target to be shifted
dbgi = get_irn_dbg_info(node);
/* Store x87 -> MEM */
- res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
+ res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
+ get_ia32_ls_mode(node));
set_ia32_frame_ent(res, get_ia32_frame_ent(node));
set_ia32_use_frame(res);
set_ia32_ls_mode(res, get_ia32_ls_mode(node));
ptr = get_irn_n(ld, 0);
offs = get_ia32_am_offs_int(ld);
} else {
- res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
+ new_val);
set_ia32_frame_ent(res, fent);
set_ia32_use_frame(res);
set_ia32_ls_mode(res, lsmode);
} else if(is_ia32_Conv_I2I(new_pred)) {
set_irn_mode(new_pred, mode_T);
if (proj == pn_Load_res) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
}
} else if (is_ia32_xLoad(new_pred)) {
if (proj == pn_Load_res) {
return res;
}
+static ir_node *gen_be_Call(ir_node *node) {
+ ir_node *res = be_duplicate_node(node);
+ be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
+
+ return res;
+}
+
+static ir_node *gen_be_IncSP(ir_node *node) {
+ ir_node *res = be_duplicate_node(node);
+ be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
+
+ return res;
+}
+
/**
* Transform the Projs from a be_Call.
*/
pn_be_Call_first_res);
/* store st(0) onto stack */
- fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_res,
- call_mem, mode);
+ fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
+ call_res, mode);
set_ia32_op_type(fstp, ia32_AddrModeD);
set_ia32_use_frame(fstp);
{
/* normally Cmps are processed when looking at Cond nodes, but this case
* can happen in complicated Psi conditions */
-
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
ir_node *cmp = get_Proj_pred(node);
+ ir_node *new_cmp = be_transform_node(cmp);
long pnc = get_Proj_proj(node);
- ir_node *cmp_left = get_Cmp_left(cmp);
- ir_node *cmp_right = get_Cmp_right(cmp);
- ir_mode *cmp_mode = get_irn_mode(cmp_left);
- dbg_info *dbgi = get_irn_dbg_info(cmp);
- ir_node *block = get_nodes_block(node);
ir_node *res;
- int use_am;
-
- assert(!mode_is_float(cmp_mode));
-
- if(!mode_is_signed(cmp_mode)) {
- pnc |= ia32_pn_Cmp_Unsigned;
- }
-
- /**
- * address mode makes only sense when we'll be the only node using the cmp
- */
- use_am = get_irn_n_edges(cmp) <= 1;
- res = create_set(pnc, cmp_left, cmp_right, dbgi, block, use_am);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
+ res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node);
return res;
}
GEN(Store);
GEN(Cond);
+ GEN(Cmp);
GEN(ASM);
GEN(CopyB);
BAD(Mux);
/* transform ops from intrinsic lowering */
GEN(ia32_Add64Bit);
+ GEN(ia32_Sub64Bit);
GEN(ia32_l_Add);
GEN(ia32_l_Adc);
- GEN(ia32_l_Sub);
- GEN(ia32_l_Sbb);
GEN(ia32_l_Neg);
GEN(ia32_l_Mul);
GEN(ia32_l_IMul);
- GEN(ia32_l_Xor);
GEN(ia32_l_ShlDep);
GEN(ia32_l_ShrDep);
GEN(ia32_l_Sar);
/* handle generic backend nodes */
GEN(be_FrameAddr);
- //GEN(be_Call);
+ GEN(be_Call);
+ GEN(be_IncSP);
GEN(be_Return);
GEN(be_AddSP);
GEN(be_SubSP);
* Walker, checks if all ia32 nodes producing more than one result have
* its Projs, other wise creates new projs and keep them using a be_Keep node.
*/
-static
-void add_missing_keep_walker(ir_node *node, void *data)
+static void add_missing_keep_walker(ir_node *node, void *data)
{
int n_outs, i;
unsigned found_projs = 0;
if(class == NULL) {
continue;
}
+ if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
+ continue;
+ }
block = get_nodes_block(node);
in[0] = new_r_Proj(current_ir_graph, block, node,
be_Keep_add_node(last_keep, class, in[0]);
} else {
last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
+ if(sched_is_scheduled(node)) {
+ sched_add_after(node, last_keep);
+ }
}
}
}
* Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
* and keeps them.
*/
-static
-void add_missing_keeps(ia32_code_gen_t *cg)
+void ia32_add_missing_keeps(ia32_code_gen_t *cg)
{
ir_graph *irg = be_get_birg_irg(cg->birg);
irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
heights_free(heights);
heights = NULL;
- add_missing_keeps(cg);
}
void ia32_init_transform(void)
projects / libfirm / blobdiff