* input here, for unary operations use NULL).
*/
static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
- ir_node *other, ir_node *other2)
+ ir_node *other, ir_node *other2, match_flags_t flags)
{
ir_node *load;
long pn;
if (get_nodes_block(load) != block)
return 0;
/* we only use address mode if we're the only user of the load */
- if (get_irn_n_edges(node) > 1)
+ if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
return 0;
/* in some edge cases with address mode we might reach the load normally
* and through some AM sequence, if it is already materialized then we
noreg_gp = ia32_new_NoReg_gp(env_cg);
if (new_op2 == NULL &&
- use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
+ use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
build_address(am, op2);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (mode_is_float(mode)) {
am->op_type = ia32_AddrModeS;
} else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
use_am &&
- ia32_use_source_address_mode(block, op1, op2, other_op)) {
+ ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
ir_node *noreg;
build_address(am, op1);
/**
* Construct a standard binary operation, set AM and immediate if required.
*
+ * @param node The original node for which the binop is created
* @param op1 The first operand
* @param op2 The second operand
* @param func The node constructor function
return res;
}
}
-
return gen_binop(node, op1, op2, new_rd_ia32_And,
match_commutative | match_mode_neutral | match_am
| match_immediate);
add_irn_dep(produceval, get_irg_frame(irg));
sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
produceval);
+
+ new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
+ addr->index, new_mem, am.new_op2,
+ am.new_op1, sign_extension);
} else {
sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
add_irn_dep(sign_extension, get_irg_frame(irg));
+ new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
+ addr->index, new_mem, am.new_op2,
+ am.new_op1, sign_extension);
}
- new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
- addr->index, new_mem, am.new_op2,
- am.new_op1, sign_extension);
+
set_irn_pinned(new_node, get_irn_pinned(node));
set_am_attributes(new_node, &am);
return new_node;
}
+/**
+ * Create a bt instruction for x & (1 << n) and place it into the block of cmp.
+ */
+static ir_node *gen_bt(ir_node *cmp, ir_node *x, ir_node *n) {
+ dbg_info *dbgi = get_irn_dbg_info(cmp);
+ ir_node *block = get_nodes_block(cmp);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *op1 = be_transform_node(x);
+ ir_node *op2 = be_transform_node(n);
+
+ return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2);
+}
+
+/**
+ * Transform a node returning a "flag" result.
+ *
+ * @param node the node to transform
+ * @param pnc_out the compare mode to use
+ */
static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
{
- ir_graph *irg = current_ir_graph;
ir_node *flags;
ir_node *new_op;
ir_node *noreg;
dbg_info *dbgi;
/* we have a Cmp as input */
- if(is_Proj(node)) {
+ if (is_Proj(node)) {
ir_node *pred = get_Proj_pred(node);
- if(is_Cmp(pred)) {
+ if (is_Cmp(pred)) {
+ pn_Cmp pnc = get_Proj_proj(node);
+ if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
+ ir_node *l = get_Cmp_left(pred);
+ ir_node *r = get_Cmp_right(pred);
+ if (is_And(l)) {
+ ir_node *la = get_And_left(l);
+ ir_node *ra = get_And_right(l);
+ if (is_Shl(la)) {
+ ir_node *c = get_Shl_left(la);
+ if (is_Const_1(c) && (is_Const_0(r) || r == la)) {
+ /* (1 << n) & ra) */
+ ir_node *n = get_Shl_right(la);
+ flags = gen_bt(pred, ra, n);
+ /* we must generate a Jc/Jnc jump */
+ pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
+ if (r == la)
+ pnc ^= pn_Cmp_Leg;
+ *pnc_out = ia32_pn_Cmp_unsigned | pnc;
+ return flags;
+ }
+ }
+ if (is_Shl(ra)) {
+ ir_node *c = get_Shl_left(ra);
+ if (is_Const_1(c) && (is_Const_0(r) || r == ra)) {
+ /* la & (1 << n)) */
+ ir_node *n = get_Shl_right(ra);
+ flags = gen_bt(pred, la, n);
+ /* we must generate a Jc/Jnc jump */
+ pnc = pnc == pn_Cmp_Lg ? pn_Cmp_Lt : pn_Cmp_Ge;
+ if (r == ra)
+ pnc ^= pn_Cmp_Leg;
+ *pnc_out = ia32_pn_Cmp_unsigned | pnc;
+ return flags;
+ }
+ }
+ }
+ }
flags = be_transform_node(pred);
- *pnc_out = get_Proj_proj(node);
+ *pnc_out = pnc;
return flags;
}
}
new_op = be_transform_node(node);
noreg = ia32_new_NoReg_gp(env_cg);
nomem = new_NoMem();
- flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
- new_op, new_op, 0, 0);
+ flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem,
+ new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
*pnc_out = pn_Cmp_Lg;
return flags;
}
return new_node;
}
+/**
+ * Generate a vfist or vfisttp instruction.
+ */
+static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index,
+ ir_node *mem, ir_node *val, ir_node **fist)
+{
+ ir_node *new_node;
+
+ if (ia32_cg_config.use_fisttp) {
+ /* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
+ if other users exists */
+ const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp];
+ ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val);
+ ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res);
+ be_new_Keep(reg_class, irg, block, 1, &value);
+
+ new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M);
+ *fist = vfisttp;
+ } else {
+ ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
+
+ /* do a fist */
+ new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode);
+ *fist = new_node;
+ }
+ return new_node;
+}
/**
* Transforms a normal Store.
*
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *new_val;
- ir_node *new_node;
+ ir_node *new_val, *new_node, *store;
ia32_address_t addr;
/* check for destination address mode */
new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
+ store = new_node;
} else if (is_float_to_int32_conv(val)) {
- ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
val = get_Conv_op(val);
/* convs (and strict-convs) before stores are unnecessary if the mode
while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
val = get_Conv_op(val);
}
- new_val = be_transform_node(val);
-
- new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
- addr.index, addr.mem, new_val, trunc_mode);
+ new_val = be_transform_node(val);
+ new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store);
} else {
new_val = create_immediate_or_transform(val, 0);
assert(mode != mode_b);
new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
addr.index, addr.mem, new_val);
}
+ store = new_node;
}
- set_irn_pinned(new_node, get_irn_pinned(node));
- set_ia32_op_type(new_node, ia32_AddrModeD);
- set_ia32_ls_mode(new_node, mode);
+ set_irn_pinned(store, get_irn_pinned(node));
+ set_ia32_op_type(store, ia32_AddrModeD);
+ set_ia32_ls_mode(store, mode);
- set_address(new_node, &addr);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ set_address(store, &addr);
+ SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
return new_node;
}
return create_Switch(node);
}
- /* we get flags from a cmp */
+ /* we get flags from a Cmp */
flags = get_flags_node(sel, &pnc);
new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
return 1;
}
+/**
+ * Generate code for a Cmp.
+ */
static ir_node *gen_Cmp(ir_node *node)
{
ir_graph *irg = current_ir_graph;
return new_node;
}
-
-
+/**
+ * Creates a ia32 Setcc instruction.
+ */
static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
int ins_permuted)
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
/* we might need to conv the result up */
- if(get_mode_size_bits(mode) > 8) {
+ if (get_mode_size_bits(mode) > 8) {
new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
return new_node;
}
+/**
+ * Create instruction for an unsigned Difference or Zero.
+ */
+static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) {
+ ir_graph *irg = current_ir_graph;
+ ir_mode *mode = get_irn_mode(psi);
+ ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem;
+ dbg_info *dbgi;
+
+ new_node = gen_binop(psi, a, b, new_rd_ia32_Sub,
+ match_mode_neutral | match_am | match_immediate | match_two_users);
+
+ block = get_nodes_block(new_node);
+
+ if (is_Proj(new_node)) {
+ sub = get_Proj_pred(new_node);
+ assert(is_ia32_Sub(sub));
+ } else {
+ sub = new_node;
+ set_irn_mode(sub, mode_T);
+ new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res);
+ }
+ eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
+
+ dbgi = get_irn_dbg_info(psi);
+ noreg = ia32_new_NoReg_gp(env_cg);
+ tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ nomem = new_NoMem();
+ sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags);
+
+ new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb);
+ set_ia32_commutative(new_node);
+ return new_node;
+}
+
/**
* Transforms a Psi node into CMov.
*
ir_node *psi_true = get_Psi_val(node, 0);
ir_node *psi_default = get_Psi_default(node);
ir_node *cond = get_Psi_cond(node, 0);
- ir_node *flags = NULL;
- ir_node *new_node;
- pn_Cmp pnc;
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *cmp = get_Proj_pred(cond);
+ ir_node *cmp_left = get_Cmp_left(cmp);
+ ir_node *cmp_right = get_Cmp_right(cmp);
+ pn_Cmp pnc = get_Proj_proj(cond);
assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
- assert(mode_needs_gp_reg(get_irn_mode(node)));
- flags = get_flags_node(cond, &pnc);
+ /* Note: a Psi node uses a Load two times IFF it's used in the compare AND in the result */
+ if (mode_is_float(mode)) {
+ if (ia32_cg_config.use_sse2) {
+ if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
+ if (cmp_left == psi_true && cmp_right == psi_default) {
+ /* psi(a <= b, a, b) => MIN */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
+ match_commutative | match_am | match_two_users);
+ } else if (cmp_left == psi_default && cmp_right == psi_true) {
+ /* psi(a <= b, b, a) => MAX */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
+ match_commutative | match_am | match_two_users);
+ }
+ } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
+ if (cmp_left == psi_true && cmp_right == psi_default) {
+ /* psi(a >= b, a, b) => MAX */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
+ match_commutative | match_am | match_two_users);
+ } else if (cmp_left == psi_default && cmp_right == psi_true) {
+ /* psi(a >= b, b, a) => MIN */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
+ match_commutative | match_am | match_two_users);
+ }
+ }
+ }
+ panic("cannot transform floating point Psi");
- if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
- } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
} else {
- new_node = create_CMov(node, cond, flags, pnc);
+ ir_node *flags;
+ ir_node *new_node;
+
+ assert(mode_needs_gp_reg(mode));
+
+ /* check for unsigned Doz first */
+ if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
+ is_Const_0(psi_default) && is_Sub(psi_true) &&
+ get_Sub_left(psi_true) == cmp_left && get_Sub_right(psi_true) == cmp_right) {
+ /* Psi(a >=u b, a - b, 0) unsigned Doz */
+ return create_Doz(node, cmp_left, cmp_right);
+ } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
+ is_Const_0(psi_true) && is_Sub(psi_default) &&
+ get_Sub_left(psi_default) == cmp_left && get_Sub_right(psi_default) == cmp_right) {
+ /* Psi(a <=u b, 0, a - b) unsigned Doz */
+ return create_Doz(node, cmp_left, cmp_right);
+ }
+
+ flags = get_flags_node(cond, &pnc);
+
+ if (is_Const(psi_true) && is_Const(psi_default)) {
+ /* both are const, good */
+ if (is_Const_1(psi_true) && is_Const_0(psi_default)) {
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0);
+ } else if (is_Const_0(psi_true) && is_Const_1(psi_default)) {
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1);
+ } else {
+ /* Not that simple. */
+ goto need_cmov;
+ }
+ } else {
+need_cmov:
+ new_node = create_CMov(node, cond, flags, pnc);
+ }
+ return new_node;
}
- return new_node;
}
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
- ir_node *trunc_mode = ia32_new_Fpu_truncate(cg);
ir_mode *mode = get_irn_mode(node);
- ir_node *fist, *load;
-
- /* do a fist */
- fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
- new_NoMem(), new_op, trunc_mode);
+ ir_node *fist, *load, *mem;
+ mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist);
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
/* do a Load */
- load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
+ load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem);
set_irn_pinned(load, op_pin_state_floats);
set_ia32_use_frame(load);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_mode *mode = get_ia32_ls_mode(node);
- ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
- ir_node *new_op;
+ ir_node *memres, *fist;
long am_offs;
- new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
- new_val, trunc_mode);
-
+ memres = gen_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, new_val, &fist);
am_offs = get_ia32_am_offs_int(node);
- add_ia32_am_offs_int(new_op, am_offs);
+ add_ia32_am_offs_int(fist, am_offs);
- set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_ls_mode(new_op, mode);
- set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
- set_ia32_use_frame(new_op);
+ set_ia32_op_type(fist, ia32_AddrModeD);
+ set_ia32_ls_mode(fist, mode);
+ set_ia32_frame_ent(fist, get_ia32_frame_ent(node));
+ set_ia32_use_frame(fist);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
- return new_op;
+ return memres;
}
/**
ir_node *nomem = new_NoMem();
ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
ir_node *new_val = be_transform_node(val);
- ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
-
- ir_node *fist;
+ ir_node *fist, *mem;
- /* do a fist */
- fist = new_rd_ia32_vfist(dbgi, irg, block, frame, noreg, nomem, new_val,
- trunc_mode);
+ mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist);
SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
- return fist;
+ return mem;
}
/**
projects / libfirm / blobdiff