+/**
+ * This file implements the IR transformation from firm into
+ * ia32-Firm.
+ *
+ * $Id$
+ */
+
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
+#include "irargs_t.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "irmode_t.h"
+#include "iropt_t.h"
+#include "irop_t.h"
+#include "irprog_t.h"
+#include "iredges_t.h"
#include "irgmod.h"
-#include "iredges.h"
#include "irvrfy.h"
#include "ircons.h"
#include "dbginfo.h"
-#include "iropt_t.h"
#include "debug.h"
#include "../benode_t.h"
+#include "../besched.h"
+
#include "bearch_ia32_t.h"
#include "ia32_nodes_attr.h"
#include "../arch/archop.h" /* we need this for Min and Max nodes */
#include "ia32_transform.h"
#include "ia32_new_nodes.h"
+#include "ia32_map_regs.h"
#include "gen_ia32_regalloc_if.h"
+#ifdef NDEBUG
+#define SET_IA32_ORIG_NODE(n, o)
+#else
+#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
+#endif /* NDEBUG */
+
+
#define SFP_SIGN "0x80000000"
#define DFP_SIGN "0x8000000000000000"
#define SFP_ABS "0x7FFFFFFF"
return ent_name;
}
-
-#undef is_cnst
-#define is_cnst(op) (is_ia32_Const(op) || is_ia32_fConst(op))
+#ifndef NDEBUG
+/**
+ * Prints the old node name on cg obst and returns a pointer to it.
+ */
+const char *get_old_node_name(ia32_transform_env_t *env) {
+ static int name_cnt = 0;
+ ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
+
+ lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
+ obstack_1grow(isa->name_obst, 0);
+ isa->name_obst_size += obstack_object_size(isa->name_obst);
+ name_cnt++;
+ if (name_cnt % 1024 == 0) {
+ printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
+ }
+ return obstack_finish(isa->name_obst);
+}
+#endif /* NDEBUG */
/* determine if one operator is an Imm */
static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
if (op1)
- return is_cnst(op1) ? op1 : (is_cnst(op2) ? op2 : NULL);
- else return is_cnst(op2) ? op2 : NULL;
+ return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
+ else return is_ia32_Cnst(op2) ? op2 : NULL;
}
/* determine if one operator is not an Imm */
static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
- return !is_cnst(op1) ? op1 : (!is_cnst(op2) ? op2 : NULL);
+ return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
}
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
-
- /* check if it's an operation with immediate */
- if (is_op_commutative(get_irn_op(env->irn))) {
+ /* Check if immediate optimization is on and */
+ /* if it's an operation with immediate. */
+ if (! env->cg->opt.immops) {
+ expr_op = op1;
+ imm_op = NULL;
+ }
+ else if (is_op_commutative(get_irn_op(env->irn))) {
imm_op = get_immediate_op(op1, op2);
expr_op = get_expr_op(op1, op2);
}
if (mode_is_float(mode)) {
/* floating point operations */
if (imm_op) {
+ DB((mod, LEVEL_1, "FP with immediate ..."));
new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_fp, nomem, mode_T);
set_ia32_Immop_attr(new_op, imm_op);
set_ia32_am_support(new_op, ia32_am_None);
}
else {
+ DB((mod, LEVEL_1, "FP binop ..."));
new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
set_ia32_am_support(new_op, ia32_am_Source);
}
/* integer operations */
if (imm_op) {
/* This is expr + const */
+ DB((mod, LEVEL_1, "INT with immediate ..."));
new_op = func(dbg, irg, block, noreg_gp, noreg_gp, expr_op, noreg_gp, nomem, mode_T);
set_ia32_Immop_attr(new_op, imm_op);
set_ia32_am_support(new_op, ia32_am_Dest);
}
else {
+ DB((mod, LEVEL_1, "INT binop ..."));
/* This is a normal operation */
new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem, mode_T);
}
}
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ set_ia32_res_mode(new_op, mode);
+
+ if (is_op_commutative(get_irn_op(env->irn))) {
+ set_ia32_commutative(new_op);
+ }
+
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
- imm_op = get_immediate_op(NULL, op2);
+ /* Check if immediate optimization is on and */
+ /* if it's an operation with immediate. */
+ imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
expr_op = get_expr_op(op1, op2);
assert((expr_op || imm_op) && "invalid operands");
/* integer operations */
if (imm_op) {
/* This is shift/rot with const */
+ DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem, mode_T);
set_ia32_Immop_attr(new_op, imm_op);
}
else {
/* This is a normal shift/rot */
+ DB((mod, LEVEL_1, "Shift/Rot binop ..."));
new_op = func(dbg, irg, block, noreg, noreg, op1, op2, nomem, mode_T);
}
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Dest);
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ set_ia32_res_mode(new_op, mode);
+
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
ir_node *new_op = NULL;
ir_mode *mode = env->mode;
dbg_info *dbg = env->dbg;
+ firm_dbg_module_t *mod = env->mod;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
if (mode_is_float(mode)) {
+ DB((mod, LEVEL_1, "FP unop ..."));
/* floating point operations don't support implicit store */
set_ia32_am_support(new_op, ia32_am_None);
}
else {
+ DB((mod, LEVEL_1, "INT unop ..."));
set_ia32_am_support(new_op, ia32_am_Dest);
}
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ set_ia32_res_mode(new_op, mode);
+
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
tarval *tv = get_ia32_Immop_tarval(const_op);
firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
int normal_add = 1;
tarval_classification_t class_tv, class_negtv;
- /* const_op: tarval or SymConst? */
- if (tv) {
+ /* try to optimize to inc/dec */
+ if (env->cg->opt.incdec && tv) {
/* optimize tarvals */
class_tv = classify_tarval(tv);
class_negtv = classify_tarval(tarval_neg(tv));
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
- imm_op = get_immediate_op(op1, op2);
+ /* Check if immediate optimization is on and */
+ /* if it's an operation with immediate. */
+ imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
expr_op = get_expr_op(op1, op2);
assert((expr_op || imm_op) && "invalid operands");
}
}
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ set_ia32_res_mode(new_op, mode);
+
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
else {
new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
set_ia32_am_support(new_op, ia32_am_None);
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
}
return new_op;
else {
new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
set_ia32_am_support(new_op, ia32_am_None);
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
}
return new_op;
tarval *tv = get_ia32_Immop_tarval(const_op);
firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
- ir_mode *mode = env->mode;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
int normal_sub = 1;
tarval_classification_t class_tv, class_negtv;
- /* const_op: tarval or SymConst? */
- if (tv) {
+ /* try to optimize to inc/dec */
+ if (env->cg->opt.incdec && tv) {
/* optimize tarvals */
class_tv = classify_tarval(tv);
class_negtv = classify_tarval(tarval_neg(tv));
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
- imm_op = get_immediate_op(NULL, op2);
+ /* Check if immediate optimization is on and */
+ /* if it's an operation with immediate. */
+ imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
expr_op = get_expr_op(op1, op2);
assert((expr_op || imm_op) && "invalid operands");
}
}
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ set_ia32_res_mode(new_op, mode);
+
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
}
- res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode);
+ res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
set_ia32_flavour(res, dm_flav);
set_ia32_n_res(res, 2);
be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
}
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+
+ set_ia32_res_mode(res, mode_Is);
+
return res;
}
new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, env->mode);
set_ia32_am_support(new_op, ia32_am_Source);
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
return new_op;
}
-/**
- * Transforms a Conv node.
- *
- * @param env The transformation environment
- * @param op The operator
- * @return The created ia32 Conv node
- */
-static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
- return new_rd_ia32_Conv(env->dbg, env->irg, env->block, op, env->mode);
-}
-
-
-
/**
* Transforms a Minus node.
*
set_ia32_sc(new_op, name);
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ set_ia32_res_mode(new_op, env->mode);
+
new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
}
else {
set_ia32_sc(res, name);
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+
+ set_ia32_res_mode(res, mode);
+
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
}
else {
res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ set_ia32_res_mode(res, mode);
+
p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
+
res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ set_ia32_res_mode(res, mode);
+
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
+
res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ set_ia32_res_mode(res, mode);
+
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
}
}
set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, get_Load_mode(node));
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
return new_op;
}
static ir_node *gen_Store(ia32_transform_env_t *env) {
ir_node *node = env->irn;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *val = get_Store_value(node);
+ ir_node *ptr = get_Store_ptr(node);
+ ir_node *mem = get_Store_mem(node);
+ ir_node *sval = val;
ir_node *new_op;
+ /* in case of storing a const -> make it an attribute */
+ if (is_ia32_Cnst(val)) {
+ sval = noreg;
+ }
+
if (mode_is_float(env->mode)) {
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, get_Store_ptr(node), noreg, get_Store_value(node), get_Store_mem(node), env->mode);
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, get_Store_ptr(node), noreg, get_Store_value(node), get_Store_mem(node), env->mode);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
}
- set_ia32_am_support(new_op, ia32_am_Dest);
- set_ia32_ls_mode(new_op, get_irn_mode(get_Store_value(node)));
- return new_op;
-}
+ /* stored const is an attribute (saves a register) */
+ if (is_ia32_Cnst(val)) {
+ set_ia32_Immop_attr(new_op, val);
+ }
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, get_irn_mode(val));
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
-/**
- * Transforms a Call and its arguments corresponding to the calling convention.
- *
- * @param env The transformation environment
- * @return The created ia32 Call node
- */
-static ir_node *gen_Call(ia32_transform_env_t *env) {
+ return new_op;
}
cmp_b = get_Cmp_right(pred);
/* check if we can use a CondJmp with immediate */
- cnst = get_immediate_op(cmp_a, cmp_b);
+ cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
expr = get_expr_op(cmp_a, cmp_b);
if (cnst && expr) {
}
set_ia32_pncode(res, get_Proj_proj(sel));
+ set_ia32_am_support(res, ia32_am_Source);
}
else {
- res = new_rd_ia32_SwitchJmp(dbg, irg, block, noreg, noreg, sel, nomem, mode_T);
+ res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
set_ia32_pncode(res, get_Cond_defaultProj(node));
}
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+
return res;
}
ir_node *src = get_CopyB_src(node);
ir_node *dst = get_CopyB_dst(node);
ir_node *mem = get_CopyB_mem(node);
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
int size = get_type_size_bytes(get_CopyB_type(node));
int rem;
/* If we have to copy more than 16 bytes, we use REP MOVSx and */
/* then we need the size explicitly in ECX. */
- if (size >= 16) {
+ if (size >= 16 * 4) {
rem = size & 0x3; /* size % 4 */
size >>= 2;
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
}
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+
return res;
}
* @return The transformed node.
*/
static ir_node *gen_Mux(ia32_transform_env_t *env) {
- ir_node *node = env->irn;
-
- return new_rd_ia32_CMov(env->dbg, env->irg, env->block,
+ ir_node *node = env->irn;
+ ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
+
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ return new_op;
+}
+
+
+/**
+ * Following conversion rules apply:
+ *
+ * INT -> INT
+ * ============
+ * 1) n bit -> m bit n < m (upscale)
+ * always ignored
+ * 2) n bit -> m bit n == m (sign change)
+ * always ignored
+ * 3) n bit -> m bit n > m (downscale)
+ * a) Un -> Um = AND Un, (1 << m) - 1
+ * b) Sn -> Um same as a)
+ * c) Un -> Sm same as a)
+ * d) Sn -> Sm = ASHL Sn, (n - m); ASHR Sn, (n - m)
+ *
+ * INT -> FLOAT
+ * ==============
+ * SSE(1/2) convert to float or double (cvtsi2ss/sd)
+ *
+ * FLOAT -> INT
+ * ==============
+ * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
+ * if target mode < 32bit: additional INT -> INT conversion (see above)
+ *
+ * FLOAT -> FLOAT
+ * ================
+ * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
+ */
+
+static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
+ ir_mode *src_mode, ir_mode *tgt_mode)
+{
+ int n = get_mode_size_bits(src_mode);
+ int m = get_mode_size_bits(tgt_mode);
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *new_op, *proj;
+
+ assert(n > m && "downscale expected");
+
+ if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
+ /* ASHL Sn, n - m */
+ new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
+ proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
+ set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
+ set_ia32_am_support(new_op, ia32_am_Source);
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ /* ASHR Sn, n - m */
+ new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
+ set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
+ }
+ else {
+ new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
+ set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
+ }
+
+ return new_op;
+}
+
+/**
+ * Transforms a Conv node.
+ *
+ * @param env The transformation environment
+ * @param op The operator
+ * @return The created ia32 Conv node
+ */
+static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_mode *src_mode = get_irn_mode(op);
+ ir_mode *tgt_mode = env->mode;
+ ir_node *block = env->block;
+ ir_node *new_op = NULL;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ firm_dbg_module_t *mod = env->mod;
+ ir_node *proj;
+
+ if (src_mode == tgt_mode) {
+ /* this can happen when changing mode_P to mode_Is */
+ DB((mod, LEVEL_1, "killed Conv(mode, mode) ..."));
+ edges_reroute(env->irn, op, irg);
+ }
+ else if (mode_is_float(src_mode)) {
+ /* we convert from float ... */
+ if (mode_is_float(tgt_mode)) {
+ /* ... to float */
+ DB((mod, LEVEL_1, "create Conv(float, float) ..."));
+ new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ }
+ else {
+ /* ... to int */
+ DB((mod, LEVEL_1, "create Conv(float, int) ..."));
+ new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ /* if target mode is not int: add an additional downscale convert */
+ if (get_mode_size_bits(tgt_mode) < 32) {
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ set_ia32_res_mode(new_op, tgt_mode);
+ set_ia32_am_support(new_op, ia32_am_Source);
+
+ proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
+ new_op = gen_int_downscale_conv(env, proj, src_mode, tgt_mode);
+ }
+ }
+ }
+ else {
+ /* we convert from int ... */
+ if (mode_is_float(tgt_mode)) {
+ /* ... to float */
+ DB((mod, LEVEL_1, "create Conv(int, float) ..."));
+ new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ }
+ else {
+ /* ... to int */
+ if (get_mode_size_bits(src_mode) <= get_mode_size_bits(tgt_mode)) {
+ DB((mod, LEVEL_1, "omitting upscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
+ edges_reroute(env->irn, op, irg);
+ }
+ else {
+ DB((mod, LEVEL_1, "create downscale Conv(%+F, %+F) ...", src_mode, tgt_mode));
+ new_op = gen_int_downscale_conv(env, op, src_mode, tgt_mode);
+ }
+ }
+ }
+
+ if (new_op) {
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ set_ia32_res_mode(new_op, tgt_mode);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+
+ new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
+ }
+
+ return new_op;
+}
+
+
+
+/********************************************
+ * _ _
+ * | | | |
+ * | |__ ___ _ __ ___ __| | ___ ___
+ * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
+ * | |_) | __/ | | | (_) | (_| | __/\__ \
+ * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
+ *
+ ********************************************/
+
+static ir_node *gen_StackParam(ia32_transform_env_t *env) {
+ ir_node *new_op = NULL;
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *mem = new_rd_NoMem(env->irg);
+ ir_node *ptr = get_irn_n(node, 0);
+ entity *ent = be_get_frame_entity(node);
+ ir_mode *mode = env->mode;
+
+ if (mode_is_float(mode)) {
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
+ else {
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
+
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, mode);
+
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
+}
+
+/**
+ * Transforms a FrameAddr into an ia32 Add.
+ */
+static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
+ ir_node *new_op = NULL;
+ ir_node *node = env->irn;
+ ir_node *op = get_irn_n(node, 0);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+
+ new_op = new_rd_ia32_Add(env->dbg, env->irg, env->block, noreg, noreg, op, noreg, nomem, mode_T);
+ set_ia32_frame_ent(new_op, be_get_frame_entity(node));
+ set_ia32_am_support(new_op, ia32_am_Full);
+ set_ia32_use_frame(new_op);
+
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
+}
+
+/**
+ * Transforms a FrameLoad into an ia32 Load.
+ */
+static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
+ ir_node *new_op = NULL;
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *mem = get_irn_n(node, 0);
+ ir_node *ptr = get_irn_n(node, 1);
+ entity *ent = be_get_frame_entity(node);
+ ir_mode *mode = get_type_mode(get_entity_type(ent));
+
+ if (mode_is_float(mode)) {
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
+ else {
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
+
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, mode);
+
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ return new_op;
+}
+
+
+/**
+ * Transforms a FrameStore into an ia32 Store.
+ */
+static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
+ ir_node *new_op = NULL;
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *mem = get_irn_n(node, 0);
+ ir_node *ptr = get_irn_n(node, 1);
+ ir_node *val = get_irn_n(node, 2);
+ entity *ent = be_get_frame_entity(node);
+ ir_mode *mode = get_irn_mode(val);
+
+ if (mode_is_float(mode)) {
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ }
+ else {
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ }
+
+ set_ia32_frame_ent(new_op, ent);
+ set_ia32_use_frame(new_op);
+
+ set_ia32_am_support(new_op, ia32_am_Dest);
+ set_ia32_op_type(new_op, ia32_AddrModeD);
+ set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_ls_mode(new_op, mode);
+
+ SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+
+ return new_op;
}
*
*********************************************************/
+/**
+ * Transforms a Sub or fSub into Neg--Add iff OUT_REG == SRC2_REG.
+ * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
+ */
+void ia32_transform_sub_to_neg_add(ir_node *irn, ia32_code_gen_t *cg) {
+ ia32_transform_env_t tenv;
+ ir_node *in1, *in2, *noreg, *nomem, *res;
+ const arch_register_t *in1_reg, *in2_reg, *out_reg, **slots;
+
+ /* Return if AM node or not a Sub or fSub */
+ if (get_ia32_op_type(irn) != ia32_Normal || !(is_ia32_Sub(irn) || is_ia32_fSub(irn)))
+ return;
+
+ noreg = ia32_new_NoReg_gp(cg);
+ nomem = new_rd_NoMem(cg->irg);
+ in1 = get_irn_n(irn, 2);
+ in2 = get_irn_n(irn, 3);
+ in1_reg = arch_get_irn_register(cg->arch_env, in1);
+ in2_reg = arch_get_irn_register(cg->arch_env, in2);
+ out_reg = get_ia32_out_reg(irn, 0);
+
+ tenv.block = get_nodes_block(irn);
+ tenv.dbg = get_irn_dbg_info(irn);
+ tenv.irg = cg->irg;
+ tenv.irn = irn;
+ tenv.mod = cg->mod;
+ tenv.mode = get_ia32_res_mode(irn);
+ tenv.cg = cg;
+
+ /* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
+ if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
+ /* generate the neg src2 */
+ res = gen_Minus(&tenv, in2);
+ arch_set_irn_register(cg->arch_env, res, in2_reg);
+
+ /* add to schedule */
+ sched_add_before(irn, res);
+
+ /* generate the add */
+ if (mode_is_float(tenv.mode)) {
+ res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+ }
+ else {
+ res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+ }
+ SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
+ /* copy register */
+ slots = get_ia32_slots(res);
+ slots[0] = in2_reg;
+
+ /* add to schedule */
+ sched_add_before(irn, res);
+
+ /* remove the old sub */
+ sched_remove(irn);
+
+ /* exchange the add and the sub */
+ exchange(irn, res);
+ }
+}
/**
* Transforms the given firm node (and maybe some other related nodes)
#define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
#define IGN(a) case iro_##a: break
#define BAD(a) case iro_##a: goto bad
+#define OTHER_BIN(a) \
+ if (get_irn_op(node) == get_op_##a()) { \
+ asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
+ break; \
+ }
+#define BE_GEN(a) \
+ if (be_is_##a(node)) { \
+ asm_node = gen_##a(&tenv); \
+ break; \
+ }
DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
BINOP(Shl);
BINOP(Shr);
BINOP(Shrs);
+ BINOP(Rot);
BINOP(Quot);
IGN(Break);
IGN(Cmp);
IGN(Unknown);
+
/* constant transformation happens earlier */
IGN(Const);
IGN(SymConst);
BAD(EndExcept);
default:
- if (get_irn_op(node) == get_op_Max()) {
- asm_node = gen_Max(&tenv, get_irn_n(node, 0), get_irn_n(node, 1));
- }
- else if (get_irn_op(node) == get_op_Min()) {
- asm_node = gen_Min(&tenv, get_irn_n(node, 0), get_irn_n(node, 1));
- }
- else if (get_irn_op(node) == get_op_Mulh()) {
- asm_node = gen_Mulh(&tenv, get_irn_n(node, 0), get_irn_n(node, 1));
- }
+ OTHER_BIN(Max);
+ OTHER_BIN(Min);
+ OTHER_BIN(Mulh);
+
+ BE_GEN(FrameAddr);
+ BE_GEN(FrameLoad);
+ BE_GEN(FrameStore);
+ BE_GEN(StackParam);
break;
bad:
fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
assert(0);
}
+ /* exchange nodes if a new one was generated */
if (asm_node) {
exchange(node, asm_node);
DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
else {
DB((tenv.mod, LEVEL_1, "ignored\n"));
}
+
+#undef UNOP
+#undef BINOP
+#undef GEN
+#undef IGN
+#undef BAD
+#undef OTHER_BIN
+#undef BE_GEN
}
projects / libfirm / blobdiff