#include "../be_t.h"
#include "bearch_ia32_t.h"
+#include "ia32_common_transform.h"
#include "ia32_nodes_attr.h"
#include "ia32_transform.h"
#include "ia32_new_nodes.h"
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
-/** hold the current code generator during transformation */
-static ia32_code_gen_t *env_cg = NULL;
static ir_node *initial_fpcw = NULL;
-static heights_t *heights = NULL;
extern ir_op *get_op_Mulh(void);
typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
ir_node *block, ir_node *op);
-static ir_node *try_create_Immediate(ir_node *node,
- char immediate_constraint_type);
-
static ir_node *create_immediate_or_transform(ir_node *node,
char immediate_constraint_type);
dbg_info *dbgi, ir_node *block,
ir_node *op, ir_node *orig_node);
-/**
- * Return true if a mode can be stored in the GP register set
- */
-int ia32_mode_needs_gp_reg(ir_mode *mode) {
- if(mode == mode_fpcw)
- return 0;
- if(get_mode_size_bits(mode) > 32)
- return 0;
- return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
-}
-
-/**
- * creates a unique ident by adding a number to a tag
- *
- * @param tag the tag string, must contain a %d if a number
- * should be added
- */
-static ident *unique_id(const char *tag)
-{
- static unsigned id = 0;
- char str[256];
-
- snprintf(str, sizeof(str), tag, ++id);
- return new_id_from_str(str);
-}
-
-/**
- * Get a primitive type for a mode.
- */
-ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
-{
- pmap_entry *e = pmap_find(types, mode);
- ir_type *res;
-
- if (! e) {
- char buf[64];
- snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
- res = new_type_primitive(new_id_from_str(buf), mode);
- set_type_alignment_bytes(res, 16);
- pmap_insert(types, mode, res);
- }
- else
- res = e->value;
- return res;
-}
-
-/**
- * Creates an immediate.
- *
- * @param symconst if set, create a SymConst immediate
- * @param symconst_sign sign for the symconst
- * @param val integer value for the immediate
- */
-static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
-{
- ir_graph *irg = current_ir_graph;
- ir_node *start_block = get_irg_start_block(irg);
- ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
- symconst, symconst_sign, val);
- arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
-
- return immediate;
-}
-
-/**
- * Get an atomic entity that is initialized with a tarval forming
- * a given constant.
- *
- * @param cnst the node representing the constant
- */
-static ir_entity *create_float_const_entity(ir_node *cnst)
-{
- ia32_isa_t *isa = env_cg->isa;
- tarval *key = get_Const_tarval(cnst);
- pmap_entry *e = pmap_find(isa->tv_ent, key);
- ir_entity *res;
- ir_graph *rem;
-
- if (e == NULL) {
- tarval *tv = key;
- ir_mode *mode = get_tarval_mode(tv);
- ir_type *tp;
-
- if (! ia32_cg_config.use_sse2) {
- /* try to reduce the mode to produce smaller sized entities */
- if (mode != mode_F) {
- if (tarval_ieee754_can_conv_lossless(tv, mode_F)) {
- mode = mode_F;
- tv = tarval_convert_to(tv, mode);
- } else if (mode != mode_D) {
- if (tarval_ieee754_can_conv_lossless(tv, mode_D)) {
- mode = mode_D;
- tv = tarval_convert_to(tv, mode);
- }
- }
- }
- }
-
- if (mode == get_irn_mode(cnst)) {
- /* mode was not changed */
- tp = get_Const_type(cnst);
- if (tp == firm_unknown_type)
- tp = ia32_get_prim_type(isa->types, mode);
- } else
- tp = ia32_get_prim_type(isa->types, mode);
-
- res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
-
- set_entity_ld_ident(res, get_entity_ident(res));
- set_entity_visibility(res, visibility_local);
- set_entity_variability(res, variability_constant);
- set_entity_allocation(res, allocation_static);
-
- /* we create a new entity here: It's initialization must resist on the
- const code irg */
- rem = current_ir_graph;
- current_ir_graph = get_const_code_irg();
- set_atomic_ent_value(res, new_Const_type(tv, tp));
- current_ir_graph = rem;
-
- pmap_insert(isa->tv_ent, key, res);
- } else {
- res = e->value;
- }
-
- return res;
-}
-
/** Return non-zero is a node represents the 0 constant. */
static int is_Const_0(ir_node *node) {
return is_Const(node) && is_Const_null(node);
return ent_cache[kct];
}
-#ifndef NDEBUG
-/**
- * Prints the old node name on cg obst and returns a pointer to it.
- */
-const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
- ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
-
- lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
- obstack_1grow(isa->name_obst, 0);
- return obstack_finish(isa->name_obst);
-}
-#endif /* NDEBUG */
-
/**
* return true if the node is a Proj(Load) and could be used in source address
* mode for another node. Will return only true if the @p other node is not
static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
ir_mode *mode = get_irn_mode(node);
- ir_node *psi_true = get_Psi_val(node, 0);
- ir_node *psi_default = get_Psi_default(node);
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
ir_graph *irg;
ir_node *cond;
ir_node *new_mem;
if(get_mode_size_bits(mode) != 8)
return NULL;
- if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
+ if(is_Const_1(mux_true) && is_Const_0(mux_false)) {
negated = 0;
- } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
+ } else if(is_Const_0(mux_true) && is_Const_1(mux_false)) {
negated = 1;
} else {
return NULL;
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
new_block = be_transform_node(block);
- cond = get_Psi_cond(node, 0);
+ cond = get_Mux_sel(node);
flags = get_flags_node(cond, &pnc);
new_mem = be_transform_node(mem);
new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
match_dest_am | match_immediate);
break;
/* TODO: match ROR patterns... */
- case iro_Psi:
+ case iro_Mux:
new_node = try_create_SetMem(val, ptr, mem);
break;
case iro_Minus:
} else if (!ia32_cg_config.use_sse2 && is_float_to_int32_conv(val)) {
val = get_Conv_op(val);
- /* We can skip ALL Convs (and strict-Convs) before stores. */
+ /* TODO: is this optimisation still necessary at all (middleend)? */
+ /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
while (is_Conv(val)) {
- val = get_Conv_op(val);
+ ir_node *op = get_Conv_op(val);
+ if (!mode_is_float(get_irn_mode(op)))
+ break;
+ if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
+ break;
+ val = op;
}
new_val = be_transform_node(val);
new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store);
assert(ia32_mode_needs_gp_reg(cmp_mode));
- /* we prefer the Test instruction where possible except cases where
- * we can use SourceAM */
+ /* Prefer the Test instruction, when encountering (x & y) ==/!= 0 */
cmp_unsigned = !mode_is_signed(cmp_mode);
- if (is_Const_0(right)) {
- if (is_And(left) &&
- get_irn_n_edges(left) == 1 &&
- can_fold_test_and(node)) {
- /* Test(and_left, and_right) */
- ir_node *and_left = get_And_left(left);
- ir_node *and_right = get_And_right(left);
- ir_mode *mode = get_irn_mode(and_left);
-
- match_arguments(&am, block, and_left, and_right, NULL,
- match_commutative |
- match_am | match_8bit_am | match_16bit_am |
- match_am_and_immediates | match_immediate |
- match_8bit | match_16bit);
- if (get_mode_size_bits(mode) == 8) {
- new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted,
- cmp_unsigned);
- } else {
- new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted, cmp_unsigned);
- }
+ if (is_Const_0(right) &&
+ is_And(left) &&
+ get_irn_n_edges(left) == 1 &&
+ can_fold_test_and(node)) {
+ /* Test(and_left, and_right) */
+ ir_node *and_left = get_And_left(left);
+ ir_node *and_right = get_And_right(left);
+ ir_mode *mode = get_irn_mode(and_left);
+
+ match_arguments(&am, block, and_left, and_right, NULL,
+ match_commutative |
+ match_am | match_8bit_am | match_16bit_am |
+ match_am_and_immediates | match_immediate |
+ match_8bit | match_16bit);
+ if (get_mode_size_bits(mode) == 8) {
+ new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.ins_permuted,
+ cmp_unsigned);
} else {
- match_arguments(&am, block, NULL, left, NULL,
- match_am | match_8bit_am | match_16bit_am |
- match_8bit | match_16bit);
- if (am.op_type == ia32_AddrModeS) {
- /* Cmp(AM, 0) */
- ir_node *imm_zero = try_create_Immediate(right, 0);
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op2,
- imm_zero, am.ins_permuted,
- cmp_unsigned);
- } else {
- new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op2,
- imm_zero, am.ins_permuted, cmp_unsigned);
- }
- } else {
- /* Test(left, left) */
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op2,
- am.new_op2, am.ins_permuted,
- cmp_unsigned);
- } else {
- new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op2,
- am.new_op2, am.ins_permuted,
- cmp_unsigned);
- }
- }
+ new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.ins_permuted, cmp_unsigned);
}
} else {
/* Cmp(left, right) */
}
}
set_am_attributes(new_node, &am);
- assert(cmp_mode != NULL);
set_ia32_ls_mode(new_node, cmp_mode);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_node *val_true = get_Psi_val(node, 0);
- ir_node *val_false = get_Psi_default(node);
+ ir_node *val_true = get_Mux_true(node);
+ ir_node *val_false = get_Mux_false(node);
ir_node *new_node;
match_flags_t match_flags;
ia32_address_mode_t am;
}
/**
- * Transforms a Psi node into CMov.
+ * Transforms a Mux node into CMov.
*
* @return The transformed node.
*/
-static ir_node *gen_Psi(ir_node *node)
+static ir_node *gen_Mux(ir_node *node)
{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_node *psi_true = get_Psi_val(node, 0);
- ir_node *psi_default = get_Psi_default(node);
- ir_node *cond = get_Psi_cond(node, 0);
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
+ ir_node *cond = get_Mux_sel(node);
ir_mode *mode = get_irn_mode(node);
pn_Cmp pnc;
- assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
- /* Note: a Psi node uses a Load two times IFF it's used in the compare AND in the result */
+ /* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
if (mode_is_float(mode)) {
ir_node *cmp = get_Proj_pred(cond);
ir_node *cmp_left = get_Cmp_left(cmp);
if (ia32_cg_config.use_sse2) {
if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
- if (cmp_left == psi_true && cmp_right == psi_default) {
- /* psi(a <= b, a, b) => MIN */
+ if (cmp_left == mux_true && cmp_right == mux_false) {
+ /* Mux(a <= b, a, b) => MIN */
return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
match_commutative | match_am | match_two_users);
- } else if (cmp_left == psi_default && cmp_right == psi_true) {
- /* psi(a <= b, b, a) => MAX */
+ } else if (cmp_left == mux_false && cmp_right == mux_true) {
+ /* Mux(a <= b, b, a) => MAX */
return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
match_commutative | match_am | match_two_users);
}
} else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
- if (cmp_left == psi_true && cmp_right == psi_default) {
- /* psi(a >= b, a, b) => MAX */
+ if (cmp_left == mux_true && cmp_right == mux_false) {
+ /* Mux(a >= b, a, b) => MAX */
return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
match_commutative | match_am | match_two_users);
- } else if (cmp_left == psi_default && cmp_right == psi_true) {
- /* psi(a >= b, b, a) => MIN */
+ } else if (cmp_left == mux_false && cmp_right == mux_true) {
+ /* Mux(a >= b, b, a) => MIN */
return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
match_commutative | match_am | match_two_users);
}
}
}
- panic("cannot transform floating point Psi");
+ panic("cannot transform floating point Mux");
} else {
ir_node *flags;
/* check for unsigned Doz first */
if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
- is_Const_0(psi_default) && is_Sub(psi_true) &&
- get_Sub_left(psi_true) == cmp_left && get_Sub_right(psi_true) == cmp_right) {
- /* Psi(a >=u b, a - b, 0) unsigned Doz */
+ is_Const_0(mux_false) && is_Sub(mux_true) &&
+ get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) {
+ /* Mux(a >=u b, a - b, 0) unsigned Doz */
return create_Doz(node, cmp_left, cmp_right);
} else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
- is_Const_0(psi_true) && is_Sub(psi_default) &&
- get_Sub_left(psi_default) == cmp_left && get_Sub_right(psi_default) == cmp_right) {
- /* Psi(a <=u b, 0, a - b) unsigned Doz */
+ is_Const_0(mux_true) && is_Sub(mux_false) &&
+ get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) {
+ /* Mux(a <=u b, 0, a - b) unsigned Doz */
return create_Doz(node, cmp_left, cmp_right);
}
}
flags = get_flags_node(cond, &pnc);
- if (is_Const(psi_true) && is_Const(psi_default)) {
+ if (is_Const(mux_true) && is_Const(mux_false)) {
/* both are const, good */
- if (is_Const_1(psi_true) && is_Const_0(psi_default)) {
+ if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0);
- } else if (is_Const_0(psi_true) && is_Const_1(psi_default)) {
+ } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1);
} else {
/* Not that simple. */
} else {
res = gen_x87_gp_to_fp(node, src_mode);
if(get_Conv_strict(node)) {
- res = gen_x87_strict_conv(tgt_mode, res);
- SET_IA32_ORIG_NODE(get_Proj_pred(res),
- ia32_get_old_node_name(env_cg, node));
+ /* The strict-Conv is only necessary, if the int mode has more bits
+ * than the float mantissa */
+ size_t int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
+ size_t float_mantissa;
+ /* FIXME There is no way to get the mantissa size of a mode */
+ switch (get_mode_size_bits(tgt_mode)) {
+ case 32: float_mantissa = 23 + 1; break; // + 1 for implicit 1
+ case 64: float_mantissa = 52 + 1; break;
+ case 80: float_mantissa = 64 + 1; break;
+ default: float_mantissa = 0; break;
+ }
+ if (float_mantissa < int_mantissa) {
+ res = gen_x87_strict_conv(tgt_mode, res);
+ SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
+ }
}
return res;
}
return res;
}
-static bool check_immediate_constraint(long val, char immediate_constraint_type)
-{
- switch (immediate_constraint_type) {
- case 0:
- case 'i':
- return true;
- case 'I':
- return val >= 0 && val <= 32;
- case 'J':
- return val >= 0 && val <= 63;
- case 'K':
- return val >= -128 && val <= 127;
- case 'L':
- return val == 0xff || val == 0xffff;
- case 'M':
- return val >= 0 && val <= 3;
- case 'N':
- return val >= 0 && val <= 255;
- case 'O':
- return val >= 0 && val <= 127;
- default:
- break;
- }
- panic("Invalid immediate constraint found");
- return false;
-}
-
-static ir_node *try_create_Immediate(ir_node *node,
- char immediate_constraint_type)
-{
- int minus = 0;
- tarval *offset = NULL;
- int offset_sign = 0;
- long val = 0;
- ir_entity *symconst_ent = NULL;
- int symconst_sign = 0;
- ir_mode *mode;
- ir_node *cnst = NULL;
- ir_node *symconst = NULL;
- ir_node *new_node;
-
- mode = get_irn_mode(node);
- if(!mode_is_int(mode) && !mode_is_reference(mode)) {
- return NULL;
- }
-
- if(is_Minus(node)) {
- minus = 1;
- node = get_Minus_op(node);
- }
-
- if(is_Const(node)) {
- cnst = node;
- symconst = NULL;
- offset_sign = minus;
- } else if(is_SymConst(node)) {
- cnst = NULL;
- symconst = node;
- symconst_sign = minus;
- } else if(is_Add(node)) {
- ir_node *left = get_Add_left(node);
- ir_node *right = get_Add_right(node);
- if(is_Const(left) && is_SymConst(right)) {
- cnst = left;
- symconst = right;
- symconst_sign = minus;
- offset_sign = minus;
- } else if(is_SymConst(left) && is_Const(right)) {
- cnst = right;
- symconst = left;
- symconst_sign = minus;
- offset_sign = minus;
- }
- } else if(is_Sub(node)) {
- ir_node *left = get_Sub_left(node);
- ir_node *right = get_Sub_right(node);
- if(is_Const(left) && is_SymConst(right)) {
- cnst = left;
- symconst = right;
- symconst_sign = !minus;
- offset_sign = minus;
- } else if(is_SymConst(left) && is_Const(right)) {
- cnst = right;
- symconst = left;
- symconst_sign = minus;
- offset_sign = !minus;
- }
- } else {
- return NULL;
- }
-
- if(cnst != NULL) {
- offset = get_Const_tarval(cnst);
- if(tarval_is_long(offset)) {
- val = get_tarval_long(offset);
- } else {
- ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
- "long?\n", cnst);
- return NULL;
- }
-
- if(!check_immediate_constraint(val, immediate_constraint_type))
- return NULL;
- }
- if(symconst != NULL) {
- if(immediate_constraint_type != 0) {
- /* we need full 32bits for symconsts */
- return NULL;
- }
-
- /* unfortunately the assembler/linker doesn't support -symconst */
- if(symconst_sign)
- return NULL;
-
- if(get_SymConst_kind(symconst) != symconst_addr_ent)
- return NULL;
- symconst_ent = get_SymConst_entity(symconst);
- }
- if(cnst == NULL && symconst == NULL)
- return NULL;
-
- if(offset_sign && offset != NULL) {
- offset = tarval_neg(offset);
- }
-
- new_node = create_Immediate(symconst_ent, symconst_sign, val);
-
- return new_node;
-}
-
static ir_node *create_immediate_or_transform(ir_node *node,
char immediate_constraint_type)
{
return new_node;
}
-
-
-void parse_asm_constraints(constraint_t *constraint, const char *c,
- bool is_output)
-{
- asm_constraint_flags_t flags = 0;
- char immediate_type = '\0';
- unsigned limited = 0;
- const arch_register_class_t *cls = NULL;
- bool memory_possible = false;
- bool all_registers_allowed = false;
- int p;
- int same_as = -1;
-
- memset(constraint, 0, sizeof(constraint[0]));
- constraint->same_as = -1;
-
- if(*c == 0) {
- /* a memory constraint: no need to do anything in backend about it
- * (the dependencies are already respected by the memory edge of
- * the node) */
- return;
- }
-
- /* TODO: improve error messages with node and source info. (As users can
- * easily hit these) */
- while(*c != 0) {
- switch(*c) {
- case ' ':
- case '\t':
- case '\n':
- break;
-
- case '=':
- flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
- | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
- break;
-
- case '+':
- flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
- | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
- break;
-
- case '*':
- ++c;
- break;
- case '#':
- while(*c != 0 && *c != ',')
- ++c;
- break;
-
- case 'a':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX;
- break;
- case 'b':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EBX;
- break;
- case 'c':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_ECX;
- break;
- case 'd':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EDX;
- break;
- case 'D':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EDI;
- break;
- case 'S':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_ESI;
- break;
- case 'Q':
- case 'q':
- /* q means lower part of the regs only, this makes no
- * difference to Q for us (we only assign whole registers) */
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
- 1 << REG_EDX;
- break;
- case 'A':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EDX;
- break;
- case 'l':
- assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
- 1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
- 1 << REG_EBP;
- break;
-
- case 'R':
- case 'r':
- case 'p':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- all_registers_allowed = true;
- break;
-
- case 'f':
- case 't':
- case 'u':
- /* TODO: mark values so the x87 simulator knows about t and u */
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
- panic("multiple register classes not supported");
- cls = &ia32_reg_classes[CLASS_ia32_vfp];
- all_registers_allowed = true;
- break;
-
- case 'Y':
- case 'x':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
- panic("multiple register classes not supproted");
- cls = &ia32_reg_classes[CLASS_ia32_xmm];
- all_registers_allowed = true;
- break;
-
- case 'I':
- case 'J':
- case 'K':
- case 'L':
- case 'M':
- case 'N':
- case 'O':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- if (immediate_type != '\0')
- panic("multiple immediate types not supported");
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- immediate_type = *c;
- break;
- case 'n':
- case 'i':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- if (immediate_type != '\0')
- panic("multiple immediate types not supported");
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- immediate_type = 'i';
- break;
-
- case 'X':
- case 'g':
- if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
- panic("multiple register classes not supported");
- if (immediate_type != '\0')
- panic("multiple immediate types not supported");
- immediate_type = 'i';
- cls = &ia32_reg_classes[CLASS_ia32_gp];
- all_registers_allowed = true;
- memory_possible = true;
- break;
-
- case '0':
- case '1':
- case '2':
- case '3':
- case '4':
- case '5':
- case '6':
- case '7':
- case '8':
- case '9':
- if (is_output)
- panic("can only specify same constraint on input");
-
- sscanf(c, "%d%n", &same_as, &p);
- if(same_as >= 0) {
- c += p;
- continue;
- }
- break;
-
- case 'm':
- case 'o':
- case 'V':
- /* memory constraint no need to do anything in backend about it
- * (the dependencies are already respected by the memory edge of
- * the node) */
- memory_possible = true;
- break;
-
- case 'E': /* no float consts yet */
- case 'F': /* no float consts yet */
- case 's': /* makes no sense on x86 */
- case '<': /* no autodecrement on x86 */
- case '>': /* no autoincrement on x86 */
- case 'C': /* sse constant not supported yet */
- case 'G': /* 80387 constant not supported yet */
- case 'y': /* we don't support mmx registers yet */
- case 'Z': /* not available in 32 bit mode */
- case 'e': /* not available in 32 bit mode */
- panic("unsupported asm constraint '%c' found in (%+F)",
- *c, current_ir_graph);
- break;
- default:
- panic("unknown asm constraint '%c' found in (%+F)", *c,
- current_ir_graph);
- break;
- }
- ++c;
- }
-
- if(same_as >= 0) {
- if (cls != NULL)
- panic("same as and register constraint not supported");
- if (immediate_type != '\0')
- panic("same as and immediate constraint not supported");
- }
-
- if (cls == NULL && same_as < 0) {
- if (!memory_possible)
- panic("no constraint specified for assembler input");
- }
-
- constraint->same_as = same_as;
- constraint->cls = cls;
- constraint->allowed_registers = limited;
- constraint->all_registers_allowed = all_registers_allowed;
- constraint->memory_possible = memory_possible;
- constraint->immediate_type = immediate_type;
-}
-
-const arch_register_req_t *make_register_req(const constraint_t *constraint,
- int n_outs, const arch_register_req_t **out_reqs, int pos)
-{
- struct obstack *obst = get_irg_obstack(current_ir_graph);
- int same_as = constraint->same_as;
- arch_register_req_t *req;
-
- if (same_as >= 0) {
- const arch_register_req_t *other_constr;
-
- if (same_as >= n_outs)
- panic("invalid output number in same_as constraint");
-
- other_constr = out_reqs[same_as];
-
- req = obstack_alloc(obst, sizeof(req[0]));
- req->cls = other_constr->cls;
- req->type = arch_register_req_type_should_be_same;
- req->limited = NULL;
- req->other_same = 1U << pos;
- req->other_different = 0;
-
- /* switch constraints. This is because in firm we have same_as
- * constraints on the output constraints while in the gcc asm syntax
- * they are specified on the input constraints */
- out_reqs[same_as] = req;
- return other_constr;
- }
-
- /* pure memory ops */
- if (constraint->cls == NULL) {
- return &no_register_req;
- }
-
- if (constraint->allowed_registers != 0
- && !constraint->all_registers_allowed) {
- unsigned *limited_ptr;
-
- req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
- memset(req, 0, sizeof(req[0]));
- limited_ptr = (unsigned*) (req+1);
-
- req->type = arch_register_req_type_limited;
- *limited_ptr = constraint->allowed_registers;
- req->limited = limited_ptr;
- } else {
- req = obstack_alloc(obst, sizeof(req[0]));
- memset(req, 0, sizeof(req[0]));
- req->type = arch_register_req_type_normal;
- }
- req->cls = constraint->cls;
-
- return req;
-}
-
-const arch_register_t *ia32_get_clobber_register(const char *clobber)
-{
- const arch_register_t *reg = NULL;
- int c;
- size_t r;
- const arch_register_class_t *cls;
-
- /* TODO: construct a hashmap instead of doing linear search for clobber
- * register */
- for(c = 0; c < N_CLASSES; ++c) {
- cls = & ia32_reg_classes[c];
- for(r = 0; r < cls->n_regs; ++r) {
- const arch_register_t *temp_reg = arch_register_for_index(cls, r);
- if(strcmp(temp_reg->name, clobber) == 0
- || (c == CLASS_ia32_gp && strcmp(temp_reg->name+1, clobber) == 0)) {
- reg = temp_reg;
- break;
- }
- }
- if(reg != NULL)
- break;
- }
-
- return reg;
-}
-
-const arch_register_req_t *parse_clobber(const char *clobber)
-{
- struct obstack *obst = get_irg_obstack(current_ir_graph);
- const arch_register_t *reg = ia32_get_clobber_register(clobber);
- arch_register_req_t *req;
- unsigned *limited;
-
- if(reg == NULL) {
- panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
- }
-
- assert(reg->index < 32);
-
- limited = obstack_alloc(obst, sizeof(limited[0]));
- *limited = 1 << reg->index;
-
- req = obstack_alloc(obst, sizeof(req[0]));
- memset(req, 0, sizeof(req[0]));
- req->type = arch_register_req_type_limited;
- req->cls = arch_register_get_class(reg);
- req->limited = limited;
-
- return req;
-}
-
-/**
- * generates code for a ASM node
- */
-static ir_node *gen_ASM(ir_node *node)
-{
- ir_graph *irg = current_ir_graph;
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- int i, arity;
- int out_idx;
- ir_node **in;
- ir_node *new_node;
- int out_arity;
- int n_out_constraints;
- int n_clobbers;
- const arch_register_req_t **out_reg_reqs;
- const arch_register_req_t **in_reg_reqs;
- ia32_asm_reg_t *register_map;
- unsigned reg_map_size = 0;
- struct obstack *obst;
- const ir_asm_constraint *in_constraints;
- const ir_asm_constraint *out_constraints;
- ident **clobbers;
- bool clobbers_flags = false;
-
- /* workaround for lots of buggy code out there as most people think volatile
- * asm is enough for everything and forget the flags (linux kernel, etc.)
- */
- if (get_irn_pinned(node) == op_pin_state_pinned) {
- clobbers_flags = true;
- }
-
- arity = get_irn_arity(node);
- in = alloca(arity * sizeof(in[0]));
- memset(in, 0, arity * sizeof(in[0]));
-
- clobbers = get_ASM_clobbers(node);
- n_clobbers = 0;
- for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
- const char *c = get_id_str(clobbers[i]);
- if (strcmp(c, "memory") == 0)
- continue;
- if (strcmp(c, "cc") == 0) {
- clobbers_flags = true;
- continue;
- }
- n_clobbers++;
- }
- n_out_constraints = get_ASM_n_output_constraints(node);
- out_arity = n_out_constraints + n_clobbers;
-
- in_constraints = get_ASM_input_constraints(node);
- out_constraints = get_ASM_output_constraints(node);
-
- /* determine size of register_map */
- for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
- const ir_asm_constraint *constraint = &out_constraints[out_idx];
- if (constraint->pos > reg_map_size)
- reg_map_size = constraint->pos;
- }
- for(i = 0; i < arity; ++i) {
- const ir_asm_constraint *constraint = &in_constraints[i];
- if(constraint->pos > reg_map_size)
- reg_map_size = constraint->pos;
- }
- ++reg_map_size;
-
- obst = get_irg_obstack(irg);
- register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
- memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
-
- /* construct output constraints */
- out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
-
- for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
- const ir_asm_constraint *constraint = &out_constraints[out_idx];
- const char *c = get_id_str(constraint->constraint);
- unsigned pos = constraint->pos;
- constraint_t parsed_constraint;
- const arch_register_req_t *req;
-
- parse_asm_constraints(&parsed_constraint, c, true);
- req = make_register_req(&parsed_constraint, n_out_constraints,
- out_reg_reqs, out_idx);
- out_reg_reqs[out_idx] = req;
-
- register_map[pos].use_input = false;
- register_map[pos].valid = true;
- register_map[pos].memory = false;
- register_map[pos].inout_pos = out_idx;
- register_map[pos].mode = constraint->mode;
- }
-
- /* inputs + input constraints */
- in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
- for(i = 0; i < arity; ++i) {
- ir_node *pred = get_irn_n(node, i);
- const ir_asm_constraint *constraint = &in_constraints[i];
- ident *constr_id = constraint->constraint;
- const char *c = get_id_str(constr_id);
- unsigned pos = constraint->pos;
- bool is_memory_op = false;
- ir_node *input = NULL;
- constraint_t parsed_constraint;
- const arch_register_req_t *req;
-
- parse_asm_constraints(&parsed_constraint, c, false);
- req = make_register_req(&parsed_constraint, n_out_constraints,
- out_reg_reqs, i);
- in_reg_reqs[i] = req;
-
- if (parsed_constraint.immediate_type != '\0') {
- char imm_type = parsed_constraint.immediate_type;
- input = try_create_Immediate(pred, imm_type);
- }
-
- if (input == NULL) {
- ir_node *pred = get_irn_n(node, i);
- input = be_transform_node(pred);
-
- if (parsed_constraint.cls == NULL
- && parsed_constraint.same_as < 0) {
- is_memory_op = true;
- } else if(parsed_constraint.memory_possible) {
- /* TODO: match Load or Load/Store if memory possible is set */
- }
- }
- in[i] = input;
-
- register_map[pos].use_input = true;
- register_map[pos].valid = true;
- register_map[pos].memory = is_memory_op;
- register_map[pos].inout_pos = i;
- register_map[pos].mode = constraint->mode;
- }
-
- /* parse clobbers */
- for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
- const char *c = get_id_str(clobbers[i]);
- const arch_register_req_t *req;
-
- if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
- continue;
-
- req = parse_clobber(c);
- out_reg_reqs[out_idx] = req;
- ++out_idx;
- }
-
- new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
- get_ASM_text(node), register_map);
-
- set_ia32_out_req_all(new_node, out_reg_reqs);
- set_ia32_in_req_all(new_node, in_reg_reqs);
-
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
-
- return new_node;
-}
-
/**
* Transforms a FrameAddr into an ia32 Add.
*/
return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
}
-/**
- * This function just sets the register for the Unknown node
- * as this is not done during register allocation because Unknown
- * is an "ignore" node.
- */
-static ir_node *gen_Unknown(ir_node *node) {
- ir_mode *mode = get_irn_mode(node);
-
- if (mode_is_float(mode)) {
- if (ia32_cg_config.use_sse2) {
- return ia32_new_Unknown_xmm(env_cg);
- } else {
- /* Unknown nodes are buggy in x87 simulator, use zero for now... */
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_irg_start_block(irg);
- ir_node *ret = new_rd_ia32_vfldz(dbgi, irg, block);
-
- /* Const Nodes before the initial IncSP are a bad idea, because
- * they could be spilled and we have no SP ready at that point yet.
- * So add a dependency to the initial frame pointer calculation to
- * avoid that situation.
- */
- add_irn_dep(ret, get_irg_frame(irg));
- return ret;
- }
- } else if (ia32_mode_needs_gp_reg(mode)) {
- return ia32_new_Unknown_gp(env_cg);
- } else {
- panic("unsupported Unknown-Mode");
- }
- return NULL;
-}
-
/**
* Change some phi modes
*/
GEN(Cmp);
GEN(ASM);
GEN(CopyB);
- BAD(Mux);
- GEN(Psi);
+ GEN(Mux);
GEN(Proj);
GEN(Phi);
GEN(IJmp);
projects / libfirm / blobdiff