Handle new ia32_isa_t type

[libfirm] / ir / be / ia32 / ia32_transform.c

diff --git a/ir/be/ia32/ia32_transform.c b/ir/be/ia32/ia32_transform.c
index 87290f6..5108be1 100644 (file)
--- a/ir/be/ia32/ia32_transform.c
+++ b/ir/be/ia32/ia32_transform.c
@@ -195,7 +195,7 @@ static ir_node *gen_binop(ia32_transform_env_t *env, ir_node *op1, ir_node *op2,
 
        /* Check if immediate optimization is on and */
        /* if it's an operation with immediate.      */
-       if (! env->cg->opt.immops) {
+       if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
                expr_op = op1;
                imm_op  = NULL;
        }
@@ -288,7 +288,7 @@ static ir_node *gen_shift_binop(ia32_transform_env_t *env, ir_node *op1, ir_node
 
        /* Check if immediate optimization is on and */
        /* if it's an operation with immediate.      */
-       imm_op  = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
+       imm_op  = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
        expr_op = get_expr_op(op1, op2);
 
        assert((expr_op || imm_op) && "invalid operands");
@@ -396,7 +396,7 @@ static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node
        DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
 
        /* try to optimize to inc/dec  */
-       if (env->cg->opt.incdec && tv) {
+       if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
                /* optimize tarvals */
                class_tv    = classify_tarval(tv);
                class_negtv = classify_tarval(tarval_neg(tv));
@@ -441,7 +441,7 @@ static ir_node *gen_Add(ia32_transform_env_t *env) {
 
        /* Check if immediate optimization is on and */
        /* if it's an operation with immediate.      */
-       imm_op  = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
+       imm_op  = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
        expr_op = get_expr_op(op1, op2);
 
        assert((expr_op || imm_op) && "invalid operands");
@@ -715,7 +715,7 @@ static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node
        DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
 
        /* try to optimize to inc/dec  */
-       if (env->cg->opt.incdec && tv) {
+       if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
                /* optimize tarvals */
                class_tv    = classify_tarval(tv);
                class_negtv = classify_tarval(tarval_neg(tv));
@@ -760,7 +760,7 @@ static ir_node *gen_Sub(ia32_transform_env_t *env) {
 
        /* Check if immediate optimization is on and */
        /* if it's an operation with immediate.      */
-       imm_op  = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
+       imm_op  = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
        expr_op = get_expr_op(op1, op2);
 
        assert((expr_op || imm_op) && "invalid operands");
@@ -888,9 +888,8 @@ static ir_node *generate_DivMod(ia32_transform_env_t *env, ir_node *dividend, ir
                set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
        }
 
-       res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
+       res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T, dm_flav);
 
-       set_ia32_flavour(res, dm_flav);
        set_ia32_n_res(res, 2);
 
        /* Only one proj is used -> We must add a second proj and */
@@ -1403,7 +1402,7 @@ static ir_node *gen_Cond(ia32_transform_env_t *env) {
                cmp_b = get_Cmp_right(pred);
 
                /* check if we can use a CondJmp with immediate */
-               cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
+               cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
                expr = get_expr_op(cmp_a, cmp_b);
 
                if (cnst && expr) {
@@ -1703,7 +1702,7 @@ static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
 static ir_node *gen_Conv(ia32_transform_env_t *env) {
        dbg_info          *dbg      = env->dbg;
        ir_graph          *irg      = env->irg;
-  ir_node           *op       = get_Conv_op(env->irn);
+       ir_node           *op       = get_Conv_op(env->irn);
        ir_mode           *src_mode = get_irn_mode(op);
        ir_mode           *tgt_mode = env->mode;
        int                src_bits = get_mode_size_bits(src_mode);
@@ -1950,6 +1949,30 @@ static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
        return new_op;
 }
 
+/**
+ * This function just sets the register for the Unknown node
+ * as this is not done during register allocation because Unknown
+ * is an "ignore" node.
+ */
+static ir_node *gen_Unknown(ia32_transform_env_t *env) {
+       ir_mode *mode = env->mode;
+       ir_node *irn  = env->irn;
+
+       if (mode_is_float(mode)) {
+               if (USE_SSE2(env->cg))
+                       arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
+               else
+                       arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
+       }
+       else if (mode_is_int(mode) || mode_is_reference(mode)) {
+               arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
+       }
+       else {
+               assert(0 && "unsupported Unknown-Mode");
+       }
+
+       return NULL;
+}
 
 
 /*********************************************************
@@ -2208,7 +2231,6 @@ void ia32_register_transformers(void) {
        IGN(IJmp);
        IGN(Break);
        IGN(Cmp);
-       IGN(Unknown);
 
        /* constant transformation happens earlier */
        IGN(Const);
@@ -2234,6 +2256,9 @@ void ia32_register_transformers(void) {
        GEN(be_FrameStore);
        GEN(be_StackParam);
 
+       /* set the register for all Unknown nodes */
+       GEN(Unknown);
+
        op_Max = get_op_Max();
        if (op_Max)
                GEN(Max);