#include "config.h"
#endif
+#include <limits.h>
+
#include "irargs_t.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "irvrfy.h"
#include "ircons.h"
#include "dbginfo.h"
+#include "irprintf.h"
#include "debug.h"
#include "../benode_t.h"
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- if (! env->cg->opt.immops) {
+ if (! (env->cg->opt & IA32_OPT_IMMOPS)) {
expr_op = op1;
imm_op = NULL;
}
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
+ imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
expr_op = get_expr_op(op1, op2);
assert((expr_op || imm_op) && "invalid operands");
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
- if (env->cg->opt.incdec && tv) {
+ if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
/* optimize tarvals */
class_tv = classify_tarval(tv);
class_negtv = classify_tarval(tarval_neg(tv));
/**
* Creates an ia32 Add.
*
- * @param dbg firm node dbg
- * @param block the block the new node should belong to
- * @param op1 first operator
- * @param op2 second operator
- * @param mode node mode
+ * @param env The transformation environment
* @return the created ia32 Add node
*/
-static ir_node *gen_Add(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Add(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
dbg_info *dbg = env->dbg;
ir_mode *mode = env->mode;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
+ ir_node *op1 = get_Add_left(env->irn);
+ ir_node *op2 = get_Add_right(env->irn);
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- imm_op = env->cg->opt.immops ? get_immediate_op(op1, op2) : NULL;
+ imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(op1, op2) : NULL;
expr_op = get_expr_op(op1, op2);
assert((expr_op || imm_op) && "invalid operands");
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
- else {
- env->cg->used_x87 = 1;
+ else
return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
- }
}
else {
/* integer ADD */
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Full);
+ set_ia32_commutative(new_op);
}
}
/**
* Creates an ia32 Mul.
*
- * @param dbg firm node dbg
- * @param block the block the new node should belong to
- * @param op1 first operator
- * @param op2 second operator
- * @param mode node mode
+ * @param env The transformation environment
* @return the created ia32 Mul node
*/
-static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Mul(ia32_transform_env_t *env) {
+ ir_node *op1 = get_Mul_left(env->irn);
+ ir_node *op2 = get_Mul_right(env->irn);
ir_node *new_op;
if (mode_is_float(env->mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
- else {
- env->cg->used_x87 = 1;
+ else
new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
- }
}
else {
new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
* this result while Mul returns the lower 32 bit.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return the created ia32 Mulh node
*/
-static ir_node *gen_Mulh(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Mulh(ia32_transform_env_t *env) {
+ ir_node *op1 = get_irn_n(env->irn, 0);
+ ir_node *op2 = get_irn_n(env->irn, 1);
ir_node *proj_EAX, *proj_EDX, *mulh;
ir_node *in[1];
* Creates an ia32 And.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 And node
*/
-static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_And(ia32_transform_env_t *env) {
+ ir_node *op1 = get_And_left(env->irn);
+ ir_node *op2 = get_And_right(env->irn);
+
assert (! mode_is_float(env->mode));
return gen_binop(env, op1, op2, new_rd_ia32_And);
}
* Creates an ia32 Or.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 Or node
*/
-static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Or(ia32_transform_env_t *env) {
+ ir_node *op1 = get_Or_left(env->irn);
+ ir_node *op2 = get_Or_right(env->irn);
+
assert (! mode_is_float(env->mode));
return gen_binop(env, op1, op2, new_rd_ia32_Or);
}
* Creates an ia32 Eor.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 Eor node
*/
-static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Eor(ia32_transform_env_t *env) {
+ ir_node *op1 = get_Eor_left(env->irn);
+ ir_node *op2 = get_Eor_right(env->irn);
+
assert(! mode_is_float(env->mode));
return gen_binop(env, op1, op2, new_rd_ia32_Eor);
}
* Creates an ia32 Max.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return the created ia32 Max node
*/
-static ir_node *gen_Max(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Max(ia32_transform_env_t *env) {
+ ir_node *op1 = get_irn_n(env->irn, 0);
+ ir_node *op2 = get_irn_n(env->irn, 1);
ir_node *new_op;
if (mode_is_float(env->mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
else {
- env->cg->used_x87 = 1;
assert(0);
}
}
* Creates an ia32 Min.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return the created ia32 Min node
*/
-static ir_node *gen_Min(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Min(ia32_transform_env_t *env) {
+ ir_node *op1 = get_irn_n(env->irn, 0);
+ ir_node *op2 = get_irn_n(env->irn, 1);
ir_node *new_op;
if (mode_is_float(env->mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
else {
- env->cg->used_x87 = 1;
assert(0);
}
}
/**
* Creates an ia32 Sub with immediate.
*
- * @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
+ * @param env The transformation environment
+ * @param expr_op The first operator
+ * @param const_op The constant operator
* @return The created ia32 Sub node
*/
static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
- if (env->cg->opt.incdec && tv) {
+ if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
/* optimize tarvals */
class_tv = classify_tarval(tv);
class_negtv = classify_tarval(tarval_neg(tv));
* Creates an ia32 Sub.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 Sub node
*/
-static ir_node *gen_Sub(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Sub(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
dbg_info *dbg = env->dbg;
ir_mode *mode = env->mode;
ir_node *block = env->block;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_NoMem();
+ ir_node *op1 = get_Sub_left(env->irn);
+ ir_node *op2 = get_Sub_right(env->irn);
ir_node *expr_op, *imm_op;
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
- imm_op = env->cg->opt.immops ? get_immediate_op(NULL, op2) : NULL;
+ imm_op = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, op2) : NULL;
expr_op = get_expr_op(op1, op2);
assert((expr_op || imm_op) && "invalid operands");
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
return gen_binop(env, op1, op2, new_rd_ia32_fSub);
- else {
- env->cg->used_x87 = 1;
+ else
return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
- }
}
else {
/* integer SUB */
set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
}
- res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T);
+ res = new_rd_ia32_DivMod(dbg, irg, block, dividend, divisor, edx_node, mem, mode_T, dm_flav);
- set_ia32_flavour(res, dm_flav);
set_ia32_n_res(res, 2);
/* Only one proj is used -> We must add a second proj and */
/**
* Wrapper for generate_DivMod. Sets flavour_Mod.
+ *
+ * @param env The transformation environment
*/
-static ir_node *gen_Mod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- return generate_DivMod(env, op1, op2, flavour_Mod);
+static ir_node *gen_Mod(ia32_transform_env_t *env) {
+ return generate_DivMod(env, get_Mod_left(env->irn), get_Mod_right(env->irn), flavour_Mod);
}
-
-
/**
* Wrapper for generate_DivMod. Sets flavour_Div.
+ *
+ * @param env The transformation environment
*/
-static ir_node *gen_Div(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- return generate_DivMod(env, op1, op2, flavour_Div);
+static ir_node *gen_Div(ia32_transform_env_t *env) {
+ return generate_DivMod(env, get_Div_left(env->irn), get_Div_right(env->irn), flavour_Div);
}
-
-
/**
* Wrapper for generate_DivMod. Sets flavour_DivMod.
*/
-static ir_node *gen_DivMod(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- return generate_DivMod(env, op1, op2, flavour_DivMod);
+static ir_node *gen_DivMod(ia32_transform_env_t *env) {
+ return generate_DivMod(env, get_DivMod_left(env->irn), get_DivMod_right(env->irn), flavour_DivMod);
}
* Creates an ia32 floating Div.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 fDiv node
*/
-static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Quot(ia32_transform_env_t *env) {
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *new_op;
ir_node *nomem = new_rd_NoMem(env->irg);
+ ir_node *op1 = get_Quot_left(env->irn);
+ ir_node *op2 = get_Quot_right(env->irn);
+ FP_USED(env->cg);
if (USE_SSE2(env->cg)) {
-
if (is_ia32_fConst(op2)) {
new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
set_ia32_am_support(new_op, ia32_am_None);
}
}
else {
- new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
- set_ia32_am_support(new_op, ia32_am_Source);
+ new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
+ set_ia32_am_support(new_op, ia32_am_Source);
}
set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
* Creates an ia32 Shl.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 Shl node
*/
-static ir_node *gen_Shl(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- return gen_shift_binop(env, op1, op2, new_rd_ia32_Shl);
+static ir_node *gen_Shl(ia32_transform_env_t *env) {
+ return gen_shift_binop(env, get_Shl_left(env->irn), get_Shl_right(env->irn), new_rd_ia32_Shl);
}
* Creates an ia32 Shr.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 Shr node
*/
-static ir_node *gen_Shr(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- return gen_shift_binop(env, op1, op2, new_rd_ia32_Shr);
+static ir_node *gen_Shr(ia32_transform_env_t *env) {
+ return gen_shift_binop(env, get_Shr_left(env->irn), get_Shr_right(env->irn), new_rd_ia32_Shr);
}
* Creates an ia32 Shrs.
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 Shrs node
*/
-static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- return gen_shift_binop(env, op1, op2, new_rd_ia32_Shrs);
+static ir_node *gen_Shrs(ia32_transform_env_t *env) {
+ return gen_shift_binop(env, get_Shrs_left(env->irn), get_Shrs_right(env->irn), new_rd_ia32_Shrs);
}
* Creates an ia32 RotR or RotL (depending on the found pattern).
*
* @param env The transformation environment
- * @param op1 The first operator
- * @param op2 The second operator
* @return The created ia32 RotL or RotR node
*/
-static ir_node *gen_Rot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Rot(ia32_transform_env_t *env) {
ir_node *rotate = NULL;
+ ir_node *op1 = get_Rot_left(env->irn);
+ ir_node *op2 = get_Rot_right(env->irn);
/* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
* Transforms a Minus node.
*
* @param env The transformation environment
- * @param op The operator
+ * @param op The Minus operand
* @return The created ia32 Minus node
*/
-static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
+static ir_node *gen_Minus_ex(ia32_transform_env_t *env, ir_node *op) {
ident *name;
ir_node *new_op;
- ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
- ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
- ir_node *nomem = new_rd_NoMem(env->irg);
int size;
if (mode_is_float(env->mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg)) {
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
+ ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
+ ir_node *nomem = new_rd_NoMem(env->irg);
+
new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
size = get_mode_size_bits(env->mode);
new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
}
else {
- env->cg->used_x87 = 1;
new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
}
return new_op;
}
+/**
+ * Transforms a Minus node.
+ *
+ * @param env The transformation environment
+ * @return The created ia32 Minus node
+ */
+static ir_node *gen_Minus(ia32_transform_env_t *env) {
+ return gen_Minus_ex(env, get_Minus_op(env->irn));
+}
/**
* Transforms a Not node.
*
* @param env The transformation environment
- * @param op The operator
* @return The created ia32 Not node
*/
-static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
+static ir_node *gen_Not(ia32_transform_env_t *env) {
assert (! mode_is_float(env->mode));
- return gen_unop(env, op, new_rd_ia32_Not);
+ return gen_unop(env, get_Not_op(env->irn), new_rd_ia32_Not);
}
* Transforms an Abs node.
*
* @param env The transformation environment
- * @param op The operator
* @return The created ia32 Abs node
*/
-static ir_node *gen_Abs(ia32_transform_env_t *env, ir_node *op) {
+static ir_node *gen_Abs(ia32_transform_env_t *env) {
ir_node *res, *p_eax, *p_edx;
dbg_info *dbg = env->dbg;
ir_mode *mode = env->mode;
ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *nomem = new_NoMem();
+ ir_node *op = get_Abs_op(env->irn);
int size;
ident *name;
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg)) {
res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
}
else {
- env->cg->used_x87 = 1;
res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
}
/**
* Transforms a Load.
*
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir Load node
- * @param mode node mode
+ * @param env The transformation environment
* @return the created ia32 Load node
*/
static ir_node *gen_Load(ia32_transform_env_t *env) {
}
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
- else {
- env->cg->used_x87 = 1;
+ else
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
- }
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
/**
* Transforms a Store.
*
- * @param mod the debug module
- * @param block the block the new node should belong to
- * @param node the ir Store node
- * @param mode node mode
+ * @param env The transformation environment
* @return the created ia32 Store node
*/
static ir_node *gen_Store(ia32_transform_env_t *env) {
}
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
+ else
new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
- }
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
cmp_b = get_Cmp_right(pred);
/* check if we can use a CondJmp with immediate */
- cnst = env->cg->opt.immops ? get_immediate_op(cmp_a, cmp_b) : NULL;
+ cnst = (env->cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(cmp_a, cmp_b) : NULL;
expr = get_expr_op(cmp_a, cmp_b);
if (cnst && expr) {
}
if (mode_is_float(get_irn_mode(expr))) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
else {
- env->cg->used_x87 = 1;
assert(0);
}
}
}
else {
if (mode_is_float(get_irn_mode(cmp_a))) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
else {
- env->cg->used_x87 = 1;
assert(0);
}
}
set_ia32_am_support(res, ia32_am_Source);
}
else {
- res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
+ /* determine the smallest switch case value */
+ int switch_min = INT_MAX;
+ const ir_edge_t *edge;
+ char buf[64];
+
+ foreach_out_edge(node, edge) {
+ int pn = get_Proj_proj(get_edge_src_irn(edge));
+ switch_min = pn < switch_min ? pn : switch_min;
+ }
+
+ if (switch_min) {
+ /* if smallest switch case is not 0 we need an additional sub */
+ snprintf(buf, sizeof(buf), "%d", switch_min);
+ res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
+ sub_ia32_am_offs(res, buf);
+ set_ia32_am_flavour(res, ia32_am_OB);
+ set_ia32_am_support(res, ia32_am_Source);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ }
+
+ res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
set_ia32_pncode(res, get_Cond_defaultProj(node));
set_ia32_res_mode(res, get_irn_mode(sel));
}
* in non-strict semantic
*/
-//static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
-// ir_mode *src_mode, ir_mode *tgt_mode)
-//{
-// int n = get_mode_size_bits(src_mode);
-// int m = get_mode_size_bits(tgt_mode);
-// dbg_info *dbg = env->dbg;
-// ir_graph *irg = env->irg;
-// ir_node *block = env->block;
-// ir_node *noreg = ia32_new_NoReg_gp(env->cg);
-// ir_node *nomem = new_rd_NoMem(irg);
-// ir_node *new_op, *proj;
-// assert(n > m && "downscale expected");
-// if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
-// /* ASHL Sn, n - m */
-// new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
-// proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
-// set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
-// set_ia32_am_support(new_op, ia32_am_Source);
-// SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
-// /* ASHR Sn, n - m */
-// new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
-// set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
-// }
-// else {
-// new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
-// set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
-// }
-// return new_op;
-//}
+/**
+ * Create a conversion from x87 state register to general purpose.
+ */
+static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
+ ia32_code_gen_t *cg = env->cg;
+ entity *ent = cg->fp_to_gp;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *op = get_Conv_op(env->irn);
+ ir_node *fist, *mem, *load;
+
+ if (! ent) {
+ int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
+ ent = cg->fp_to_gp =
+ frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
+ }
+
+ /* do a fist */
+ fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg), mode_T);
+
+ set_ia32_frame_ent(fist, ent);
+ set_ia32_use_frame(fist);
+ set_ia32_am_support(fist, ia32_am_Dest);
+ set_ia32_op_type(fist, ia32_AddrModeD);
+ set_ia32_am_flavour(fist, ia32_B);
+ set_ia32_ls_mode(fist, mode_E);
+
+ mem = new_r_Proj(irg, block, fist, mode_M, 0);
+
+ /* do a Load */
+ load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
+
+ set_ia32_frame_ent(load, ent);
+ set_ia32_use_frame(load);
+ set_ia32_am_support(load, ia32_am_Source);
+ set_ia32_op_type(load, ia32_AddrModeS);
+ set_ia32_am_flavour(load, ia32_B);
+ set_ia32_ls_mode(load, tgt_mode);
+
+ return new_r_Proj(irg, block, load, tgt_mode, 0);
+}
+
+/**
+ * Create a conversion from x87 state register to general purpose.
+ */
+static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
+ ia32_code_gen_t *cg = env->cg;
+ entity *ent = cg->gp_to_fp;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = get_irg_no_mem(irg);
+ ir_node *op = get_Conv_op(env->irn);
+ ir_node *fild, *store, *mem;
+ int src_bits;
+
+ if (! ent) {
+ int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
+ ent = cg->gp_to_fp =
+ frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
+ }
+
+ /* first convert to 32 bit */
+ src_bits = get_mode_size_bits(src_mode);
+ if (src_bits == 8) {
+ op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ op = new_r_Proj(irg, block, op, mode_Is, 0);
+ }
+ else if (src_bits < 32) {
+ op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ op = new_r_Proj(irg, block, op, mode_Is, 0);
+ }
+
+ /* do a store */
+ store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem, mode_T);
+
+ set_ia32_frame_ent(store, ent);
+ set_ia32_use_frame(store);
+
+ set_ia32_am_support(store, ia32_am_Dest);
+ set_ia32_op_type(store, ia32_AddrModeD);
+ set_ia32_am_flavour(store, ia32_B);
+ set_ia32_ls_mode(store, mode_Is);
+
+ mem = new_r_Proj(irg, block, store, mode_M, 0);
+
+ /* do a fild */
+ fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
+
+ set_ia32_frame_ent(fild, ent);
+ set_ia32_use_frame(fild);
+ set_ia32_am_support(fild, ia32_am_Source);
+ set_ia32_op_type(fild, ia32_AddrModeS);
+ set_ia32_am_flavour(fild, ia32_B);
+ set_ia32_ls_mode(fild, mode_E);
+
+ return new_r_Proj(irg, block, fild, mode_E, 0);
+}
/**
* Transforms a Conv node.
*
* @param env The transformation environment
- * @param op The operator
* @return The created ia32 Conv node
*/
-static ir_node *gen_Conv(ia32_transform_env_t *env, ir_node *op) {
+static ir_node *gen_Conv(ia32_transform_env_t *env) {
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
+ ir_node *op = get_Conv_op(env->irn);
ir_mode *src_mode = get_irn_mode(op);
ir_mode *tgt_mode = env->mode;
int src_bits = get_mode_size_bits(src_mode);
else {
/* ... to int */
DB((mod, LEVEL_1, "create Conv(float, int) ..."));
- new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ else
+ return gen_x87_fp_to_gp(env, tgt_mode);
+
/* if target mode is not int: add an additional downscale convert */
if (tgt_bits < 32) {
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
else {
/* we convert from int ... */
if (mode_is_float(tgt_mode)) {
+ FP_USED(env->cg);
/* ... to float */
DB((mod, LEVEL_1, "create Conv(int, float) ..."));
- new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ else
+ return gen_x87_gp_to_fp(env, src_mode);
}
else {
/* ... to int */
*
********************************************/
-static ir_node *gen_StackParam(ia32_transform_env_t *env) {
+static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
ir_node *node = env->irn;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
// }
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
+ else
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- }
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
/**
* Transforms a FrameAddr into an ia32 Add.
*/
-static ir_node *gen_FrameAddr(ia32_transform_env_t *env) {
+static ir_node *gen_be_FrameAddr(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
ir_node *node = env->irn;
ir_node *op = get_irn_n(node, 0);
set_ia32_am_support(new_op, ia32_am_Full);
set_ia32_use_frame(new_op);
set_ia32_immop_type(new_op, ia32_ImmConst);
+ set_ia32_commutative(new_op);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
/**
* Transforms a FrameLoad into an ia32 Load.
*/
-static ir_node *gen_FrameLoad(ia32_transform_env_t *env) {
+static ir_node *gen_be_FrameLoad(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
ir_node *node = env->irn;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_mode *mode = get_type_mode(get_entity_type(ent));
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
+ else
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- }
}
- else {
+ else
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- }
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
/**
* Transforms a FrameStore into an ia32 Store.
*/
-static ir_node *gen_FrameStore(ia32_transform_env_t *env) {
+static ir_node *gen_be_FrameStore(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
ir_node *node = env->irn;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_mode *mode = get_irn_mode(val);
if (mode_is_float(mode)) {
+ FP_USED(env->cg);
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
- else {
- env->cg->used_x87 = 1;
+ else
new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
- }
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
return new_op;
}
+/**
+ * This function just sets the register for the Unknown node
+ * as this is not done during register allocation because Unknown
+ * is an "ignore" node.
+ */
+static ir_node *gen_Unknown(ia32_transform_env_t *env) {
+ ir_mode *mode = env->mode;
+ ir_node *irn = env->irn;
+
+ if (mode_is_float(mode)) {
+ if (USE_SSE2(env->cg))
+ arch_set_irn_register(env->cg->arch_env, irn, &ia32_xmm_regs[REG_XMM_UKNWN]);
+ else
+ arch_set_irn_register(env->cg->arch_env, irn, &ia32_vfp_regs[REG_VFP_UKNWN]);
+ }
+ else if (mode_is_int(mode) || mode_is_reference(mode)) {
+ arch_set_irn_register(env->cg->arch_env, irn, &ia32_gp_regs[REG_GP_UKNWN]);
+ }
+ else {
+ assert(0 && "unsupported Unknown-Mode");
+ }
+
+ return NULL;
+}
/*********************************************************
tenv.dbg = get_irn_dbg_info(irn);
tenv.irg = cg->irg;
tenv.irn = irn;
- DEBUG_ONLY(tenv.mod = cg->mod;)
tenv.mode = get_ia32_res_mode(irn);
tenv.cg = cg;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
/* in case of sub and OUT == SRC2 we can transform the sequence into neg src2 -- add */
if (REGS_ARE_EQUAL(out_reg, in2_reg)) {
/* generate the neg src2 */
- res = gen_Minus(&tenv, in2);
+ res = gen_Minus_ex(&tenv, in2);
arch_set_irn_register(cg->arch_env, res, in2_reg);
/* add to schedule */
else {
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
set_ia32_am_support(res, ia32_am_Full);
+ set_ia32_commutative(res);
}
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
arch_set_irn_register(cg->arch_env, res, out_reg);
set_ia32_op_type(res, ia32_Normal);
+ set_ia32_commutative(res);
if (imm) {
set_ia32_cnst(res, offs);
exchange(irn, res);
}
+/**
+ * the BAD transformer.
+ */
+static ir_node *bad_transform(ia32_transform_env_t *env) {
+ ir_fprintf(stderr, "Not implemented: %+F\n", env->irn);
+ assert(0);
+ return NULL;
+}
+
+/**
+ * Enters all transform functions into the generic pointer
+ */
+void ia32_register_transformers(void) {
+ ir_op *op_Max, *op_Min, *op_Mulh;
+
+ /* first clear the generic function pointer for all ops */
+ clear_irp_opcodes_generic_func();
+
+#define GEN(a) op_##a->ops.generic = (op_func)gen_##a
+#define BAD(a) op_##a->ops.generic = (op_func)bad_transform
+#define IGN(a)
+
+ GEN(Add);
+ GEN(Sub);
+ GEN(Mul);
+ GEN(And);
+ GEN(Or);
+ GEN(Eor);
+
+ GEN(Shl);
+ GEN(Shr);
+ GEN(Shrs);
+ GEN(Rot);
+
+ GEN(Quot);
+
+ GEN(Div);
+ GEN(Mod);
+ GEN(DivMod);
+
+ GEN(Minus);
+ GEN(Conv);
+ GEN(Abs);
+ GEN(Not);
+
+ GEN(Load);
+ GEN(Store);
+ GEN(Cond);
+
+ GEN(CopyB);
+ GEN(Mux);
+
+ IGN(Call);
+ IGN(Alloc);
+
+ IGN(Proj);
+ IGN(Block);
+ IGN(Start);
+ IGN(End);
+ IGN(NoMem);
+ IGN(Phi);
+ IGN(IJmp);
+ IGN(Break);
+ IGN(Cmp);
+
+ /* constant transformation happens earlier */
+ IGN(Const);
+ IGN(SymConst);
+ IGN(Sync);
+
+ BAD(Raise);
+ BAD(Sel);
+ BAD(InstOf);
+ BAD(Cast);
+ BAD(Free);
+ BAD(Tuple);
+ BAD(Id);
+ BAD(Bad);
+ BAD(Confirm);
+ BAD(Filter);
+ BAD(CallBegin);
+ BAD(EndReg);
+ BAD(EndExcept);
+
+ GEN(be_FrameAddr);
+ GEN(be_FrameLoad);
+ GEN(be_FrameStore);
+ GEN(be_StackParam);
+
+ /* set the register for all Unknown nodes */
+ GEN(Unknown);
+
+ op_Max = get_op_Max();
+ if (op_Max)
+ GEN(Max);
+ op_Min = get_op_Min();
+ if (op_Min)
+ GEN(Min);
+ op_Mulh = get_op_Mulh();
+ if (op_Mulh)
+ GEN(Mulh);
+
+#undef GEN
+#undef BAD
+#undef IGN
+}
+
+typedef ir_node *(transform_func)(ia32_transform_env_t *env);
+
/**
* Transforms the given firm node (and maybe some other related nodes)
* into one or more assembler nodes.
* @param env the debug module
*/
void ia32_transform_node(ir_node *node, void *env) {
- ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
- opcode code;
- ir_node *asm_node = NULL;
- ia32_transform_env_t tenv;
+ ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
+ ir_op *op = get_irn_op(node);
+ ir_node *asm_node = NULL;
if (is_Block(node))
return;
- tenv.block = get_nodes_block(node);
- tenv.dbg = get_irn_dbg_info(node);
- tenv.irg = current_ir_graph;
- tenv.irn = node;
- DEBUG_ONLY(tenv.mod = cgenv->mod;)
- tenv.mode = get_irn_mode(node);
- tenv.cg = cgenv;
-
-#define UNOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_op(node)); break
-#define BINOP(a) case iro_##a: asm_node = gen_##a(&tenv, get_##a##_left(node), get_##a##_right(node)); break
-#define GEN(a) case iro_##a: asm_node = gen_##a(&tenv); break
-#define IGN(a) case iro_##a: break
-#define BAD(a) case iro_##a: goto bad
-#define OTHER_BIN(a) \
- if (get_irn_op(node) == get_op_##a()) { \
- asm_node = gen_##a(&tenv, get_irn_n(node, 0), get_irn_n(node, 1)); \
- break; \
- }
-#define BE_GEN(a) \
- if (be_is_##a(node)) { \
- asm_node = gen_##a(&tenv); \
- break; \
- }
-
- DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
-
- code = get_irn_opcode(node);
- switch (code) {
- BINOP(Add);
- BINOP(Sub);
- BINOP(Mul);
- BINOP(And);
- BINOP(Or);
- BINOP(Eor);
-
- BINOP(Shl);
- BINOP(Shr);
- BINOP(Shrs);
- BINOP(Rot);
-
- BINOP(Quot);
-
- BINOP(Div);
- BINOP(Mod);
- BINOP(DivMod);
-
- UNOP(Minus);
- UNOP(Conv);
- UNOP(Abs);
- UNOP(Not);
-
- GEN(Load);
- GEN(Store);
- GEN(Cond);
-
- GEN(CopyB);
- GEN(Mux);
-
- IGN(Call);
- IGN(Alloc);
-
- IGN(Proj);
- IGN(Block);
- IGN(Start);
- IGN(End);
- IGN(NoMem);
- IGN(Phi);
- IGN(IJmp);
- IGN(Break);
- IGN(Cmp);
- IGN(Unknown);
-
- /* constant transformation happens earlier */
- IGN(Const);
- IGN(SymConst);
- IGN(Sync);
-
- BAD(Raise);
- BAD(Sel);
- BAD(InstOf);
- BAD(Cast);
- BAD(Free);
- BAD(Tuple);
- BAD(Id);
- BAD(Bad);
- BAD(Confirm);
- BAD(Filter);
- BAD(CallBegin);
- BAD(EndReg);
- BAD(EndExcept);
+ DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
+ if (op->ops.generic) {
+ ia32_transform_env_t tenv;
+ transform_func *transform = (transform_func *)op->ops.generic;
- default:
- OTHER_BIN(Max);
- OTHER_BIN(Min);
- OTHER_BIN(Mulh);
-
- BE_GEN(FrameAddr);
- BE_GEN(FrameLoad);
- BE_GEN(FrameStore);
- BE_GEN(StackParam);
- break;
-bad:
- fprintf(stderr, "Not implemented: %s\n", get_irn_opname(node));
- assert(0);
+ tenv.block = get_nodes_block(node);
+ tenv.dbg = get_irn_dbg_info(node);
+ tenv.irg = current_ir_graph;
+ tenv.irn = node;
+ tenv.mode = get_irn_mode(node);
+ tenv.cg = cg;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
+
+ asm_node = (*transform)(&tenv);
}
/* exchange nodes if a new one was generated */
if (asm_node) {
exchange(node, asm_node);
- DB((tenv.mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
+ DB((cg->mod, LEVEL_1, "created node %+F[%p]\n", asm_node, asm_node));
}
else {
- DB((tenv.mod, LEVEL_1, "ignored\n"));
+ DB((cg->mod, LEVEL_1, "ignored\n"));
}
-
-#undef UNOP
-#undef BINOP
-#undef GEN
-#undef IGN
-#undef BAD
-#undef OTHER_BIN
-#undef BE_GEN
}