dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
- firm_dbg_module_t *mod = env->mod;
ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
- firm_dbg_module_t *mod = env->mod;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
tarval *tv;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
ir_node *new_op = NULL;
ir_mode *mode = env->mode;
dbg_info *dbg = env->dbg;
- firm_dbg_module_t *mod = env->mod;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_NoMem();
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
ir_node *new_op = NULL;
tarval *tv = get_ia32_Immop_tarval(const_op);
- firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *nomem = new_NoMem();
int normal_add = 1;
tarval_classification_t class_tv, class_negtv;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
if (env->cg->opt.incdec && tv) {
if (USE_SSE2(env->cg))
return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
else {
+ env->cg->used_x87 = 1;
return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
}
}
if (mode_is_float(env->mode)) {
if (USE_SSE2(env->cg))
new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
- else
+ else {
+ env->cg->used_x87 = 1;
new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
+ }
}
else {
new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
ir_node *new_op;
if (mode_is_float(env->mode)) {
- new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
+ if (USE_SSE2(env->cg))
+ new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
+ else {
+ env->cg->used_x87 = 1;
+ assert(0);
+ }
}
else {
new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
ir_node *new_op;
if (mode_is_float(env->mode)) {
- new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
+ if (USE_SSE2(env->cg))
+ new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
+ else {
+ env->cg->used_x87 = 1;
+ assert(0);
+ }
}
else {
new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
ir_node *new_op = NULL;
tarval *tv = get_ia32_Immop_tarval(const_op);
- firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *nomem = new_NoMem();
int normal_sub = 1;
tarval_classification_t class_tv, class_negtv;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
if (env->cg->opt.incdec && tv) {
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
return gen_binop(env, op1, op2, new_rd_ia32_fSub);
- else
+ else {
+ env->cg->used_x87 = 1;
return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
+ }
}
else {
/* integer SUB */
new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
}
else {
+ env->cg->used_x87 = 1;
new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env));
}
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
}
else {
+ env->cg->used_x87 = 1;
res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env));
}
ir_node *node = env->irn;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *ptr = get_Load_ptr(node);
+ ir_node *lptr = ptr;
ir_mode *mode = get_Load_mode(node);
- const char *offs = NULL;
+ int is_imm = 0;
ir_node *new_op;
ia32_am_flavour_t am_flav = ia32_B;
/* address might be a constant (symconst or absolute address) */
if (is_ia32_Const(ptr)) {
- offs = get_ia32_cnst(ptr);
- ptr = noreg;
+ lptr = noreg;
+ is_imm = 1;
}
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
- else
- new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ else {
+ env->cg->used_x87 = 1;
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ }
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, get_Load_mem(node), env->mode);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
}
/* base is an constant address */
- if (offs) {
- add_ia32_am_offs(new_op, offs);
+ if (is_imm) {
+ if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
+ }
+ else {
+ add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
+ }
+
am_flav = ia32_O;
}
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *val = get_Store_value(node);
ir_node *ptr = get_Store_ptr(node);
+ ir_node *sptr = ptr;
ir_node *mem = get_Store_mem(node);
ir_mode *mode = get_irn_mode(val);
ir_node *sval = val;
- const char *offs = NULL;
+ int is_imm = 0;
ir_node *new_op;
ia32_am_flavour_t am_flav = ia32_B;
- ia32_immop_type_t immop = ia32_ImmNone;
-
- /* in case of storing a const (but not a symconst) -> make it an attribute */
- if (is_ia32_Cnst(val)) {
- switch (get_ia32_op_type(val)) {
- case ia32_Const:
- immop = ia32_ImmConst;
- break;
- case ia32_SymConst:
- immop = ia32_ImmSymConst;
- break;
- default:
- assert(0 && "unsupported Const type");
+ ia32_immop_type_t immop = ia32_ImmNone;
+
+ if (! mode_is_float(mode)) {
+ /* in case of storing a const (but not a symconst) -> make it an attribute */
+ if (is_ia32_Cnst(val)) {
+ switch (get_ia32_op_type(val)) {
+ case ia32_Const:
+ immop = ia32_ImmConst;
+ break;
+ case ia32_SymConst:
+ immop = ia32_ImmSymConst;
+ break;
+ default:
+ assert(0 && "unsupported Const type");
+ }
+ sval = noreg;
}
- sval = noreg;
}
/* address might be a constant (symconst or absolute address) */
if (is_ia32_Const(ptr)) {
- offs = get_ia32_cnst(ptr);
- ptr = noreg;
+ sptr = noreg;
+ is_imm = 0;
}
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
- else
- new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
+ else {
+ env->cg->used_x87 = 1;
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
+ }
}
else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
}
else {
new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
}
/* stored const is an attribute (saves a register) */
- if (is_ia32_Cnst(val)) {
+ if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
set_ia32_Immop_attr(new_op, val);
}
/* base is an constant address */
- if (offs) {
- add_ia32_am_offs(new_op, offs);
+ if (is_imm) {
+ if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
+ }
+ else {
+ add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
+ }
+
am_flav = ia32_O;
}
}
if (mode_is_float(get_irn_mode(expr))) {
- res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+ else {
+ env->cg->used_x87 = 1;
+ assert(0);
+ }
}
else {
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
}
else {
if (mode_is_float(get_irn_mode(cmp_a))) {
- res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+ else {
+ env->cg->used_x87 = 1;
+ assert(0);
+ }
}
else {
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
ir_node *new_op = NULL;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_rd_NoMem(irg);
- firm_dbg_module_t *mod = env->mod;
ir_node *proj;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
if (src_mode == tgt_mode) {
/* this can happen when changing mode_P to mode_Is */
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- else
+ else {
+ env->cg->used_x87 = 1;
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- else
+ else {
+ env->cg->used_x87 = 1;
new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ }
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
if (mode_is_float(mode)) {
if (USE_SSE2(env->cg))
new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
- else
+ else {
+ env->cg->used_x87 = 1;
new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ }
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
tenv.dbg = get_irn_dbg_info(irn);
tenv.irg = cg->irg;
tenv.irn = irn;
- tenv.mod = cg->mod;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
tenv.mode = get_ia32_res_mode(irn);
tenv.cg = cg;
tenv.dbg = get_irn_dbg_info(irn);
tenv.irg = cg->irg;
tenv.irn = irn;
- tenv.mod = cg->mod;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
tenv.mode = get_irn_mode(irn);
tenv.cg = cg;
tenv.dbg = get_irn_dbg_info(node);
tenv.irg = current_ir_graph;
tenv.irn = node;
- tenv.mod = cgenv->mod;
+ DEBUG_ONLY(tenv.mod = cgenv->mod;)
tenv.mode = get_irn_mode(node);
tenv.cg = cgenv;