#define SFP_ABS "0x7FFFFFFF"
#define DFP_ABS "0x7FFFFFFFFFFFFFFF"
#define DFP_INTMAX "9223372036854775807"
+#define ULL_BIAS "18446744073709551616"
#define TP_SFP_SIGN "ia32_sfp_sign"
#define TP_DFP_SIGN "ia32_dfp_sign"
#define TP_SFP_ABS "ia32_sfp_abs"
#define TP_DFP_ABS "ia32_dfp_abs"
-#define TP_INT_MAX "ia32_int_max"
+#define TP_ULL_BIAS "ia32_ull_bias"
-#define ENT_SFP_SIGN "IA32_SFP_SIGN"
-#define ENT_DFP_SIGN "IA32_DFP_SIGN"
-#define ENT_SFP_ABS "IA32_SFP_ABS"
-#define ENT_DFP_ABS "IA32_DFP_ABS"
-#define ENT_INT_MAX "IA32_INT_MAX"
+#define ENT_SFP_SIGN ".LC_ia32_sfp_sign"
+#define ENT_DFP_SIGN ".LC_ia32_dfp_sign"
+#define ENT_SFP_ABS ".LC_ia32_sfp_abs"
+#define ENT_DFP_ABS ".LC_ia32_dfp_abs"
+#define ENT_ULL_BIAS ".LC_ia32_ull_bias"
#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
extern ir_op *get_op_Mulh(void);
-typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
- ir_node *op1, ir_node *op2);
+typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
+ ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
+ ir_node *op2);
-typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
- ir_node *op1, ir_node *op2, ir_node *flags);
+typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_node *block,
+ ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
+ ir_node *flags);
-typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *op1, ir_node *op2);
+typedef ir_node *construct_shift_func(dbg_info *db, ir_node *block,
+ ir_node *op1, ir_node *op2);
-typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
- ir_node *op);
+typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_node *block,
+ ir_node *base, ir_node *index, ir_node *mem, ir_node *op);
-typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
+typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_node *block,
+ ir_node *base, ir_node *index, ir_node *mem);
-typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
- ir_node *op1, ir_node *op2, ir_node *fpcw);
+typedef ir_node *construct_binop_float_func(dbg_info *db, ir_node *block,
+ ir_node *base, ir_node *index, ir_node *mem, ir_node *op1, ir_node *op2,
+ ir_node *fpcw);
-typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *op);
+typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
static ir_node *create_immediate_or_transform(ir_node *node,
char immediate_constraint_type);
*/
static ir_node *gen_Const(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- ir_node *old_block = get_nodes_block(node);
- ir_node *block = be_transform_node(old_block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
+ ir_node *old_block = get_nodes_block(node);
+ ir_node *block = be_transform_node(old_block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
assert(is_Const(node));
if (ia32_cg_config.use_sse2) {
tarval *tv = get_Const_tarval(node);
if (tarval_is_null(tv)) {
- load = new_rd_ia32_xZero(dbgi, irg, block);
+ load = new_bd_ia32_xZero(dbgi, block);
set_ia32_ls_mode(load, mode);
res = load;
} else if (tarval_is_one(tv)) {
ir_node *imm2 = create_Immediate(NULL, 0, 2);
ir_node *pslld, *psrld;
- load = new_rd_ia32_xAllOnes(dbgi, irg, block);
+ load = new_bd_ia32_xAllOnes(dbgi, block);
set_ia32_ls_mode(load, mode);
- pslld = new_rd_ia32_xPslld(dbgi, irg, block, load, imm1);
+ pslld = new_bd_ia32_xPslld(dbgi, block, load, imm1);
set_ia32_ls_mode(pslld, mode);
- psrld = new_rd_ia32_xPsrld(dbgi, irg, block, pslld, imm2);
+ psrld = new_bd_ia32_xPsrld(dbgi, block, pslld, imm2);
set_ia32_ls_mode(psrld, mode);
res = psrld;
} else if (mode == mode_F) {
(get_tarval_sub_bits(tv, 1) << 8) |
(get_tarval_sub_bits(tv, 2) << 16) |
(get_tarval_sub_bits(tv, 3) << 24);
- ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
- load = new_rd_ia32_xMovd(dbgi, irg, block, cnst);
+ ir_node *cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val);
+ load = new_bd_ia32_xMovd(dbgi, block, cnst);
set_ia32_ls_mode(load, mode);
res = load;
} else {
(get_tarval_sub_bits(tv, 5) << 8) |
(get_tarval_sub_bits(tv, 6) << 16) |
(get_tarval_sub_bits(tv, 7) << 24);
- cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
- load = new_rd_ia32_xMovd(dbgi, irg, block, cnst);
+ cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val);
+ load = new_bd_ia32_xMovd(dbgi, block, cnst);
set_ia32_ls_mode(load, mode);
- psllq = new_rd_ia32_xPsllq(dbgi, irg, block, load, imm32);
+ psllq = new_bd_ia32_xPsllq(dbgi, block, load, imm32);
set_ia32_ls_mode(psllq, mode);
res = psllq;
goto end;
}
floatent = create_float_const_entity(node);
- load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
+ load = new_bd_ia32_xLoad(dbgi, block, noreg, noreg, nomem,
mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
- set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
- res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
+ arch_irn_add_flags(load, arch_irn_flags_rematerializable);
+ res = new_r_Proj(current_ir_graph, block, load, mode_xmm, pn_ia32_xLoad_res);
}
} else {
if (is_Const_null(node)) {
- load = new_rd_ia32_vfldz(dbgi, irg, block);
+ load = new_bd_ia32_vfldz(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else if (is_Const_one(node)) {
- load = new_rd_ia32_vfld1(dbgi, irg, block);
+ load = new_bd_ia32_vfld1(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else {
floatent = create_float_const_entity(node);
- load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
+ load = new_bd_ia32_vfld(dbgi, block, noreg, noreg, nomem, mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
- set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
- res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
+ arch_irn_add_flags(load, arch_irn_flags_rematerializable);
+ res = new_r_Proj(current_ir_graph, block, load, mode_vfp, pn_ia32_vfld_res);
/* take the mode from the entity */
set_ia32_ls_mode(load, get_type_mode(get_entity_type(floatent)));
}
}
end:
- SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(load, node);
be_dep_on_frame(load);
return res;
}
val = get_tarval_long(tv);
- cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
- SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
+ cnst = new_bd_ia32_Const(dbgi, block, NULL, 0, val);
+ SET_IA32_ORIG_NODE(cnst, node);
be_dep_on_frame(cnst);
return cnst;
*/
static ir_node *gen_SymConst(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
ir_node *old_block = get_nodes_block(node);
ir_node *block = be_transform_node(old_block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *nomem = new_NoMem();
if (ia32_cg_config.use_sse2)
- cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
+ cnst = new_bd_ia32_xLoad(dbgi, block, noreg, noreg, nomem, mode_E);
else
- cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
+ cnst = new_bd_ia32_vfld(dbgi, block, noreg, noreg, nomem, mode_E);
set_ia32_am_sc(cnst, get_SymConst_entity(node));
set_ia32_use_frame(cnst);
} else {
panic("backend only support symconst_addr_ent (at %+F)", node);
}
entity = get_SymConst_entity(node);
- cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
+ cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0);
}
- SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(cnst, node);
be_dep_on_frame(cnst);
return cnst;
{ TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
{ TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
{ TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
- { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
+ { TP_ULL_BIAS, ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
};
static ir_entity *ent_cache[ia32_known_const_max];
const char *tp_name, *ent_name, *cnst_str;
ir_type *tp;
- ir_node *cnst;
- ir_graph *rem;
ir_entity *ent;
tarval *tv;
ir_mode *mode;
/* set the specified alignment */
set_type_alignment_bytes(tp, names[kct].align);
+ if (kct == ia32_ULLBIAS) {
+ /* we are in the backend, construct a fixed type here */
+ unsigned size = get_type_size_bytes(tp);
+ tp = new_type_array(new_id_from_str(tp_name), 1, tp);
+ set_type_alignment_bytes(tp, names[kct].align);
+ set_type_size_bytes(tp, 2 * size);
+ set_type_state(tp, layout_fixed);
+ }
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
set_entity_ld_ident(ent, get_entity_ident(ent));
set_entity_variability(ent, variability_constant);
set_entity_allocation(ent, allocation_static);
- /* we create a new entity here: It's initialization must resist on the
- const code irg */
- rem = current_ir_graph;
- current_ir_graph = get_const_code_irg();
- cnst = new_Const(mode, tv);
- current_ir_graph = rem;
+ if (kct == ia32_ULLBIAS) {
+ ir_initializer_t *initializer = create_initializer_compound(2);
- set_atomic_ent_value(ent, cnst);
+ set_initializer_compound_value(initializer, 0,
+ create_initializer_tarval(get_tarval_null(mode)));
+ set_initializer_compound_value(initializer, 1,
+ create_initializer_tarval(tv));
+
+ set_entity_initializer(ent, initializer);
+ } else {
+ set_entity_initializer(ent, create_initializer_tarval(tv));
+ }
/* cache the entry */
ent_cache[kct] = ent;
/* construct load address */
memset(addr, 0, sizeof(addr[0]));
- ia32_create_address_mode(addr, ptr, /*force=*/0);
+ ia32_create_address_mode(addr, ptr, 0);
noreg_gp = ia32_new_NoReg_gp(env_cg);
addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
addr->mem = be_transform_node(mem);
}
-static void build_address(ia32_address_mode_t *am, ir_node *node)
+static void build_address(ia32_address_mode_t *am, ir_node *node,
+ ia32_create_am_flags_t flags)
{
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ia32_address_t *addr = &am->addr;
am->am_node = node;
/* construct load address */
- ia32_create_address_mode(addr, ptr, /*force=*/0);
+ ia32_create_address_mode(addr, ptr, flags);
addr->base = addr->base ? be_transform_node(addr->base) : noreg_gp;
addr->index = addr->index ? be_transform_node(addr->index) : noreg_gp;
src_mode = get_irn_mode(get_Conv_op(node));
dest_mode = get_irn_mode(node);
- return ia32_mode_needs_gp_reg(src_mode)
- && ia32_mode_needs_gp_reg(dest_mode)
- && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
+ return
+ ia32_mode_needs_gp_reg(src_mode) &&
+ ia32_mode_needs_gp_reg(dest_mode) &&
+ get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
}
/* Skip all Down-Conv's on a given node and return the resulting node. */
assert(use_am || !(flags & match_8bit_am));
assert(use_am || !(flags & match_16bit_am));
- if (mode_bits == 8) {
- if (!(flags & match_8bit_am))
- use_am = 0;
- /* we don't automatically add upconvs yet */
- assert((flags & match_mode_neutral) || (flags & match_8bit));
- } else if (mode_bits == 16) {
- if (!(flags & match_16bit_am))
- use_am = 0;
- /* we don't automatically add upconvs yet */
- assert((flags & match_mode_neutral) || (flags & match_16bit));
+ if ((mode_bits == 8 && !(flags & match_8bit_am)) ||
+ (mode_bits == 16 && !(flags & match_16bit_am))) {
+ use_am = 0;
}
/* we can simply skip downconvs for mode neutral nodes: the upper bits
noreg_gp = ia32_new_NoReg_gp(env_cg);
if (new_op2 == NULL &&
use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
- build_address(am, op2);
+ build_address(am, op2, 0);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (mode_is_float(mode)) {
new_op2 = ia32_new_NoReg_vfp(env_cg);
use_am &&
ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
ir_node *noreg;
- build_address(am, op1);
+ build_address(am, op1, 0);
if (mode_is_float(mode)) {
noreg = ia32_new_NoReg_vfp(env_cg);
dbgi = get_irn_dbg_info(node);
new_block = be_transform_node(block);
- new_node = func(dbgi, current_ir_graph, new_block,
- addr->base, addr->index, addr->mem,
- am.new_op1, am.new_op2);
+ new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
+ am.new_op1, am.new_op2);
set_am_attributes(new_node, &am);
/* we can't use source address mode anymore when using immediates */
if (!(flags & match_am_and_immediates) &&
(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
set_ia32_am_support(new_node, ia32_am_none);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
dbgi = get_irn_dbg_info(node);
block = be_transform_node(src_block);
new_eflags = be_transform_node(eflags);
- new_node = func(dbgi, current_ir_graph, block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2, new_eflags);
+ new_node = func(dbgi, block, addr->base, addr->index, addr->mem,
+ am.new_op1, am.new_op2, new_eflags);
set_am_attributes(new_node, &am);
/* we can't use source address mode anymore when using immediates */
if (!(flags & match_am_and_immediates) &&
(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2)))
set_ia32_am_support(new_node, ia32_am_none);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
dbgi = get_irn_dbg_info(node);
new_block = be_transform_node(block);
- new_node = func(dbgi, current_ir_graph, new_block,
- addr->base, addr->index, addr->mem,
- am.new_op1, am.new_op2, get_fpcw());
+ new_node = func(dbgi, new_block, addr->base, addr->index, addr->mem,
+ am.new_op1, am.new_op2, get_fpcw());
set_am_attributes(new_node, &am);
attr = get_ia32_x87_attr(new_node);
attr->attr.data.ins_permuted = am.ins_permuted;
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
new_block = be_transform_node(block);
- new_node = func(dbgi, current_ir_graph, new_block, new_op1, new_op2);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = func(dbgi, new_block, new_op1, new_op2);
+ SET_IA32_ORIG_NODE(new_node, node);
/* lowered shift instruction may have a dependency operand, handle it here */
if (get_irn_arity(node) == 3) {
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
new_block = be_transform_node(block);
- new_node = func(dbgi, current_ir_graph, new_block, new_op);
+ new_node = func(dbgi, new_block, new_op);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
index = be_transform_node(index);
}
- res = new_rd_ia32_Lea(dbgi, current_ir_graph, block, base, index);
+ res = new_bd_ia32_Lea(dbgi, block, base, index);
set_address(res, addr);
return res;
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
- return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
+ return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
}
ia32_mark_non_am(node);
* 3. Otherwise -> Lea
*/
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, node, /*force=*/1);
+ ia32_create_address_mode(&addr, node, ia32_create_am_force);
add_immediate_op = NULL;
dbgi = get_irn_dbg_info(node);
/* a constant? */
if (addr.base == NULL && addr.index == NULL) {
- ir_graph *irg = current_ir_graph;
- new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
+ new_node = new_bd_ia32_Const(dbgi, new_block, addr.symconst_ent,
addr.symconst_sign, addr.offset);
be_dep_on_frame(new_node);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
/* add with immediate? */
}
new_node = create_lea_from_address(dbgi, new_block, &addr);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
/* construct an Add with source address mode */
if (am.op_type == ia32_AddrModeS) {
- ir_graph *irg = current_ir_graph;
ia32_address_t *am_addr = &am.addr;
- new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
+ new_node = new_bd_ia32_Add(dbgi, new_block, am_addr->base,
am_addr->index, am_addr->mem, am.new_op1,
am.new_op2);
set_am_attributes(new_node, &am);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
/* otherwise construct a lea */
new_node = create_lea_from_address(dbgi, new_block, &addr);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
- return gen_binop(node, op1, op2, new_rd_ia32_xMul,
+ return gen_binop(node, op1, op2, new_bd_ia32_xMul,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
}
- return gen_binop(node, op1, op2, new_rd_ia32_IMul,
+ return gen_binop(node, op1, op2, new_bd_ia32_IMul,
match_commutative | match_am | match_mode_neutral |
match_immediate | match_am_and_immediates);
}
ir_node *proj_res_high;
if (mode_is_signed(mode)) {
- new_node = gen_binop(node, op1, op2, new_rd_ia32_IMul1OP, match_commutative | match_am);
+ new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node,
mode_Iu, pn_ia32_IMul1OP_res_high);
} else {
- new_node = gen_binop(node, op1, op2, new_rd_ia32_Mul, match_commutative | match_am);
+ new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
proj_res_high = new_rd_Proj(dbgi, current_ir_graph, new_block, new_node,
mode_Iu, pn_ia32_Mul_res_high);
}
return res;
}
}
- return gen_binop(node, op1, op2, new_rd_ia32_And,
- match_commutative | match_mode_neutral | match_am
- | match_immediate);
+ return gen_binop(node, op1, op2, new_bd_ia32_And,
+ match_commutative | match_mode_neutral | match_am | match_immediate);
}
ir_node *op2 = get_Or_right(node);
assert (! mode_is_float(get_irn_mode(node)));
- return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
+ return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
| match_mode_neutral | match_am | match_immediate);
}
ir_node *op2 = get_Eor_right(node);
assert(! mode_is_float(get_irn_mode(node)));
- return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
+ return gen_binop(node, op1, op2, new_bd_ia32_Xor, match_commutative
| match_mode_neutral | match_am | match_immediate);
}
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
- return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
+ return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
}
if (is_Const(op2)) {
node);
}
- return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
+ return gen_binop(node, op1, op2, new_bd_ia32_Sub, match_mode_neutral
| match_am | match_immediate);
}
NEW_ARR_A(ir_node*, ins, arity + 1);
+ /* NOTE: This sometimes produces dead-code because the old sync in
+ * src_mem might not be used anymore, we should detect this case
+ * and kill the sync... */
for (i = arity - 1; i >= 0; --i) {
ir_node *const pred = get_Sync_pred(src_mem, i);
}
}
+static ir_node *create_sex_32_64(dbg_info *dbgi, ir_node *block,
+ ir_node *val, const ir_node *orig)
+{
+ ir_node *res;
+
+ (void)orig;
+ if (ia32_cg_config.use_short_sex_eax) {
+ ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
+ be_dep_on_frame(pval);
+ res = new_bd_ia32_Cltd(dbgi, block, val, pval);
+ } else {
+ ir_node *imm31 = create_Immediate(NULL, 0, 31);
+ res = new_bd_ia32_Sar(dbgi, block, val, imm31);
+ }
+ SET_IA32_ORIG_NODE(res, orig);
+ return res;
+}
+
/**
* Generates an ia32 DivMod with additional infrastructure for the
* register allocator if needed.
*/
static ir_node *create_Div(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
/* Beware: We don't need a Sync, if the memory predecessor of the Div node
is the memory of the consumed address. We can have only the second op as address
in Div nodes, so check only op2. */
- new_mem = transform_AM_mem(irg, block, op2, mem, addr->mem);
+ new_mem = transform_AM_mem(current_ir_graph, block, op2, mem, addr->mem);
if (mode_is_signed(mode)) {
- ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
- be_dep_on_frame(produceval);
- sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
- produceval);
-
- new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
- addr->index, new_mem, am.new_op2,
- am.new_op1, sign_extension);
+ sign_extension = create_sex_32_64(dbgi, new_block, am.new_op1, node);
+ new_node = new_bd_ia32_IDiv(dbgi, new_block, addr->base,
+ addr->index, new_mem, am.new_op2, am.new_op1, sign_extension);
} else {
- sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
+ sign_extension = new_bd_ia32_Const(dbgi, new_block, NULL, 0, 0);
be_dep_on_frame(sign_extension);
- new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
+ new_node = new_bd_ia32_Div(dbgi, new_block, addr->base,
addr->index, new_mem, am.new_op2,
am.new_op1, sign_extension);
}
set_irn_pinned(new_node, get_irn_pinned(node));
set_am_attributes(new_node, &am);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
ir_node *op2 = get_Quot_right(node);
if (ia32_cg_config.use_sse2) {
- return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
+ return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
} else {
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
}
}
ir_node *left = get_Shl_left(node);
ir_node *right = get_Shl_right(node);
- return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
+ return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
match_mode_neutral | match_immediate);
}
ir_node *left = get_Shr_left(node);
ir_node *right = get_Shr_right(node);
- return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
+ return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
}
long val = get_tarval_long(tv);
if (val == 31) {
/* this is a sign extension */
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = left;
- ir_node *new_op = be_transform_node(op);
- ir_node *pval = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ ir_node *new_op = be_transform_node(left);
- be_dep_on_frame(pval);
- return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
+ return create_sex_32_64(dbgi, block, new_op, node);
}
}
}
}
- return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
+ return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
}
*/
static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2)
{
- return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
+ return gen_shift_binop(node, op1, op2, new_bd_ia32_Rol, match_immediate);
}
*/
static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2)
{
- return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
+ return gen_shift_binop(node, op1, op2, new_bd_ia32_Ror, match_immediate);
}
{
ir_node *op = get_Minus_op(node);
ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_irn_mode(node);
ir_entity *ent;
* several AM nodes... */
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *nomem = new_NoMem();
- new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
+ new_node = new_bd_ia32_xXor(dbgi, block, noreg_gp, noreg_gp,
nomem, new_op, noreg_xmm);
size = get_mode_size_bits(mode);
set_ia32_op_type(new_node, ia32_AddrModeS);
set_ia32_ls_mode(new_node, mode);
} else {
- new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
+ new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
}
} else {
- new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
+ new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
}
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
assert(get_irn_mode(node) != mode_b); /* should be lowered already */
assert (! mode_is_float(get_irn_mode(node)));
- return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
+ return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
}
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_node *op = get_Abs_op(node);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_irn_mode(node);
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
if (ia32_cg_config.use_sse2) {
ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
- new_node = new_rd_ia32_xAnd(dbgi,irg, new_block, noreg_gp, noreg_gp,
+ new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_gp, noreg_gp,
nomem, new_op, noreg_fp);
size = get_mode_size_bits(mode);
set_ia32_am_sc(new_node, ent);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
set_ia32_op_type(new_node, ia32_AddrModeS);
set_ia32_ls_mode(new_node, mode);
} else {
- new_node = new_rd_ia32_vfabs(dbgi, irg, new_block, new_op);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
+ SET_IA32_ORIG_NODE(new_node, node);
}
} else {
- ir_node *xor, *pval, *sign_extension;
+ ir_node *xor, *sign_extension;
if (get_mode_size_bits(mode) == 32) {
new_op = be_transform_node(op);
new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
}
- pval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
- sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block,
- new_op, pval);
+ sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
- be_dep_on_frame(pval);
- SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
-
- xor = new_rd_ia32_Xor(dbgi, irg, new_block, noreg_gp, noreg_gp,
+ xor = new_bd_ia32_Xor(dbgi, new_block, noreg_gp, noreg_gp,
nomem, new_op, sign_extension);
- SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(xor, node);
- new_node = new_rd_ia32_Sub(dbgi, irg, new_block, noreg_gp, noreg_gp,
+ new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_gp, noreg_gp,
nomem, xor, sign_extension);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
}
return new_node;
ir_node *op1 = be_transform_node(x);
ir_node *op2 = be_transform_node(n);
- return new_rd_ia32_Bt(dbgi, current_ir_graph, new_block, op1, op2);
+ return new_bd_ia32_Bt(dbgi, new_block, op1, op2);
}
/**
new_op = be_transform_node(node);
noreg = ia32_new_NoReg_gp(env_cg);
nomem = new_NoMem();
- flags = new_rd_ia32_Test(dbgi, current_ir_graph, new_block, noreg, noreg, nomem,
- new_op, new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
+ flags = new_bd_ia32_Test(dbgi, new_block, noreg, noreg, nomem, new_op,
+ new_op, /*is_permuted=*/0, /*cmp_unsigned=*/0);
*pnc_out = pn_Cmp_Lg;
return flags;
}
ir_node *new_mem = be_transform_node(mem);
ir_node *base;
ir_node *index;
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_mode *mode = get_Load_mode(node);
/* construct load address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, /*force=*/0);
+ ia32_create_address_mode(&addr, ptr, 0);
base = addr.base;
index = addr.index;
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2) {
- new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
+ new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
mode);
res_mode = mode_xmm;
} else {
- new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
+ new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
mode);
res_mode = mode_vfp;
}
/* create a conv node with address mode for smaller modes */
if (get_mode_size_bits(mode) < 32) {
- new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
+ new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
new_mem, noreg, mode);
} else {
- new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
+ new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
}
res_mode = mode_Iu;
}
set_address(new_node, &addr);
if (get_irn_pinned(node) == op_pin_state_floats) {
- add_ia32_flags(new_node, arch_irn_flags_rematerializable);
+ assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
+ && pn_ia32_vfld_res == pn_ia32_Load_res
+ && pn_ia32_Load_res == pn_ia32_res);
+ arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
}
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
be_dep_on_frame(new_node);
return new_node;
return 0;
}
- if (is_Sync(mem)) {
- int i;
-
- for (i = get_Sync_n_preds(mem) - 1; i >= 0; --i) {
- ir_node *const pred = get_Sync_pred(mem, i);
-
- if (is_Proj(pred) && get_Proj_pred(pred) == load)
- continue;
-
- if (get_nodes_block(pred) == block &&
- heights_reachable_in_block(heights, pred, load)) {
- return 0;
- }
- }
- } else {
- /* Store should be attached to the load */
- if (!is_Proj(mem) || get_Proj_pred(mem) != load)
- return 0;
- }
+ if (prevents_AM(block, load, mem))
+ return 0;
+ /* Store should be attached to the load via mem */
+ assert(heights_reachable_in_block(heights, mem, load));
return 1;
}
ir_node *src_block = get_nodes_block(node);
ir_node *block;
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi;
ir_node *new_mem;
ir_node *new_node;
ia32_address_t *addr = &am.addr;
memset(&am, 0, sizeof(am));
- assert(flags & match_dest_am);
assert(flags & match_immediate); /* there is no destam node without... */
commutative = (flags & match_commutative) != 0;
if (use_dest_am(src_block, op1, mem, ptr, op2)) {
- build_address(&am, op1);
+ build_address(&am, op1, ia32_create_am_double_use);
new_op = create_immediate_or_transform(op2, 0);
} else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
- build_address(&am, op2);
+ build_address(&am, op2, ia32_create_am_double_use);
new_op = create_immediate_or_transform(op1, 0);
} else {
return NULL;
dbgi = get_irn_dbg_info(node);
block = be_transform_node(src_block);
- new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem);
+ new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem);
if (get_mode_size_bits(mode) == 8) {
- new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
- new_mem, new_op);
+ new_node = func8bit(dbgi, block, addr->base, addr->index, new_mem, new_op);
} else {
- new_node = func(dbgi, irg, block, addr->base, addr->index, new_mem,
- new_op);
+ new_node = func(dbgi, block, addr->base, addr->index, new_mem, new_op);
}
set_address(new_node, addr);
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
mem_proj = be_transform_node(am.mem_proj);
ir_node *ptr, ir_mode *mode,
construct_unop_dest_func *func)
{
- ir_graph *irg = current_ir_graph;
ir_node *src_block = get_nodes_block(node);
ir_node *block;
dbg_info *dbgi;
ir_node *mem_proj;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
- memset(&am, 0, sizeof(am));
if (!use_dest_am(src_block, op, mem, ptr, NULL))
return NULL;
- build_address(&am, op);
+ memset(&am, 0, sizeof(am));
+ build_address(&am, op, ia32_create_am_double_use);
dbgi = get_irn_dbg_info(node);
block = be_transform_node(src_block);
- new_mem = transform_AM_mem(irg, block, am.am_node, mem, addr->mem);
- new_node = func(dbgi, irg, block, addr->base, addr->index, new_mem);
+ new_mem = transform_AM_mem(current_ir_graph, block, am.am_node, mem, addr->mem);
+ new_node = func(dbgi, block, addr->base, addr->index, new_mem);
set_address(new_node, addr);
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
mem_proj = be_transform_node(am.mem_proj);
ir_mode *mode = get_irn_mode(node);
ir_node *mux_true = get_Mux_true(node);
ir_node *mux_false = get_Mux_false(node);
- ir_graph *irg;
ir_node *cond;
ir_node *new_mem;
dbg_info *dbgi;
build_address_ptr(&addr, ptr, mem);
- irg = current_ir_graph;
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
new_block = be_transform_node(block);
cond = get_Mux_sel(node);
flags = get_flags_node(cond, &pnc);
new_mem = be_transform_node(mem);
- new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
+ new_node = new_bd_ia32_SetMem(dbgi, new_block, addr.base,
addr.index, addr.mem, flags, pnc, negated);
set_address(new_node, &addr);
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
case iro_Add:
op1 = get_Add_left(val);
op2 = get_Add_right(val);
- if (is_Const_1(op2)) {
- new_node = dest_am_unop(val, op1, mem, ptr, mode,
- new_rd_ia32_IncMem);
- break;
- } else if (is_Const_Minus_1(op2)) {
- new_node = dest_am_unop(val, op1, mem, ptr, mode,
- new_rd_ia32_DecMem);
- break;
+ if (ia32_cg_config.use_incdec) {
+ if (is_Const_1(op2)) {
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_IncMem);
+ break;
+ } else if (is_Const_Minus_1(op2)) {
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_DecMem);
+ break;
+ }
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
- match_dest_am | match_commutative |
- match_immediate);
+ new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
+ match_commutative | match_immediate);
break;
case iro_Sub:
op1 = get_Sub_left(val);
ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
- match_dest_am | match_immediate |
+ new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
match_immediate);
break;
case iro_And:
op1 = get_And_left(val);
op2 = get_And_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
- match_dest_am | match_commutative |
- match_immediate);
+ new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
+ match_commutative | match_immediate);
break;
case iro_Or:
op1 = get_Or_left(val);
op2 = get_Or_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
- match_dest_am | match_commutative |
- match_immediate);
+ new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
+ match_commutative | match_immediate);
break;
case iro_Eor:
op1 = get_Eor_left(val);
op2 = get_Eor_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
- match_dest_am | match_commutative |
- match_immediate);
+ new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
+ match_commutative | match_immediate);
break;
case iro_Shl:
op1 = get_Shl_left(val);
op2 = get_Shl_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
- match_dest_am | match_immediate);
+ new_bd_ia32_ShlMem, new_bd_ia32_ShlMem,
+ match_immediate);
break;
case iro_Shr:
op1 = get_Shr_left(val);
op2 = get_Shr_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
- match_dest_am | match_immediate);
+ new_bd_ia32_ShrMem, new_bd_ia32_ShrMem,
+ match_immediate);
break;
case iro_Shrs:
op1 = get_Shrs_left(val);
op2 = get_Shrs_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_SarMem, new_rd_ia32_SarMem,
- match_dest_am | match_immediate);
+ new_bd_ia32_SarMem, new_bd_ia32_SarMem,
+ match_immediate);
break;
case iro_Rotl:
op1 = get_Rotl_left(val);
op2 = get_Rotl_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_rd_ia32_RolMem, new_rd_ia32_RolMem,
- match_dest_am | match_immediate);
+ new_bd_ia32_RolMem, new_bd_ia32_RolMem,
+ match_immediate);
break;
/* TODO: match ROR patterns... */
case iro_Mux:
break;
case iro_Minus:
op1 = get_Minus_op(val);
- new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NegMem);
break;
case iro_Not:
/* should be lowered already */
assert(mode != mode_b);
op1 = get_Not_op(val);
- new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_bd_ia32_NotMem);
break;
default:
return NULL;
return new_node;
}
+static bool possible_int_mode_for_fp(ir_mode *mode)
+{
+ unsigned size;
+
+ if (!mode_is_signed(mode))
+ return false;
+ size = get_mode_size_bits(mode);
+ if (size != 16 && size != 32)
+ return false;
+ return true;
+}
+
static int is_float_to_int_conv(const ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
ir_node *conv_op;
ir_mode *conv_mode;
- if (mode != mode_Is && mode != mode_Hs)
+ if (!possible_int_mode_for_fp(mode))
return 0;
if (!is_Conv(node))
}
/**
- * Transform a Store(floatConst).
+ * Transform a Store(floatConst) into a sequence of
+ * integer stores.
*
* @return the created ia32 Store node
*/
ir_node *new_block = be_transform_node(block);
ir_node *ptr = get_Store_ptr(node);
ir_node *mem = get_Store_mem(node);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
int ofs = 0;
size_t i = 0;
(get_tarval_sub_bits(tv, ofs + 3) << 24);
ir_node *imm = create_Immediate(NULL, 0, val);
- ir_node *new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
+ ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, imm);
set_irn_pinned(new_node, get_irn_pinned(node));
set_ia32_op_type(new_node, ia32_AddrModeD);
set_ia32_ls_mode(new_node, mode_Iu);
set_address(new_node, &addr);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
+ assert(i < 4);
ins[i++] = new_node;
size -= 4;
addr.offset += 4;
} while (size != 0);
- return i == 1 ? ins[0] : new_rd_Sync(dbgi, irg, new_block, i, ins);
+ if (i > 1) {
+ return new_rd_Sync(dbgi, current_ir_graph, new_block, i, ins);
+ } else {
+ return ins[0];
+ }
}
/**
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp];
- ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val);
+ ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res);
be_new_Keep(reg_class, irg, block, 1, &value);
ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
/* do a fist */
- new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode);
+ new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
*fist = new_node;
}
return new_node;
}
/**
- * Transforms a normal Store.
+ * Transforms a general (no special case) Store.
*
* @return the created ia32 Store node
*/
-static ir_node *gen_normal_Store(ir_node *node)
+static ir_node *gen_general_Store(ir_node *node)
{
ir_node *val = get_Store_value(node);
ir_mode *mode = get_irn_mode(val);
ir_node *new_block = be_transform_node(block);
ir_node *ptr = get_Store_ptr(node);
ir_node *mem = get_Store_mem(node);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *new_val, *new_node, *store;
/* construct store address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, /*force=*/0);
+ ia32_create_address_mode(&addr, ptr, 0);
if (addr.base == NULL) {
addr.base = noreg;
}
new_val = be_transform_node(val);
if (ia32_cg_config.use_sse2) {
- new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
+ new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val);
} else {
- new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
+ new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
store = new_node;
val = op;
}
new_val = be_transform_node(val);
- new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store);
+ new_node = gen_vfist(dbgi, current_ir_graph, new_block, addr.base, addr.index, addr.mem, new_val, &store);
} else {
new_val = create_immediate_or_transform(val, 0);
assert(mode != mode_b);
if (get_mode_size_bits(mode) == 8) {
- new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
+ new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val);
} else {
- new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
+ new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val);
}
store = new_node;
set_ia32_ls_mode(store, mode);
set_address(store, &addr);
- SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(store, node);
return new_node;
}
ir_mode *mode = get_irn_mode(val);
if (mode_is_float(mode) && is_Const(val)) {
- int transform;
-
- /* we are storing a floating point constant */
- if (ia32_cg_config.use_sse2) {
- transform = !is_simple_sse_Const(val);
- } else {
- transform = !is_simple_x87_Const(val);
- }
- if (transform)
- return gen_float_const_Store(node, val);
+ /* We can transform every floating const store
+ into a sequence of integer stores.
+ If the constant is already in a register,
+ it would be better to use it, but we don't
+ have this information here. */
+ return gen_float_const_Store(node, val);
}
- return gen_normal_Store(node);
+ return gen_general_Store(node);
}
/**
*/
static ir_node *create_Switch(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *sel = get_Cond_selector(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
/* if smallest switch case is not 0 we need an additional sub */
- new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
+ new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg);
add_ia32_am_offs_int(new_sel, -switch_min);
set_ia32_op_type(new_sel, ia32_AddrModeS);
- SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_sel, node);
}
- new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel, default_pn);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *sel = get_Cond_selector(node);
ir_mode *sel_mode = get_irn_mode(sel);
/* we get flags from a Cmp */
flags = get_flags_node(sel, &pnc);
- new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = new_bd_ia32_Jcc(dbgi, new_block, flags, pnc);
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
static ir_node *create_Fucom(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
if (ia32_cg_config.use_fucomi) {
new_right = be_transform_node(right);
- new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
+ new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
new_right, 0);
set_ia32_commutative(new_node);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
} else {
if (ia32_cg_config.use_ftst && is_Const_0(right)) {
- new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
- 0);
+ new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
} else {
new_right = be_transform_node(right);
- new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
- new_right, 0);
+ new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
}
set_ia32_commutative(new_node);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
- new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
+ SET_IA32_ORIG_NODE(new_node, node);
}
return new_node;
static ir_node *create_Ucomi(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *src_block = get_nodes_block(node);
ir_node *new_block = be_transform_node(src_block);
match_arguments(&am, src_block, left, right, NULL,
match_commutative | match_am);
- new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
+ new_node = new_bd_ia32_Ucomi(dbgi, new_block, addr->base, addr->index,
addr->mem, am.new_op1, am.new_op2,
am.ins_permuted);
set_am_attributes(new_node, &am);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
if (is_Proj(transformed_node))
return upper_bits_clean(get_Proj_pred(transformed_node), mode);
- if (is_ia32_Conv_I2I(transformed_node)
- || is_ia32_Conv_I2I8Bit(transformed_node)) {
- ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
- if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
- return false;
- if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
- return false;
+ switch (get_ia32_irn_opcode(transformed_node)) {
+ case iro_ia32_Conv_I2I:
+ case iro_ia32_Conv_I2I8Bit: {
+ ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
+ if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
+ return false;
+ if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
+ return false;
- return true;
- }
-
- if (is_ia32_Shr(transformed_node) && !mode_is_signed(mode)) {
- ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
- if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
- const ia32_immediate_attr_t *attr
- = get_ia32_immediate_attr_const(right);
- if (attr->symconst == 0
- && (unsigned) attr->offset >= (32 - get_mode_size_bits(mode))) {
- return true;
- }
+ return true;
}
- return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
- }
- if (is_ia32_And(transformed_node) && !mode_is_signed(mode)) {
- ir_node *right = get_irn_n(transformed_node, n_ia32_And_right);
- if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
- const ia32_immediate_attr_t *attr
- = get_ia32_immediate_attr_const(right);
- if (attr->symconst == 0
- && (unsigned) attr->offset
- <= (0xffffffff >> (32 - get_mode_size_bits(mode)))) {
- return true;
+ case iro_ia32_Shr:
+ if (mode_is_signed(mode)) {
+ return false; /* TODO handle signed modes */
+ } else {
+ ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
+ if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
+ const ia32_immediate_attr_t *attr
+ = get_ia32_immediate_attr_const(right);
+ if (attr->symconst == 0 &&
+ (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
+ return true;
+ }
+ }
+ return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
}
- }
- /* TODO recurse? */
- }
- /* TODO recurse on Or, Xor, ... if appropriate? */
+ case iro_ia32_Sar:
+ /* TODO too conservative if shift amount is constant */
+ return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
- if (is_ia32_Immediate(transformed_node)
- || is_ia32_Const(transformed_node)) {
- const ia32_immediate_attr_t *attr
- = get_ia32_immediate_attr_const(transformed_node);
- if (mode_is_signed(mode)) {
- long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
- if (shifted == 0 || shifted == -1)
- return true;
- } else {
- unsigned long shifted = (unsigned long) attr->offset;
- shifted >>= get_mode_size_bits(mode);
- if (shifted == 0)
- return true;
+ case iro_ia32_And:
+ if (!mode_is_signed(mode)) {
+ return
+ upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
+ upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
+ }
+ /* TODO if one is known to be zero extended, then || is sufficient */
+ /* FALLTHROUGH */
+ case iro_ia32_Or:
+ case iro_ia32_Xor:
+ return
+ upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
+ upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
+
+ case iro_ia32_Const:
+ case iro_ia32_Immediate: {
+ const ia32_immediate_attr_t *attr =
+ get_ia32_immediate_attr_const(transformed_node);
+ if (mode_is_signed(mode)) {
+ long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
+ return shifted == 0 || shifted == -1;
+ } else {
+ unsigned long shifted = (unsigned long)attr->offset;
+ shifted >>= get_mode_size_bits(mode);
+ return shifted == 0;
+ }
}
- }
- return false;
+ default:
+ return false;
+ }
}
/**
*/
static ir_node *gen_Cmp(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
match_arguments(&am, block, and_left, and_right, NULL,
match_commutative |
match_am | match_8bit_am | match_16bit_am |
- match_am_and_immediates | match_immediate |
- match_8bit | match_16bit);
+ match_am_and_immediates | match_immediate);
/* use 32bit compare mode if possible since the opcode is smaller */
if (upper_bits_clean(am.new_op1, cmp_mode) &&
}
if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted,
- cmp_unsigned);
+ new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted,
+ cmp_unsigned);
} else {
- new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted,
- cmp_unsigned);
+ new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
}
} else {
/* Cmp(left, right) */
match_arguments(&am, block, left, right, NULL,
match_commutative | match_am | match_8bit_am |
match_16bit_am | match_am_and_immediates |
- match_immediate | match_8bit | match_16bit);
+ match_immediate);
/* use 32bit compare mode if possible since the opcode is smaller */
if (upper_bits_clean(am.new_op1, cmp_mode) &&
upper_bits_clean(am.new_op2, cmp_mode)) {
}
if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
+ new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
addr->index, addr->mem, am.new_op1,
am.new_op2, am.ins_permuted,
cmp_unsigned);
} else {
- new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted, cmp_unsigned);
+ new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, am.ins_permuted, cmp_unsigned);
}
}
set_am_attributes(new_node, &am);
set_ia32_ls_mode(new_node, cmp_mode);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
pn_Cmp pnc)
{
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_node *val_true = get_Mux_true(node);
ir_node *val_false = get_Mux_false(node);
ir_node *new_node;
- match_flags_t match_flags;
ia32_address_mode_t am;
ia32_address_t *addr;
addr = &am.addr;
- match_flags = match_commutative | match_am | match_16bit_am |
- match_mode_neutral;
+ match_arguments(&am, block, val_false, val_true, flags,
+ match_commutative | match_am | match_16bit_am | match_mode_neutral);
- match_arguments(&am, block, val_false, val_true, flags, match_flags);
-
- new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
+ new_node = new_bd_ia32_CMov(dbgi, new_block, addr->base, addr->index,
addr->mem, am.new_op1, am.new_op2, new_flags,
am.ins_permuted, pnc);
set_am_attributes(new_node, &am);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
int ins_permuted)
{
- ir_graph *irg = current_ir_graph;
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_mode *mode = get_irn_mode(orig_node);
- ir_node *new_node;
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
+ ir_mode *mode = get_irn_mode(orig_node);
+ ir_node *new_node;
- new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
+ new_node = new_bd_ia32_Set(dbgi, new_block, flags, pnc, ins_permuted);
+ SET_IA32_ORIG_NODE(new_node, orig_node);
/* we might need to conv the result up */
if (get_mode_size_bits(mode) > 8) {
- new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
+ new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg, noreg,
nomem, new_node, mode_Bu);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
+ SET_IA32_ORIG_NODE(new_node, orig_node);
}
return new_node;
ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem;
dbg_info *dbgi;
- new_node = gen_binop(psi, a, b, new_rd_ia32_Sub,
+ new_node = gen_binop(psi, a, b, new_bd_ia32_Sub,
match_mode_neutral | match_am | match_immediate | match_two_users);
block = get_nodes_block(new_node);
dbgi = get_irn_dbg_info(psi);
noreg = ia32_new_NoReg_gp(env_cg);
- tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ tmpreg = new_bd_ia32_ProduceVal(dbgi, block);
nomem = new_NoMem();
- sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags);
+ sbb = new_bd_ia32_Sbb(dbgi, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags);
- new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb);
+ new_node = new_bd_ia32_And(dbgi, block, noreg, noreg, nomem, new_node, sbb);
set_ia32_commutative(new_node);
return new_node;
}
if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
if (cmp_left == mux_true && cmp_right == mux_false) {
/* Mux(a <= b, a, b) => MIN */
- return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
+ return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
match_commutative | match_am | match_two_users);
} else if (cmp_left == mux_false && cmp_right == mux_true) {
/* Mux(a <= b, b, a) => MAX */
- return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
+ return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
match_commutative | match_am | match_two_users);
}
} else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
if (cmp_left == mux_true && cmp_right == mux_false) {
/* Mux(a >= b, a, b) => MAX */
- return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
+ return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMax,
match_commutative | match_am | match_two_users);
} else if (cmp_left == mux_false && cmp_right == mux_true) {
/* Mux(a >= b, b, a) => MIN */
- return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
+ return gen_binop(node, cmp_left, cmp_right, new_bd_ia32_xMin,
match_commutative | match_am | match_two_users);
}
}
} else {
set_ia32_ls_mode(fist, mode_Is);
}
- SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
+ SET_IA32_ORIG_NODE(fist, node);
/* do a Load */
- load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem);
+ load = new_bd_ia32_Load(dbgi, block, get_irg_frame(irg), noreg, mem);
set_irn_pinned(load, op_pin_state_floats);
set_ia32_use_frame(load);
ia32_attr_t *attr = get_ia32_attr(load);
attr->data.need_32bit_stackent = 1;
}
- SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
+ SET_IA32_ORIG_NODE(load, node);
return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
}
ir_node *store, *load;
ir_node *new_node;
- store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
- tgt_mode);
+ store = new_bd_ia32_vfst(dbgi, block, frame, noreg, nomem, node, tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
- SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(store, node);
- load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
- tgt_mode);
+ load = new_bd_ia32_vfld(dbgi, block, frame, noreg, store, tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
- SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(load, node);
new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
return new_node;
}
+static ir_node *create_Conv_I2I(dbg_info *dbgi, ir_node *block, ir_node *base,
+ ir_node *index, ir_node *mem, ir_node *val, ir_mode *mode)
+{
+ ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
+
+ func = get_mode_size_bits(mode) == 8 ?
+ new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
+ return func(dbgi, block, base, index, mem, val, mode);
+}
+
/**
* Create a conversion from general purpose to x87 register
*/
ir_node *fild;
ir_node *store;
ir_node *new_node;
- int src_bits;
/* fild can use source AM if the operand is a signed 16bit or 32bit integer */
- if (src_mode == mode_Is || src_mode == mode_Hs) {
+ if (possible_int_mode_for_fp(src_mode)) {
ia32_address_mode_t am;
- match_arguments(&am, src_block, NULL, op, NULL,
- match_am | match_try_am | match_16bit | match_16bit_am);
+ match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
if (am.op_type == ia32_AddrModeS) {
ia32_address_t *addr = &am.addr;
- fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
- addr->index, addr->mem);
+ fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index,
+ addr->mem);
new_node = new_r_Proj(irg, block, fild, mode_vfp,
pn_ia32_vfild_res);
set_am_attributes(fild, &am);
- SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(fild, node);
fix_mem_proj(fild, &am);
mode = get_irn_mode(op);
/* first convert to 32 bit signed if necessary */
- src_bits = get_mode_size_bits(src_mode);
- if (src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
- new_op, src_mode);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- mode = mode_Is;
- } else if (src_bits < 32) {
- new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
- new_op, src_mode);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ if (get_mode_size_bits(src_mode) < 32) {
+ if (!upper_bits_clean(new_op, src_mode)) {
+ new_op = create_Conv_I2I(dbgi, block, noreg, noreg, nomem, new_op, src_mode);
+ SET_IA32_ORIG_NODE(new_op, node);
+ }
mode = mode_Is;
}
assert(get_mode_size_bits(mode) == 32);
/* do a store */
- store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
+ store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg), noreg, nomem,
new_op);
set_ia32_use_frame(store);
/* store a zero */
ir_node *zero_const = create_Immediate(NULL, 0, 0);
- ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
- get_irg_frame(irg), noreg, nomem,
- zero_const);
+ ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
+ noreg, nomem, zero_const);
set_ia32_use_frame(zero_store);
set_ia32_op_type(zero_store, ia32_AddrModeD);
}
/* do a fild */
- fild = new_rd_ia32_vfild(dbgi, irg, block, get_irg_frame(irg), noreg, store);
+ fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg, store);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
dbg_info *dbgi, ir_node *block, ir_node *op,
ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
- ir_node *new_block = be_transform_node(block);
- ir_node *new_node;
- ir_mode *smaller_mode;
- int smaller_bits;
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_node;
+ ir_mode *smaller_mode;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
(void) node;
- if (src_bits < tgt_bits) {
+ if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
smaller_mode = src_mode;
- smaller_bits = src_bits;
} else {
smaller_mode = tgt_mode;
- smaller_bits = tgt_bits;
}
#ifdef DEBUG_libfirm
#endif
match_arguments(&am, block, NULL, op, NULL,
- match_8bit | match_16bit |
match_am | match_8bit_am | match_16bit_am);
if (upper_bits_clean(am.new_op2, smaller_mode)) {
return am.new_op2;
}
- if (smaller_bits == 8) {
- new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op2,
- smaller_mode);
- } else {
- new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
- addr->index, addr->mem, am.new_op2,
- smaller_mode);
- }
+ new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
+ addr->mem, am.new_op2, smaller_mode);
set_am_attributes(new_node, &am);
/* match_arguments assume that out-mode = in-mode, this isn't true here
* so fix it */
set_ia32_ls_mode(new_node, smaller_mode);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
return new_node;
}
ir_node *new_block = be_transform_node(block);
ir_node *op = get_Conv_op(node);
ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *src_mode = get_irn_mode(op);
ir_mode *tgt_mode = get_irn_mode(node);
int src_bits = get_mode_size_bits(src_mode);
int tgt_bits = get_mode_size_bits(tgt_mode);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *nomem = new_NoMem();
ir_node *res = NULL;
+ assert(!mode_is_int(src_mode) || src_bits <= 32);
+ assert(!mode_is_int(tgt_mode) || tgt_bits <= 32);
+
if (src_mode == mode_b) {
assert(mode_is_int(tgt_mode) || mode_is_reference(tgt_mode));
/* nothing to do, we already model bools as 0/1 ints */
/* ... to float */
if (ia32_cg_config.use_sse2) {
DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
- res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
+ res = new_bd_ia32_Conv_FP2FP(dbgi, new_block, noreg, noreg,
nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
if (get_Conv_strict(node)) {
res = gen_x87_strict_conv(tgt_mode, new_op);
- SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
return res;
}
DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
/* ... to int */
DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
if (ia32_cg_config.use_sse2) {
- res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
+ res = new_bd_ia32_Conv_FP2I(dbgi, new_block, noreg, noreg,
nomem, new_op);
set_ia32_ls_mode(res, src_mode);
} else {
DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
if (ia32_cg_config.use_sse2) {
new_op = be_transform_node(op);
- res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
+ res = new_bd_ia32_Conv_I2FP(dbgi, new_block, noreg, noreg,
nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
}
if (float_mantissa < int_mantissa) {
res = gen_x87_strict_conv(tgt_mode, res);
- SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
}
}
return res;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *op = be_get_FrameAddr_frame(node);
ir_node *new_op = be_transform_node(op);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_node *new_node;
- new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
+ new_node = new_bd_ia32_Lea(dbgi, block, new_op, noreg);
set_ia32_frame_ent(new_node, arch_get_frame_entity(node));
set_ia32_use_frame(new_node);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
noreg = ia32_new_NoReg_gp(env_cg);
/* store xmm0 onto stack */
- sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
+ sse_store = new_bd_ia32_xStoreSimple(dbgi, block, frame, noreg,
new_ret_mem, new_ret_val);
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
/* load into x87 register */
- fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
+ fld = new_bd_ia32_vfld(dbgi, block, frame, noreg, sse_store, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
/* create a new barrier */
arity = get_irn_arity(barrier);
- in = alloca(arity * sizeof(in[0]));
+ in = ALLOCAN(ir_node*, arity);
for (i = 0; i < arity; ++i) {
ir_node *new_in;
ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
- return gen_binop(node, sp, sz, new_rd_ia32_SubSP,
+ return gen_binop(node, sp, sz, new_bd_ia32_SubSP,
match_am | match_immediate);
}
ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
- return gen_binop(node, sp, sz, new_rd_ia32_AddSP,
+ return gen_binop(node, sp, sz, new_bd_ia32_AddSP,
match_am | match_immediate);
}
assert(get_irn_mode(op) == mode_P);
- match_arguments(&am, block, NULL, op, NULL,
- match_am | match_8bit_am | match_16bit_am |
- match_immediate | match_8bit | match_16bit);
+ match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
- new_node = new_rd_ia32_IJmp(dbgi, current_ir_graph, new_block,
- addr->base, addr->index, addr->mem,
- am.new_op2);
+ new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
+ addr->mem, am.new_op2);
set_am_attributes(new_node, &am);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
ir_graph *irg = current_ir_graph;
res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
- new_rd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
+ new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
block = get_nodes_block(res);
if (! is_Proj(res)) {
sub = get_Proj_pred(res);
}
flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
- new_node = new_rd_ia32_Jcc(dbgi, irg, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
+ SET_IA32_ORIG_NODE(new_node, node);
} else {
panic("generic Bound not supported in ia32 Backend");
}
ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
- return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
+ return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
match_immediate | match_mode_neutral);
}
{
ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
- return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
+ return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
match_immediate);
}
{
ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
- return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
+ return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
match_immediate);
}
{
ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
- ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
+ ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Add,
match_commutative | match_am | match_immediate |
match_mode_neutral);
static ir_node *gen_ia32_l_Adc(ir_node *node)
{
- return gen_binop_flags(node, new_rd_ia32_Adc,
+ return gen_binop_flags(node, new_bd_ia32_Adc,
match_commutative | match_am | match_immediate |
match_mode_neutral);
}
ir_node *left = get_binop_left(node);
ir_node *right = get_binop_right(node);
- return gen_binop(node, left, right, new_rd_ia32_Mul,
+ return gen_binop(node, left, right, new_bd_ia32_Mul,
match_commutative | match_am | match_mode_neutral);
}
ir_node *left = get_binop_left(node);
ir_node *right = get_binop_right(node);
- return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
+ return gen_binop(node, left, right, new_bd_ia32_IMul1OP,
match_commutative | match_am | match_mode_neutral);
}
{
ir_node *left = get_irn_n(node, n_ia32_l_Sub_minuend);
ir_node *right = get_irn_n(node, n_ia32_l_Sub_subtrahend);
- ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
+ ir_node *lowered = gen_binop(node, left, right, new_bd_ia32_Sub,
match_am | match_immediate | match_mode_neutral);
if (is_Proj(lowered)) {
static ir_node *gen_ia32_l_Sbb(ir_node *node)
{
- return gen_binop_flags(node, new_rd_ia32_Sbb,
+ return gen_binop_flags(node, new_bd_ia32_Sbb,
match_am | match_immediate | match_mode_neutral);
}
{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *new_high = be_transform_node(high);
ir_node *new_low = be_transform_node(low);
new_count = create_immediate_or_transform(count, 0);
if (is_ia32_l_ShlD(node)) {
- new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
+ new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
new_count);
} else {
- new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
+ new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
new_count);
}
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
ir_node *new_val_low = be_transform_node(val_low);
ir_node *new_val_high = be_transform_node(val_high);
ir_node *in[2];
- ir_node *sync;
- ir_node *fild;
- ir_node *store_low;
- ir_node *store_high;
+ ir_node *sync, *fild, *res;
+ ir_node *store_low, *store_high;
- if (!mode_is_signed(get_irn_mode(val_high))) {
- panic("unsigned long long -> float not supported yet (%+F)", node);
+ if (ia32_cg_config.use_sse2) {
+ panic("ia32_l_LLtoFloat not implemented for SSE2");
}
/* do a store */
- store_low = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
+ store_low = new_bd_ia32_Store(dbgi, block, frame, noreg, nomem,
new_val_low);
- store_high = new_rd_ia32_Store(dbgi, irg, block, frame, noreg, nomem,
+ store_high = new_bd_ia32_Store(dbgi, block, frame, noreg, nomem,
new_val_high);
- SET_IA32_ORIG_NODE(store_low, ia32_get_old_node_name(env_cg, node));
- SET_IA32_ORIG_NODE(store_high, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(store_low, node);
+ SET_IA32_ORIG_NODE(store_high, node);
set_ia32_use_frame(store_low);
set_ia32_use_frame(store_high);
sync = new_rd_Sync(dbgi, irg, block, 2, in);
/* do a fild */
- fild = new_rd_ia32_vfild(dbgi, irg, block, frame, noreg, sync);
+ fild = new_bd_ia32_vfild(dbgi, block, frame, noreg, sync);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_ls_mode(fild, mode_Ls);
- SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
-
- return new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
+ SET_IA32_ORIG_NODE(fild, node);
+
+ res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
+
+ if (! mode_is_signed(get_irn_mode(val_high))) {
+ ia32_address_mode_t am;
+
+ ir_node *count = create_Immediate(NULL, 0, 31);
+ ir_node *fadd;
+
+ am.addr.base = ia32_new_NoReg_gp(env_cg);
+ am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
+ am.addr.mem = nomem;
+ am.addr.offset = 0;
+ am.addr.scale = 2;
+ am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
+ am.addr.use_frame = 0;
+ am.addr.frame_entity = NULL;
+ am.addr.symconst_sign = 0;
+ am.ls_mode = mode_F;
+ am.mem_proj = nomem;
+ am.op_type = ia32_AddrModeS;
+ am.new_op1 = res;
+ am.new_op2 = ia32_new_NoReg_vfp(env_cg);
+ am.pinned = op_pin_state_floats;
+ am.commutative = 1;
+ am.ins_permuted = 0;
+
+ fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
+ am.new_op1, am.new_op2, get_fpcw());
+ set_am_attributes(fadd, &am);
+
+ set_irn_mode(fadd, mode_T);
+ res = new_rd_Proj(NULL, irg, block, fadd, mode_vfp, pn_ia32_res);
+ }
+ return res;
}
static ir_node *gen_ia32_l_FloattoLL(ir_node *node)
ir_node *fist, *mem;
mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist);
- SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(fist, node);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
ir_node *proj;
ia32_attr_t *attr;
- load = new_rd_ia32_Load(dbgi, irg, block, frame, noreg, new_pred);
- SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
+ load = new_bd_ia32_Load(dbgi, block, frame, noreg, new_pred);
+ SET_IA32_ORIG_NODE(load, node);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_ls_mode(load, mode_Iu);
}
mem = transform_AM_mem(irg, block, src_ptr, src_mem, addr->mem);
- call = new_rd_ia32_Call(dbgi, irg, block, addr->base, addr->index, mem,
+ call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
set_am_attributes(call, &am);
call = fix_mem_proj(call, &am);
if (get_irn_pinned(node) == op_pin_state_pinned)
set_irn_pinned(call, op_pin_state_pinned);
- SET_IA32_ORIG_NODE(call, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(call, node);
return call;
}
static ir_node *gen_be_IncSP(ir_node *node)
{
ir_node *res = be_duplicate_node(node);
- be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
+ arch_irn_add_flags(res, arch_irn_flags_modify_flags);
return res;
}
long proj = get_Proj_proj(node);
ir_mode *mode = get_irn_mode(node);
ir_node *sse_load;
- const arch_register_class_t *cls;
- ir_node *res;
+ ir_node *res;
/* The following is kinda tricky: If we're using SSE, then we have to
* move the result value of the call in floating point registers to an
pn_be_Call_first_res);
/* store st(0) onto stack */
- fstp = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, call_mem,
+ fstp = new_bd_ia32_vfst(dbgi, block, frame, noreg, call_mem,
call_res, mode);
set_ia32_op_type(fstp, ia32_AddrModeD);
set_ia32_use_frame(fstp);
/* load into SSE register */
- sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
- mode);
+ sse_load = new_bd_ia32_xLoad(dbgi, block, frame, noreg, fstp, mode);
set_ia32_op_type(sse_load, ia32_AddrModeS);
set_ia32_use_frame(sse_load);
/* transform call modes */
if (mode_is_data(mode)) {
- cls = arch_get_irn_reg_class(node, -1);
+ const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
mode = cls->mode;
}
} else if (proj == pn_be_Call_M_regular) {
proj = pn_ia32_Call_M;
} else {
- arch_register_req_t const *const req = arch_get_register_req(node, BE_OUT_POS(proj));
- int const n_outs = get_ia32_n_res(new_call);
+ arch_register_req_t const *const req = arch_get_register_req_out(node);
+ int const n_outs = arch_irn_get_n_outs(new_call);
int i;
assert(proj >= pn_be_Call_first_res);
- assert(req->type == arch_register_req_type_limited);
+ assert(req->type & arch_register_req_type_limited);
for (i = 0; i < n_outs; ++i) {
arch_register_req_t const *const new_req = get_ia32_out_req(new_call, i);
- if (new_req->type != arch_register_req_type_limited ||
- new_req->cls != req->cls ||
+ if (!(new_req->type & arch_register_req_type_limited) ||
+ new_req->cls != req->cls ||
*new_req->limited != *req->limited)
continue;
new_pred = be_transform_node(pred);
block = get_nodes_block(new_pred);
return new_r_Proj(current_ir_graph, block, new_pred, mode_M,
- get_ia32_n_res(new_pred) + 1);
+ arch_irn_get_n_outs(new_pred) + 1);
}
/**
if (!is_ia32_irn(node))
return;
- n_outs = get_ia32_n_res(node);
+ n_outs = arch_irn_get_n_outs(node);
if (n_outs <= 0)
return;
if (is_ia32_SwitchJmp(node))
projects / libfirm / blobdiff