/**
* Return true if a mode can be stored in the GP register set
*/
-static INLINE int mode_needs_gp_reg(ir_mode *mode) {
+int ia32_mode_needs_gp_reg(ir_mode *mode) {
if(mode == mode_fpcw)
return 0;
if(get_mode_size_bits(mode) > 32)
/**
* Get a primitive type for a mode.
*/
-static ir_type *get_prim_type(pmap *types, ir_mode *mode)
+ir_type *ia32_get_prim_type(pmap *types, ir_mode *mode)
{
pmap_entry *e = pmap_find(types, mode);
ir_type *res;
/* mode was not changed */
tp = get_Const_type(cnst);
if (tp == firm_unknown_type)
- tp = get_prim_type(isa->types, mode);
+ tp = ia32_get_prim_type(isa->types, mode);
} else
- tp = get_prim_type(isa->types, mode);
+ tp = ia32_get_prim_type(isa->types, mode);
res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
return res;
}
+/** Return non-zero is a node represents the 0 constant. */
static int is_Const_0(ir_node *node) {
return is_Const(node) && is_Const_null(node);
}
+/** Return non-zero is a node represents the 1 constant. */
static int is_Const_1(ir_node *node) {
return is_Const(node) && is_Const_one(node);
}
+/** Return non-zero is a node represents the -1 constant. */
static int is_Const_Minus_1(ir_node *node) {
return is_Const(node) && is_Const_all_one(node);
}
* Prints the old node name on cg obst and returns a pointer to it.
*/
const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
- ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
+ ia32_isa_t *isa = (ia32_isa_t*) cg->arch_env;
lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
obstack_1grow(isa->name_obst, 0);
* input here, for unary operations use NULL).
*/
static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
- ir_node *other, ir_node *other2)
+ ir_node *other, ir_node *other2, match_flags_t flags)
{
ir_node *load;
long pn;
if (get_nodes_block(load) != block)
return 0;
/* we only use address mode if we're the only user of the load */
- if (get_irn_n_edges(node) > 1)
+ if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
return 0;
/* in some edge cases with address mode we might reach the load normally
* and through some AM sequence, if it is already materialized then we
set_ia32_op_type(node, am->op_type);
set_ia32_ls_mode(node, am->ls_mode);
if (am->pinned == op_pin_state_pinned) {
- set_irn_pinned(node, am->pinned);
+ /* beware: some nodes are already pinned and did not allow to change the state */
+ if (get_irn_pinned(node) != op_pin_state_pinned)
+ set_irn_pinned(node, op_pin_state_pinned);
}
if (am->commutative)
set_ia32_commutative(node);
src_mode = get_irn_mode(get_Conv_op(node));
dest_mode = get_irn_mode(node);
- return mode_needs_gp_reg(src_mode)
- && mode_needs_gp_reg(dest_mode)
+ return ia32_mode_needs_gp_reg(src_mode)
+ && ia32_mode_needs_gp_reg(dest_mode)
&& get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
}
return node;
}
-#if 0
static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
{
ir_mode *mode = get_irn_mode(node);
return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
}
-#endif
/**
* matches operands of a node into ia32 addressing/operand modes. This covers
noreg_gp = ia32_new_NoReg_gp(env_cg);
if (new_op2 == NULL &&
- use_am && ia32_use_source_address_mode(block, op2, op1, other_op)) {
+ use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
build_address(am, op2);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (mode_is_float(mode)) {
am->op_type = ia32_AddrModeS;
} else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
use_am &&
- ia32_use_source_address_mode(block, op1, op2, other_op)) {
+ ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
ir_node *noreg;
build_address(am, op1);
/**
* Construct a standard binary operation, set AM and immediate if required.
*
+ * @param node The original node for which the binop is created
* @param op1 The first operand
* @param op2 The second operand
* @param func The node constructor function
assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
if (flags & match_mode_neutral) {
- op1 = ia32_skip_downconv(op1);
+ op1 = ia32_skip_downconv(op1);
+ new_op1 = be_transform_node(op1);
} else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
- panic("right shifting of non-32bit values not supported, yet");
+ new_op1 = create_upconv(op1, node);
+ } else {
+ new_op1 = be_transform_node(op1);
}
- new_op1 = be_transform_node(op1);
/* the shift amount can be any mode that is bigger than 5 bits, since all
* other bits are ignored anyway */
/**
- * Creates an ia32 RotL.
+ * Creates an ia32 Rol.
*
* @param op1 The first operator
* @param op2 The second operator
* @return The created ia32 RotL node
*/
-static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Rol(ir_node *node, ir_node *op1, ir_node *op2) {
return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
}
/**
- * Creates an ia32 RotR.
+ * Creates an ia32 Ror.
* NOTE: There is no RotR with immediate because this would always be a RotL
* "imm-mode_size_bits" which can be pre-calculated.
*
* @param op2 The second operator
* @return The created ia32 RotR node
*/
-static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
+static ir_node *gen_Ror(ir_node *node, ir_node *op1, ir_node *op2) {
return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
}
*
* @return The created ia32 RotL or RotR node
*/
-static ir_node *gen_Rot(ir_node *node) {
+static ir_node *gen_Rotl(ir_node *node) {
ir_node *rotate = NULL;
- ir_node *op1 = get_Rot_left(node);
- ir_node *op2 = get_Rot_right(node);
+ ir_node *op1 = get_Rotl_left(node);
+ ir_node *op2 = get_Rotl_right(node);
- /* Firm has only Rot (which is a RotL), so we are looking for a right (op2)
+ /* Firm has only RotL, so we are looking for a right (op2)
operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
that means we can create a RotR instead of an Add and a RotL */
- if (get_irn_op(op2) == op_Add) {
+ if (is_Add(op2)) {
ir_node *add = op2;
ir_node *left = get_Add_left(add);
ir_node *right = get_Add_right(add);
ir_mode *mode = get_irn_mode(node);
long bits = get_mode_size_bits(mode);
- if (get_irn_op(left) == op_Minus &&
- tarval_is_long(tv) &&
- get_tarval_long(tv) == bits &&
- bits == 32)
+ if (is_Minus(left) &&
+ tarval_is_long(tv) &&
+ get_tarval_long(tv) == bits &&
+ bits == 32)
{
DB((dbg, LEVEL_1, "RotL into RotR ... "));
- rotate = gen_RotR(node, op1, get_Minus_op(left));
+ rotate = gen_Ror(node, op1, get_Minus_op(left));
}
}
}
if (rotate == NULL) {
- rotate = gen_RotL(node, op1, op2);
+ rotate = gen_Rol(node, op1, op2);
}
return rotate;
return 1;
}
+static void set_transformed_and_mark(ir_node *const old_node, ir_node *const new_node)
+{
+ mark_irn_visited(old_node);
+ be_set_transformed_node(old_node, new_node);
+}
+
static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
ir_node *mem, ir_node *ptr, ir_mode *mode,
construct_binop_dest_func *func,
dbg_info *dbgi;
ir_node *new_node;
ir_node *new_op;
+ ir_node *mem_proj;
int commutative;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
set_ia32_ls_mode(new_node, mode);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node);
+ mem_proj = be_transform_node(am.mem_proj);
+ set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node);
+
return new_node;
}
ir_node *block;
dbg_info *dbgi;
ir_node *new_node;
+ ir_node *mem_proj;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
memset(&am, 0, sizeof(am));
set_ia32_ls_mode(new_node, mode);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ set_transformed_and_mark(get_Proj_pred(am.mem_proj), new_node);
+ mem_proj = be_transform_node(am.mem_proj);
+ set_transformed_and_mark(mem_proj ? mem_proj : am.mem_proj, new_node);
+
return new_node;
}
ir_node *new_node;
/* handle only GP modes for now... */
- if(!mode_needs_gp_reg(mode))
+ if(!ia32_mode_needs_gp_reg(mode))
return NULL;
while(1) {
if(get_nodes_block(node) != get_nodes_block(val))
return NULL;
- switch(get_irn_opcode(val)) {
+ switch (get_irn_opcode(val)) {
case iro_Add:
op1 = get_Add_left(val);
op2 = get_Add_right(val);
new_rd_ia32_SarMem, new_rd_ia32_SarMem,
match_dest_am | match_immediate);
break;
- case iro_Rot:
- op1 = get_Rot_left(val);
- op2 = get_Rot_right(val);
+ case iro_Rotl:
+ op1 = get_Rotl_left(val);
+ op2 = get_Rotl_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
new_rd_ia32_RolMem, new_rd_ia32_RolMem,
match_dest_am | match_immediate);
ir_node *conv_op;
ir_mode *conv_mode;
- if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
+ if(get_mode_size_bits(mode) != 32 || !ia32_mode_needs_gp_reg(mode))
return 0;
if(!is_Conv(node))
* Generate a vfist or vfisttp instruction.
*/
static ir_node *gen_vfist(dbg_info *dbgi, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index,
- ir_node *mem, ir_node *val)
+ ir_node *mem, ir_node *val, ir_node **fist)
{
ir_node *new_node;
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
const arch_register_class_t *reg_class = &ia32_reg_classes[CLASS_ia32_vfp];
- val = be_new_Copy(reg_class, irg, block, val);
+ ir_node *vfisttp = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val);
+ ir_node *value = new_r_Proj(irg, block, vfisttp, mode_E, pn_ia32_vfisttp_res);
+ be_new_Keep(reg_class, irg, block, 1, &value);
- new_node = new_rd_ia32_vfisttp(dbgi, irg, block, base, index, mem, val);
+ new_node = new_r_Proj(irg, block, vfisttp, mode_M, pn_ia32_vfisttp_M);
+ *fist = vfisttp;
} else {
ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
/* do a fist */
new_node = new_rd_ia32_vfist(dbgi, irg, block, base, index, mem, val, trunc_mode);
+ *fist = new_node;
}
return new_node;
}
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *new_val;
- ir_node *new_node;
+ ir_node *new_val, *new_node, *store;
ia32_address_t addr;
/* check for destination address mode */
addr.mem = be_transform_node(mem);
if (mode_is_float(mode)) {
- /* convs (and strict-convs) before stores are unnecessary if the mode
- is the same */
- while (is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
- val = get_Conv_op(val);
+ /* Convs (and strict-Convs) before stores are unnecessary if the mode
+ is the same. */
+ while (is_Conv(val) && mode == get_irn_mode(val)) {
+ ir_node *op = get_Conv_op(val);
+ if (!mode_is_float(get_irn_mode(op)))
+ break;
+ val = op;
}
new_val = be_transform_node(val);
if (ia32_cg_config.use_sse2) {
new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
- } else if (is_float_to_int32_conv(val)) {
+ store = new_node;
+ } else if (!ia32_cg_config.use_sse2 && is_float_to_int32_conv(val)) {
val = get_Conv_op(val);
- /* convs (and strict-convs) before stores are unnecessary if the mode
- is the same */
- while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
+ /* We can skip ALL Convs (and strict-Convs) before stores. */
+ while (is_Conv(val)) {
val = get_Conv_op(val);
}
new_val = be_transform_node(val);
- new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val);
+ new_node = gen_vfist(dbgi, irg, new_block, addr.base, addr.index, addr.mem, new_val, &store);
} else {
new_val = create_immediate_or_transform(val, 0);
assert(mode != mode_b);
new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
addr.index, addr.mem, new_val);
}
+ store = new_node;
}
- set_irn_pinned(new_node, get_irn_pinned(node));
- set_ia32_op_type(new_node, ia32_AddrModeD);
- set_ia32_ls_mode(new_node, mode);
+ set_irn_pinned(store, get_irn_pinned(node));
+ set_ia32_op_type(store, ia32_AddrModeD);
+ set_ia32_ls_mode(store, mode);
- set_address(new_node, &addr);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ set_address(store, &addr);
+ SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
return new_node;
}
ir_node *new_node = be_duplicate_node(node);
ir_mode *mode = get_irn_mode(new_node);
- if (mode_needs_gp_reg(mode)) {
+ if (ia32_mode_needs_gp_reg(mode)) {
set_irn_mode(new_node, mode_Iu);
}
}
}
- assert(mode_needs_gp_reg(cmp_mode));
+ assert(ia32_mode_needs_gp_reg(cmp_mode));
/* we prefer the Test instruction where possible except cases where
* we can use SourceAM */
ia32_address_t *addr;
assert(ia32_cg_config.use_cmov);
- assert(mode_needs_gp_reg(get_irn_mode(val_true)));
+ assert(ia32_mode_needs_gp_reg(get_irn_mode(val_true)));
addr = &am.addr;
return new_node;
}
-
-
+/**
+ * Creates a ia32 Setcc instruction.
+ */
static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
int ins_permuted)
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
/* we might need to conv the result up */
- if(get_mode_size_bits(mode) > 8) {
+ if (get_mode_size_bits(mode) > 8) {
new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
return new_node;
}
+/**
+ * Create instruction for an unsigned Difference or Zero.
+ */
+static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b) {
+ ir_graph *irg = current_ir_graph;
+ ir_mode *mode = get_irn_mode(psi);
+ ir_node *new_node, *sub, *sbb, *eflags, *block, *noreg, *tmpreg, *nomem;
+ dbg_info *dbgi;
+
+ new_node = gen_binop(psi, a, b, new_rd_ia32_Sub,
+ match_mode_neutral | match_am | match_immediate | match_two_users);
+
+ block = get_nodes_block(new_node);
+
+ if (is_Proj(new_node)) {
+ sub = get_Proj_pred(new_node);
+ assert(is_ia32_Sub(sub));
+ } else {
+ sub = new_node;
+ set_irn_mode(sub, mode_T);
+ new_node = new_rd_Proj(NULL, irg, block, sub, mode, pn_ia32_res);
+ }
+ eflags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
+
+ dbgi = get_irn_dbg_info(psi);
+ noreg = ia32_new_NoReg_gp(env_cg);
+ tmpreg = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ nomem = new_NoMem();
+ sbb = new_rd_ia32_Sbb(dbgi, irg, block, noreg, noreg, nomem, tmpreg, tmpreg, eflags);
+
+ new_node = new_rd_ia32_And(dbgi, irg, block, noreg, noreg, nomem, new_node, sbb);
+ set_ia32_commutative(new_node);
+ return new_node;
+}
+
/**
* Transforms a Psi node into CMov.
*
ir_node *psi_true = get_Psi_val(node, 0);
ir_node *psi_default = get_Psi_default(node);
ir_node *cond = get_Psi_cond(node, 0);
- ir_node *flags = NULL;
- ir_node *new_node;
- pn_Cmp pnc;
+ ir_mode *mode = get_irn_mode(node);
+ pn_Cmp pnc;
assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
- assert(mode_needs_gp_reg(get_irn_mode(node)));
- flags = get_flags_node(cond, &pnc);
+ /* Note: a Psi node uses a Load two times IFF it's used in the compare AND in the result */
+ if (mode_is_float(mode)) {
+ ir_node *cmp = get_Proj_pred(cond);
+ ir_node *cmp_left = get_Cmp_left(cmp);
+ ir_node *cmp_right = get_Cmp_right(cmp);
+ pn_Cmp pnc = get_Proj_proj(cond);
+
+ if (ia32_cg_config.use_sse2) {
+ if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
+ if (cmp_left == psi_true && cmp_right == psi_default) {
+ /* psi(a <= b, a, b) => MIN */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
+ match_commutative | match_am | match_two_users);
+ } else if (cmp_left == psi_default && cmp_right == psi_true) {
+ /* psi(a <= b, b, a) => MAX */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
+ match_commutative | match_am | match_two_users);
+ }
+ } else if (pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge) {
+ if (cmp_left == psi_true && cmp_right == psi_default) {
+ /* psi(a >= b, a, b) => MAX */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMax,
+ match_commutative | match_am | match_two_users);
+ } else if (cmp_left == psi_default && cmp_right == psi_true) {
+ /* psi(a >= b, b, a) => MIN */
+ return gen_binop(node, cmp_left, cmp_right, new_rd_ia32_xMin,
+ match_commutative | match_am | match_two_users);
+ }
+ }
+ }
+ panic("cannot transform floating point Psi");
- if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
- } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
} else {
- new_node = create_CMov(node, cond, flags, pnc);
+ ir_node *flags;
+ ir_node *new_node;
+
+ assert(ia32_mode_needs_gp_reg(mode));
+
+ if (is_Proj(cond)) {
+ ir_node *cmp = get_Proj_pred(cond);
+ if (is_Cmp(cmp)) {
+ ir_node *cmp_left = get_Cmp_left(cmp);
+ ir_node *cmp_right = get_Cmp_right(cmp);
+ pn_Cmp pnc = get_Proj_proj(cond);
+
+ /* check for unsigned Doz first */
+ if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
+ is_Const_0(psi_default) && is_Sub(psi_true) &&
+ get_Sub_left(psi_true) == cmp_left && get_Sub_right(psi_true) == cmp_right) {
+ /* Psi(a >=u b, a - b, 0) unsigned Doz */
+ return create_Doz(node, cmp_left, cmp_right);
+ } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
+ is_Const_0(psi_true) && is_Sub(psi_default) &&
+ get_Sub_left(psi_default) == cmp_left && get_Sub_right(psi_default) == cmp_right) {
+ /* Psi(a <=u b, 0, a - b) unsigned Doz */
+ return create_Doz(node, cmp_left, cmp_right);
+ }
+ }
+ }
+
+ flags = get_flags_node(cond, &pnc);
+
+ if (is_Const(psi_true) && is_Const(psi_default)) {
+ /* both are const, good */
+ if (is_Const_1(psi_true) && is_Const_0(psi_default)) {
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/0);
+ } else if (is_Const_0(psi_true) && is_Const_1(psi_default)) {
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, /*is_premuted=*/1);
+ } else {
+ /* Not that simple. */
+ goto need_cmov;
+ }
+ } else {
+need_cmov:
+ new_node = create_CMov(node, cond, flags, pnc);
+ }
+ return new_node;
}
- return new_node;
}
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(cg);
ir_mode *mode = get_irn_mode(node);
- ir_node *fist, *load;
+ ir_node *fist, *load, *mem;
- fist = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op);
+ mem = gen_vfist(dbgi, irg, block, get_irg_frame(irg), noreg, new_NoMem(), new_op, &fist);
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(cg, node));
/* do a Load */
- load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, fist);
+ load = new_rd_ia32_Load(dbgi, irg, block, get_irg_frame(irg), noreg, mem);
set_irn_pinned(load, op_pin_state_floats);
set_ia32_use_frame(load);
return res;
}
-static int check_immediate_constraint(long val, char immediate_constraint_type)
+static bool check_immediate_constraint(long val, char immediate_constraint_type)
{
switch (immediate_constraint_type) {
case 0:
- return 1;
+ case 'i':
+ return true;
case 'I':
return val >= 0 && val <= 32;
case 'J':
break;
}
panic("Invalid immediate constraint found");
- return 0;
+ return false;
}
static ir_node *try_create_Immediate(ir_node *node,
return new_node;
}
-static const arch_register_req_t no_register_req = {
- arch_register_req_type_none,
- NULL, /* regclass */
- NULL, /* limit bitset */
- 0, /* same pos */
- 0 /* different pos */
-};
-/**
- * An assembler constraint.
- */
-typedef struct constraint_t constraint_t;
-struct constraint_t {
- int is_in;
- int n_outs;
- const arch_register_req_t **out_reqs;
-
- const arch_register_req_t *req;
- unsigned immediate_possible;
- char immediate_type;
-};
-static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
+void parse_asm_constraints(constraint_t *constraint, const char *c,
+ bool is_output)
{
- int immediate_possible = 0;
- char immediate_type = 0;
+ asm_constraint_flags_t flags = 0;
+ char immediate_type = '\0';
unsigned limited = 0;
const arch_register_class_t *cls = NULL;
- ir_graph *irg = current_ir_graph;
- struct obstack *obst = get_irg_obstack(irg);
- arch_register_req_t *req;
- unsigned *limited_ptr = NULL;
+ bool memory_possible = false;
+ bool all_registers_allowed = false;
int p;
int same_as = -1;
- /* TODO: replace all the asserts with nice error messages */
+ memset(constraint, 0, sizeof(constraint[0]));
+ constraint->same_as = -1;
if(*c == 0) {
/* a memory constraint: no need to do anything in backend about it
* (the dependencies are already respected by the memory edge of
* the node) */
- constraint->req = &no_register_req;
return;
}
+ /* TODO: improve error messages with node and source info. (As users can
+ * easily hit these) */
while(*c != 0) {
switch(*c) {
case ' ':
case '\n':
break;
+ case '=':
+ flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
+ | ASM_CONSTRAINT_FLAG_MODIFIER_NO_READ;
+ break;
+
+ case '+':
+ flags |= ASM_CONSTRAINT_FLAG_MODIFIER_WRITE
+ | ASM_CONSTRAINT_FLAG_MODIFIER_READ;
+ break;
+
+ case '*':
+ ++c;
+ break;
+ case '#':
+ while(*c != 0 && *c != ',')
+ ++c;
+ break;
+
case 'a':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EAX;
break;
case 'b':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EBX;
break;
case 'c':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_ECX;
break;
case 'd':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EDX;
break;
case 'D':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EDI;
break;
case 'S':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_ESI;
break;
case 'Q':
- case 'q': /* q means lower part of the regs only, this makes no
- * difference to Q for us (we only assigne whole registers) */
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ case 'q':
+ /* q means lower part of the regs only, this makes no
+ * difference to Q for us (we only assign whole registers) */
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
1 << REG_EDX;
break;
case 'A':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EAX | 1 << REG_EDX;
break;
case 'l':
- assert(cls == NULL ||
- (cls == &ia32_reg_classes[CLASS_ia32_gp] && limited != 0));
+ assert(cls == NULL || cls == &ia32_reg_classes[CLASS_ia32_gp]);
cls = &ia32_reg_classes[CLASS_ia32_gp];
limited |= 1 << REG_EAX | 1 << REG_EBX | 1 << REG_ECX |
1 << REG_EDX | 1 << REG_ESI | 1 << REG_EDI |
case 'R':
case 'r':
case 'p':
- assert(cls == NULL);
- cls = &ia32_reg_classes[CLASS_ia32_gp];
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
+ panic("multiple register classes not supported");
+ cls = &ia32_reg_classes[CLASS_ia32_gp];
+ all_registers_allowed = true;
break;
case 'f':
case 't':
case 'u':
/* TODO: mark values so the x87 simulator knows about t and u */
- assert(cls == NULL);
- cls = &ia32_reg_classes[CLASS_ia32_vfp];
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_vfp])
+ panic("multiple register classes not supported");
+ cls = &ia32_reg_classes[CLASS_ia32_vfp];
+ all_registers_allowed = true;
break;
case 'Y':
case 'x':
- assert(cls == NULL);
- /* TODO: check that sse2 is supported */
- cls = &ia32_reg_classes[CLASS_ia32_xmm];
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_xmm])
+ panic("multiple register classes not supproted");
+ cls = &ia32_reg_classes[CLASS_ia32_xmm];
+ all_registers_allowed = true;
break;
case 'I':
case 'M':
case 'N':
case 'O':
- assert(!immediate_possible);
- immediate_possible = 1;
- immediate_type = *c;
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
+ panic("multiple register classes not supported");
+ if (immediate_type != '\0')
+ panic("multiple immediate types not supported");
+ cls = &ia32_reg_classes[CLASS_ia32_gp];
+ immediate_type = *c;
break;
case 'n':
case 'i':
- assert(!immediate_possible);
- immediate_possible = 1;
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
+ panic("multiple register classes not supported");
+ if (immediate_type != '\0')
+ panic("multiple immediate types not supported");
+ cls = &ia32_reg_classes[CLASS_ia32_gp];
+ immediate_type = 'i';
break;
+ case 'X':
case 'g':
- assert(!immediate_possible && cls == NULL);
- immediate_possible = 1;
- cls = &ia32_reg_classes[CLASS_ia32_gp];
+ if (cls != NULL && cls != &ia32_reg_classes[CLASS_ia32_gp])
+ panic("multiple register classes not supported");
+ if (immediate_type != '\0')
+ panic("multiple immediate types not supported");
+ immediate_type = 'i';
+ cls = &ia32_reg_classes[CLASS_ia32_gp];
+ all_registers_allowed = true;
+ memory_possible = true;
break;
case '0':
case '7':
case '8':
case '9':
- assert(constraint->is_in && "can only specify same constraint "
- "on input");
+ if (is_output)
+ panic("can only specify same constraint on input");
sscanf(c, "%d%n", &same_as, &p);
if(same_as >= 0) {
break;
case 'm':
+ case 'o':
+ case 'V':
/* memory constraint no need to do anything in backend about it
* (the dependencies are already respected by the memory edge of
* the node) */
- constraint->req = &no_register_req;
- return;
+ memory_possible = true;
+ break;
case 'E': /* no float consts yet */
case 'F': /* no float consts yet */
case 's': /* makes no sense on x86 */
- case 'X': /* we can't support that in firm */
- case 'o':
- case 'V':
case '<': /* no autodecrement on x86 */
case '>': /* no autoincrement on x86 */
case 'C': /* sse constant not supported yet */
}
if(same_as >= 0) {
+ if (cls != NULL)
+ panic("same as and register constraint not supported");
+ if (immediate_type != '\0')
+ panic("same as and immediate constraint not supported");
+ }
+
+ if (cls == NULL && same_as < 0) {
+ if (!memory_possible)
+ panic("no constraint specified for assembler input");
+ }
+
+ constraint->same_as = same_as;
+ constraint->cls = cls;
+ constraint->allowed_registers = limited;
+ constraint->all_registers_allowed = all_registers_allowed;
+ constraint->memory_possible = memory_possible;
+ constraint->immediate_type = immediate_type;
+}
+
+const arch_register_req_t *make_register_req(const constraint_t *constraint,
+ int n_outs, const arch_register_req_t **out_reqs, int pos)
+{
+ struct obstack *obst = get_irg_obstack(current_ir_graph);
+ int same_as = constraint->same_as;
+ arch_register_req_t *req;
+
+ if (same_as >= 0) {
const arch_register_req_t *other_constr;
- assert(cls == NULL && "same as and register constraint not supported");
- assert(!immediate_possible && "same as and immediate constraint not "
- "supported");
- assert(same_as < constraint->n_outs && "wrong constraint number in "
- "same_as constraint");
+ if (same_as >= n_outs)
+ panic("invalid output number in same_as constraint");
- other_constr = constraint->out_reqs[same_as];
+ other_constr = out_reqs[same_as];
req = obstack_alloc(obst, sizeof(req[0]));
req->cls = other_constr->cls;
/* switch constraints. This is because in firm we have same_as
* constraints on the output constraints while in the gcc asm syntax
* they are specified on the input constraints */
- constraint->req = other_constr;
- constraint->out_reqs[same_as] = req;
- constraint->immediate_possible = 0;
- return;
+ out_reqs[same_as] = req;
+ return other_constr;
}
- if(immediate_possible && cls == NULL) {
- cls = &ia32_reg_classes[CLASS_ia32_gp];
+ /* pure memory ops */
+ if (constraint->cls == NULL) {
+ return &no_register_req;
}
- assert(!immediate_possible || cls == &ia32_reg_classes[CLASS_ia32_gp]);
- assert(cls != NULL);
- if(immediate_possible) {
- assert(constraint->is_in
- && "immediate make no sense for output constraints");
- }
- /* todo: check types (no float input on 'r' constrained in and such... */
+ if (constraint->allowed_registers != 0
+ && !constraint->all_registers_allowed) {
+ unsigned *limited_ptr;
- if(limited != 0) {
- req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
- limited_ptr = (unsigned*) (req+1);
- } else {
- req = obstack_alloc(obst, sizeof(req[0]));
- }
- memset(req, 0, sizeof(req[0]));
+ req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
+ memset(req, 0, sizeof(req[0]));
+ limited_ptr = (unsigned*) (req+1);
- if(limited != 0) {
req->type = arch_register_req_type_limited;
- *limited_ptr = limited;
+ *limited_ptr = constraint->allowed_registers;
req->limited = limited_ptr;
} else {
- req->type = arch_register_req_type_normal;
+ req = obstack_alloc(obst, sizeof(req[0]));
+ memset(req, 0, sizeof(req[0]));
+ req->type = arch_register_req_type_normal;
}
- req->cls = cls;
+ req->cls = constraint->cls;
- constraint->req = req;
- constraint->immediate_possible = immediate_possible;
- constraint->immediate_type = immediate_type;
+ return req;
}
-static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
- const char *clobber)
+const arch_register_t *ia32_get_clobber_register(const char *clobber)
{
- ir_graph *irg = get_irn_irg(node);
- struct obstack *obst = get_irg_obstack(irg);
- const arch_register_t *reg = NULL;
+ const arch_register_t *reg = NULL;
int c;
size_t r;
- arch_register_req_t *req;
const arch_register_class_t *cls;
- unsigned *limited;
-
- (void) pos;
/* TODO: construct a hashmap instead of doing linear search for clobber
* register */
if(reg != NULL)
break;
}
+
+ return reg;
+}
+
+const arch_register_req_t *parse_clobber(const char *clobber)
+{
+ struct obstack *obst = get_irg_obstack(current_ir_graph);
+ const arch_register_t *reg = ia32_get_clobber_register(clobber);
+ arch_register_req_t *req;
+ unsigned *limited;
+
if(reg == NULL) {
panic("Register '%s' mentioned in asm clobber is unknown\n", clobber);
- return;
}
assert(reg->index < 32);
req = obstack_alloc(obst, sizeof(req[0]));
memset(req, 0, sizeof(req[0]));
req->type = arch_register_req_type_limited;
- req->cls = cls;
+ req->cls = arch_register_get_class(reg);
req->limited = limited;
- constraint->req = req;
- constraint->immediate_possible = 0;
- constraint->immediate_type = 0;
-}
-
-static int is_memory_op(const ir_asm_constraint *constraint)
-{
- ident *id = constraint->constraint;
- const char *str = get_id_str(id);
- const char *c;
-
- for(c = str; *c != '\0'; ++c) {
- if(*c == 'm')
- return 1;
- }
-
- return 0;
+ return req;
}
/**
*/
static ir_node *gen_ASM(ir_node *node)
{
- int i, arity;
ir_graph *irg = current_ir_graph;
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
+ int i, arity;
+ int out_idx;
ir_node **in;
ir_node *new_node;
int out_arity;
const ir_asm_constraint *in_constraints;
const ir_asm_constraint *out_constraints;
ident **clobbers;
- constraint_t parsed_constraint;
+ bool clobbers_flags = false;
+
+ /* workaround for lots of buggy code out there as most people think volatile
+ * asm is enough for everything and forget the flags (linux kernel, etc.)
+ */
+ if (get_irn_pinned(node) == op_pin_state_pinned) {
+ clobbers_flags = true;
+ }
arity = get_irn_arity(node);
in = alloca(arity * sizeof(in[0]));
memset(in, 0, arity * sizeof(in[0]));
+ clobbers = get_ASM_clobbers(node);
+ n_clobbers = 0;
+ for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
+ const char *c = get_id_str(clobbers[i]);
+ if (strcmp(c, "memory") == 0)
+ continue;
+ if (strcmp(c, "cc") == 0) {
+ clobbers_flags = true;
+ continue;
+ }
+ n_clobbers++;
+ }
n_out_constraints = get_ASM_n_output_constraints(node);
- n_clobbers = get_ASM_n_clobbers(node);
out_arity = n_out_constraints + n_clobbers;
- /* hack to keep space for mem proj */
- if(n_clobbers > 0)
- out_arity += 1;
in_constraints = get_ASM_input_constraints(node);
out_constraints = get_ASM_output_constraints(node);
- clobbers = get_ASM_clobbers(node);
-
- /* construct output constraints */
- obst = get_irg_obstack(irg);
- out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
- parsed_constraint.out_reqs = out_reg_reqs;
- parsed_constraint.n_outs = n_out_constraints;
- parsed_constraint.is_in = 0;
-
- for(i = 0; i < out_arity; ++i) {
- const char *c;
-
- if(i < n_out_constraints) {
- const ir_asm_constraint *constraint = &out_constraints[i];
- c = get_id_str(constraint->constraint);
- parse_asm_constraint(i, &parsed_constraint, c);
-
- if(constraint->pos > reg_map_size)
- reg_map_size = constraint->pos;
-
- out_reg_reqs[i] = parsed_constraint.req;
- } else if(i < out_arity - 1) {
- ident *glob_id = clobbers [i - n_out_constraints];
- assert(glob_id != NULL);
- c = get_id_str(glob_id);
- parse_clobber(node, i, &parsed_constraint, c);
- out_reg_reqs[i+1] = parsed_constraint.req;
- }
+ /* determine size of register_map */
+ for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
+ const ir_asm_constraint *constraint = &out_constraints[out_idx];
+ if (constraint->pos > reg_map_size)
+ reg_map_size = constraint->pos;
}
- if(n_clobbers > 1)
- out_reg_reqs[n_out_constraints] = &no_register_req;
-
- /* construct input constraints */
- in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
- parsed_constraint.is_in = 1;
for(i = 0; i < arity; ++i) {
const ir_asm_constraint *constraint = &in_constraints[i];
- ident *constr_id = constraint->constraint;
- const char *c = get_id_str(constr_id);
-
- parse_asm_constraint(i, &parsed_constraint, c);
- in_reg_reqs[i] = parsed_constraint.req;
-
if(constraint->pos > reg_map_size)
reg_map_size = constraint->pos;
-
- if(parsed_constraint.immediate_possible) {
- ir_node *pred = get_irn_n(node, i);
- char imm_type = parsed_constraint.immediate_type;
- ir_node *immediate = try_create_Immediate(pred, imm_type);
-
- if(immediate != NULL) {
- in[i] = immediate;
- }
- }
}
- reg_map_size++;
+ ++reg_map_size;
+ obst = get_irg_obstack(irg);
register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
- for(i = 0; i < n_out_constraints; ++i) {
- const ir_asm_constraint *constraint = &out_constraints[i];
- unsigned pos = constraint->pos;
+ /* construct output constraints */
+ out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
- assert(pos < reg_map_size);
- register_map[pos].use_input = 0;
- register_map[pos].valid = 1;
- register_map[pos].memory = is_memory_op(constraint);
- register_map[pos].inout_pos = i;
+ for(out_idx = 0; out_idx < n_out_constraints; ++out_idx) {
+ const ir_asm_constraint *constraint = &out_constraints[out_idx];
+ const char *c = get_id_str(constraint->constraint);
+ unsigned pos = constraint->pos;
+ constraint_t parsed_constraint;
+ const arch_register_req_t *req;
+
+ parse_asm_constraints(&parsed_constraint, c, true);
+ req = make_register_req(&parsed_constraint, n_out_constraints,
+ out_reg_reqs, out_idx);
+ out_reg_reqs[out_idx] = req;
+
+ register_map[pos].use_input = false;
+ register_map[pos].valid = true;
+ register_map[pos].memory = false;
+ register_map[pos].inout_pos = out_idx;
register_map[pos].mode = constraint->mode;
}
- /* transform inputs */
+ /* inputs + input constraints */
+ in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
for(i = 0; i < arity; ++i) {
- const ir_asm_constraint *constraint = &in_constraints[i];
- unsigned pos = constraint->pos;
- ir_node *pred = get_irn_n(node, i);
- ir_node *transformed;
-
- assert(pos < reg_map_size);
- register_map[pos].use_input = 1;
- register_map[pos].valid = 1;
- register_map[pos].memory = is_memory_op(constraint);
+ ir_node *pred = get_irn_n(node, i);
+ const ir_asm_constraint *constraint = &in_constraints[i];
+ ident *constr_id = constraint->constraint;
+ const char *c = get_id_str(constr_id);
+ unsigned pos = constraint->pos;
+ bool is_memory_op = false;
+ ir_node *input = NULL;
+ constraint_t parsed_constraint;
+ const arch_register_req_t *req;
+
+ parse_asm_constraints(&parsed_constraint, c, false);
+ req = make_register_req(&parsed_constraint, n_out_constraints,
+ out_reg_reqs, i);
+ in_reg_reqs[i] = req;
+
+ if (parsed_constraint.immediate_type != '\0') {
+ char imm_type = parsed_constraint.immediate_type;
+ input = try_create_Immediate(pred, imm_type);
+ }
+
+ if (input == NULL) {
+ ir_node *pred = get_irn_n(node, i);
+ input = be_transform_node(pred);
+
+ if (parsed_constraint.cls == NULL
+ && parsed_constraint.same_as < 0) {
+ is_memory_op = true;
+ } else if(parsed_constraint.memory_possible) {
+ /* TODO: match Load or Load/Store if memory possible is set */
+ }
+ }
+ in[i] = input;
+
+ register_map[pos].use_input = true;
+ register_map[pos].valid = true;
+ register_map[pos].memory = is_memory_op;
register_map[pos].inout_pos = i;
register_map[pos].mode = constraint->mode;
+ }
- if(in[i] != NULL)
+ /* parse clobbers */
+ for(i = 0; i < get_ASM_n_clobbers(node); ++i) {
+ const char *c = get_id_str(clobbers[i]);
+ const arch_register_req_t *req;
+
+ if (strcmp(c, "memory") == 0 || strcmp(c, "cc") == 0)
continue;
- transformed = be_transform_node(pred);
- in[i] = transformed;
+ req = parse_clobber(c);
+ out_reg_reqs[out_idx] = req;
+ ++out_idx;
}
new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
add_irn_dep(ret, get_irg_frame(irg));
return ret;
}
- } else if (mode_needs_gp_reg(mode)) {
+ } else if (ia32_mode_needs_gp_reg(mode)) {
return ia32_new_Unknown_gp(env_cg);
} else {
panic("unsupported Unknown-Mode");
ir_mode *mode = get_irn_mode(node);
ir_node *phi;
- if(mode_needs_gp_reg(mode)) {
+ if(ia32_mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
/* all integer operations are on 32bit registers now */
{
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *op = get_IJmp_target(node);
ir_node *new_node;
match_am | match_8bit_am | match_16bit_am |
match_immediate | match_8bit | match_16bit);
- new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
- addr->mem, am.new_op2);
+ new_node = new_rd_ia32_IJmp(dbgi, current_ir_graph, new_block,
+ addr->base, addr->index, addr->mem,
+ am.new_op2);
set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
return new_node;
}
+/**
+ * Transform a Bound node.
+ */
+static ir_node *gen_Bound(ir_node *node)
+{
+ ir_node *new_node;
+ ir_node *lower = get_Bound_lower(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+
+ if (is_Const_0(lower)) {
+ /* typical case for Java */
+ ir_node *sub, *res, *flags, *block;
+ ir_graph *irg = current_ir_graph;
+
+ res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
+ new_rd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
+
+ block = get_nodes_block(res);
+ if (! is_Proj(res)) {
+ sub = res;
+ set_irn_mode(sub, mode_T);
+ res = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_res);
+ } else {
+ sub = get_Proj_pred(res);
+ }
+ flags = new_rd_Proj(NULL, irg, block, sub, mode_Iu, pn_ia32_Sub_flags);
+ new_node = new_rd_ia32_Jcc(dbgi, irg, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ } else {
+ panic("generic Bound not supported in ia32 Backend");
+ }
+ return new_node;
+}
+
+
typedef ir_node *construct_load_func(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, \
ir_node *mem);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_mode *mode = get_ia32_ls_mode(node);
- ir_node *new_op;
+ ir_node *memres, *fist;
long am_offs;
- new_op = gen_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, new_val);
+ memres = gen_vfist(dbgi, irg, block, new_ptr, noreg, new_mem, new_val, &fist);
am_offs = get_ia32_am_offs_int(node);
- add_ia32_am_offs_int(new_op, am_offs);
+ add_ia32_am_offs_int(fist, am_offs);
- set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_ls_mode(new_op, mode);
- set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
- set_ia32_use_frame(new_op);
+ set_ia32_op_type(fist, ia32_AddrModeD);
+ set_ia32_ls_mode(fist, mode);
+ set_ia32_frame_ent(fist, get_ia32_frame_ent(node));
+ set_ia32_use_frame(fist);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
- return new_op;
+ return memres;
}
/**
ir_node *nomem = new_NoMem();
ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
ir_node *new_val = be_transform_node(val);
+ ir_node *fist, *mem;
- ir_node *fist = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val);
+ mem = gen_vfist(dbgi, irg, block, frame, noreg, nomem, new_val, &fist);
SET_IA32_ORIG_NODE(fist, ia32_get_old_node_name(env_cg, node));
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
- return fist;
+ return mem;
}
/**
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
-
/* loads might be part of source address mode matches, so we don't
- transform the ProjMs yet (with the exception of loads whose result is
- not used)
+ * transform the ProjMs yet (with the exception of loads whose result is
+ * not used)
*/
if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
ir_node *res;
- assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
- nodes is 1 */
/* this is needed, because sometimes we have loops that are only
reachable through the ProjM */
be_enqueue_preds(node);
/* do it in 2 steps, to silence firm verifier */
res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
- set_Proj_proj(res, pn_ia32_Load_M);
+ set_Proj_proj(res, pn_ia32_mem);
return res;
}
node);
}
+/**
+ * Transform the Projs from a Bound.
+ */
+static ir_node *gen_Proj_Bound(ir_node *node)
+{
+ ir_node *new_node, *block;
+ ir_node *pred = get_Proj_pred(node);
+
+ switch (get_Proj_proj(node)) {
+ case pn_Bound_M:
+ return be_transform_node(get_Bound_mem(pred));
+ case pn_Bound_X_regular:
+ new_node = be_transform_node(pred);
+ block = get_nodes_block(new_node);
+ return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_true);
+ case pn_Bound_X_except:
+ new_node = be_transform_node(pred);
+ block = get_nodes_block(new_node);
+ return new_r_Proj(current_ir_graph, block, new_node, mode_X, pn_ia32_Jcc_false);
+ case pn_Bound_res:
+ return be_transform_node(get_Bound_index(pred));
+ default:
+ panic("unsupported Proj from Bound");
+ }
+}
+
/**
* Transform and potentially renumber Proj nodes.
*/
static ir_node *gen_Proj(ir_node *node) {
- ir_node *pred = get_Proj_pred(node);
- if (is_Store(pred)) {
- long proj = get_Proj_proj(node);
+ ir_node *pred = get_Proj_pred(node);
+ long proj;
+
+ switch (get_irn_opcode(pred)) {
+ case iro_Store:
+ proj = get_Proj_proj(node);
if (proj == pn_Store_M) {
return be_transform_node(pred);
} else {
assert(0);
return new_r_Bad(current_ir_graph);
}
- } else if (is_Load(pred)) {
+ case iro_Load:
return gen_Proj_Load(node);
- } else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
+ case iro_Div:
+ case iro_Mod:
+ case iro_DivMod:
return gen_Proj_DivMod(node);
- } else if (is_CopyB(pred)) {
+ case iro_CopyB:
return gen_Proj_CopyB(node);
- } else if (is_Quot(pred)) {
+ case iro_Quot:
return gen_Proj_Quot(node);
- } else if (be_is_SubSP(pred)) {
+ case beo_SubSP:
return gen_Proj_be_SubSP(node);
- } else if (be_is_AddSP(pred)) {
+ case beo_AddSP:
return gen_Proj_be_AddSP(node);
- } else if (be_is_Call(pred)) {
+ case beo_Call:
return gen_Proj_be_Call(node);
- } else if (is_Cmp(pred)) {
+ case iro_Cmp:
return gen_Proj_Cmp(node);
- } else if (get_irn_op(pred) == op_Start) {
- long proj = get_Proj_proj(node);
+ case iro_Bound:
+ return gen_Proj_Bound(node);
+ case iro_Start:
+ proj = get_Proj_proj(node);
if (proj == pn_Start_X_initial_exec) {
ir_node *block = get_nodes_block(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
if (node == be_get_old_anchor(anchor_tls)) {
return gen_Proj_tls(node);
}
- } else if (is_ia32_l_FloattoLL(pred)) {
- return gen_Proj_l_FloattoLL(node);
+ break;
+
+ default:
+ if (is_ia32_l_FloattoLL(pred)) {
+ return gen_Proj_l_FloattoLL(node);
#ifdef FIRM_EXT_GRS
- } else if(!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
+ } else if (!is_ia32_irn(pred)) { // Quick hack for SIMD optimization
#else
- } else {
+ } else {
#endif
- ir_mode *mode = get_irn_mode(node);
- if (mode_needs_gp_reg(mode)) {
- ir_node *new_pred = be_transform_node(pred);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred,
- mode_Iu, get_Proj_proj(node));
+ ir_mode *mode = get_irn_mode(node);
+ if (ia32_mode_needs_gp_reg(mode)) {
+ ir_node *new_pred = be_transform_node(pred);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *new_proj = new_r_Proj(current_ir_graph, block, new_pred,
+ mode_Iu, get_Proj_proj(node));
#ifdef DEBUG_libfirm
- new_proj->node_nr = node->node_nr;
+ new_proj->node_nr = node->node_nr;
#endif
- return new_proj;
+ return new_proj;
+ }
}
}
-
return be_duplicate_node(node);
}
GEN(Shl);
GEN(Shr);
GEN(Shrs);
- GEN(Rot);
+ GEN(Rotl);
GEN(Quot);
GEN(Proj);
GEN(Phi);
GEN(IJmp);
+ GEN(Bound);
/* transform ops from intrinsic lowering */
GEN(ia32_l_Add);
/**
* Walker, checks if all ia32 nodes producing more than one result have
- * its Projs, other wise creates new projs and keep them using a be_Keep node.
+ * its Projs, otherwise creates new Projs and keep them using a be_Keep node.
*/
static void add_missing_keep_walker(ir_node *node, void *data)
{
ir_node *block;
ir_node *in[1];
const arch_register_req_t *req;
- const arch_register_class_t *class;
+ const arch_register_class_t *cls;
if(found_projs & (1 << i)) {
continue;
}
req = get_ia32_out_req(node, i);
- class = req->cls;
- if(class == NULL) {
+ cls = req->cls;
+ if(cls == NULL) {
continue;
}
- if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
+ if(cls == &ia32_reg_classes[CLASS_ia32_flags]) {
continue;
}
block = get_nodes_block(node);
in[0] = new_r_Proj(current_ir_graph, block, node,
- arch_register_class_mode(class), i);
+ arch_register_class_mode(cls), i);
if(last_keep != NULL) {
- be_Keep_add_node(last_keep, class, in[0]);
+ be_Keep_add_node(last_keep, cls, in[0]);
} else {
- last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
+ last_keep = be_new_Keep(cls, current_ir_graph, block, 1, in);
if(sched_is_scheduled(node)) {
sched_add_after(node, last_keep);
}
env_cg = cg;
initial_fpcw = NULL;
-BE_TIMER_PUSH(t_heights);
+ BE_TIMER_PUSH(t_heights);
heights = heights_new(irg);
-BE_TIMER_POP(t_heights);
+ BE_TIMER_POP(t_heights);
ia32_calculate_non_address_mode_nodes(cg->birg);
/* the transform phase is not safe for CSE (yet) because several nodes get
projects / libfirm / blobdiff