#include "irdom.h"
#include "archop.h"
#include "error.h"
+#include "height.h"
#include "../benode_t.h"
#include "../besched.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
#include "ia32_util.h"
+#include "ia32_address_mode.h"
#include "gen_ia32_regalloc_if.h"
-#define SFP_SIGN "0x80000000"
-#define DFP_SIGN "0x8000000000000000"
-#define SFP_ABS "0x7FFFFFFF"
-#define DFP_ABS "0x7FFFFFFFFFFFFFFF"
+#define SFP_SIGN "0x80000000"
+#define DFP_SIGN "0x8000000000000000"
+#define SFP_ABS "0x7FFFFFFF"
+#define DFP_ABS "0x7FFFFFFFFFFFFFFF"
+#define DFP_INTMAX "9223372036854775807"
#define TP_SFP_SIGN "ia32_sfp_sign"
#define TP_DFP_SIGN "ia32_dfp_sign"
#define TP_SFP_ABS "ia32_sfp_abs"
#define TP_DFP_ABS "ia32_dfp_abs"
+#define TP_INT_MAX "ia32_int_max"
#define ENT_SFP_SIGN "IA32_SFP_SIGN"
#define ENT_DFP_SIGN "IA32_DFP_SIGN"
#define ENT_SFP_ABS "IA32_SFP_ABS"
#define ENT_DFP_ABS "IA32_DFP_ABS"
+#define ENT_INT_MAX "IA32_INT_MAX"
#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
/** hold the current code generator during transformation */
static ia32_code_gen_t *env_cg = NULL;
static ir_node *initial_fpcw = NULL;
+static heights_t *heights = NULL;
+static transform_config_t transform_config;
extern ir_op *get_op_Mulh(void);
typedef ir_node *construct_binop_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
- ir_node *op2, ir_node *mem);
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op1, ir_node *op2);
+
+typedef ir_node *construct_binop_flags_func(dbg_info *db, ir_graph *irg,
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op1, ir_node *op2, ir_node *flags);
+
+typedef ir_node *construct_shift_func(dbg_info *db, ir_graph *irg,
+ ir_node *block, ir_node *op1, ir_node *op2);
+
+typedef ir_node *construct_binop_dest_func(dbg_info *db, ir_graph *irg,
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op);
+
+typedef ir_node *construct_unop_dest_func(dbg_info *db, ir_graph *irg,
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
typedef ir_node *construct_binop_float_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *op1,
- ir_node *op2, ir_node *mem, ir_node *fpcw);
+ ir_node *block, ir_node *base, ir_node *index, ir_node *mem,
+ ir_node *op1, ir_node *op2, ir_node *fpcw);
typedef ir_node *construct_unop_func(dbg_info *db, ir_graph *irg,
- ir_node *block, ir_node *base, ir_node *index, ir_node *op,
- ir_node *mem);
+ ir_node *block, ir_node *op);
/****************************************************************************************************
* _ _ __ _ _
char immediate_constraint_type);
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
- dbg_info *dbgi, ir_node *new_block,
- ir_node *new_op);
+ dbg_info *dbgi, ir_node *block,
+ ir_node *op, ir_node *orig_node);
/**
* Return true if a mode can be stored in the GP register set
static INLINE int mode_needs_gp_reg(ir_mode *mode) {
if(mode == mode_fpcw)
return 0;
+ if(get_mode_size_bits(mode) > 32)
+ return 0;
return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
}
-/**
- * Returns 1 if irn is a Const representing 0, 0 otherwise
- */
-static INLINE int is_ia32_Const_0(ir_node *irn) {
- return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
- && tarval_is_null(get_ia32_Immop_tarval(irn));
-}
-
-/**
- * Returns 1 if irn is a Const representing 1, 0 otherwise
- */
-static INLINE int is_ia32_Const_1(ir_node *irn) {
- return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
- && tarval_is_one(get_ia32_Immop_tarval(irn));
-}
-
-/**
- * Collects all Projs of a node into the node array. Index is the projnum.
- * BEWARE: The caller has to assure the appropriate array size!
- */
-static void ia32_collect_Projs(ir_node *irn, ir_node **projs, int size) {
- const ir_edge_t *edge;
- assert(get_irn_mode(irn) == mode_T && "need mode_T");
-
- memset(projs, 0, size * sizeof(projs[0]));
-
- foreach_out_edge(irn, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- int proj_proj = get_Proj_proj(proj);
- assert(proj_proj < size);
- projs[proj_proj] = proj;
- }
-}
-
-/**
- * Renumbers the proj having pn_old in the array tp pn_new
- * and removes the proj from the array.
- */
-static INLINE void ia32_renumber_Proj(ir_node **projs, long pn_old, long pn_new) {
- fprintf(stderr, "Warning: renumber_Proj used!\n");
- if (projs[pn_old]) {
- set_Proj_proj(projs[pn_old], pn_new);
- projs[pn_old] = NULL;
- }
-}
-
/**
* creates a unique ident by adding a number to a tag
*
}
/**
- * Get an entity that is initialized with a tarval
+ * Get an atomic entity that is initialized with a tarval
*/
-static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
+static ir_entity *create_float_const_entity(ir_node *cnst)
{
- tarval *tv = get_Const_tarval(cnst);
- pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
+ ia32_isa_t *isa = env_cg->isa;
+ tarval *tv = get_Const_tarval(cnst);
+ pmap_entry *e = pmap_find(isa->tv_ent, tv);
ir_entity *res;
ir_graph *rem;
ir_mode *mode = get_irn_mode(cnst);
ir_type *tp = get_Const_type(cnst);
if (tp == firm_unknown_type)
- tp = get_prim_type(cg->isa->types, mode);
+ tp = get_prim_type(isa->types, mode);
res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
set_atomic_ent_value(res, new_Const_type(tv, tp));
current_ir_graph = rem;
- pmap_insert(cg->isa->tv_ent, tv, res);
+ pmap_insert(isa->tv_ent, tv, res);
} else {
res = e->value;
}
}
static int is_Const_0(ir_node *node) {
- if(!is_Const(node))
- return 0;
-
- return classify_Const(node) == CNST_NULL;
+ return is_Const(node) && is_Const_null(node);
}
static int is_Const_1(ir_node *node) {
- if(!is_Const(node))
- return 0;
+ return is_Const(node) && is_Const_one(node);
+}
+
+static int is_Const_Minus_1(ir_node *node) {
+ return is_Const(node) && is_Const_all_one(node);
+}
+
+/**
+ * returns true if constant can be created with a simple float command
+ */
+static int is_simple_x87_Const(ir_node *node)
+{
+ tarval *tv = get_Const_tarval(node);
+
+ if(tarval_is_null(tv) || tarval_is_one(tv))
+ return 1;
- return classify_Const(node) == CNST_ONE;
+ /* TODO: match all the other float constants */
+ return 0;
}
/**
ir_node *load;
ir_entity *floatent;
- if (! USE_SSE2(env_cg)) {
- cnst_classify_t clss = classify_Const(node);
+ if (USE_SSE2(env_cg)) {
+ if (is_Const_null(node)) {
+ load = new_rd_ia32_xZero(dbgi, irg, block);
+ set_ia32_ls_mode(load, mode);
+ res = load;
+ } else {
+ floatent = create_float_const_entity(node);
- if (clss == CNST_NULL) {
+ load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem,
+ mode);
+ set_ia32_op_type(load, ia32_AddrModeS);
+ set_ia32_am_sc(load, floatent);
+ set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
+ res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
+ }
+ } else {
+ if (is_Const_null(node)) {
load = new_rd_ia32_vfldz(dbgi, irg, block);
res = load;
- } else if (clss == CNST_ONE) {
+ } else if (is_Const_one(node)) {
load = new_rd_ia32_vfld1(dbgi, irg, block);
res = load;
} else {
- floatent = get_entity_for_tv(env_cg, node);
+ floatent = create_float_const_entity(node);
load = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode);
set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_am_flavour(load, ia32_am_N);
set_ia32_am_sc(load, floatent);
set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
res = new_r_Proj(irg, block, load, mode_vfp, pn_ia32_vfld_res);
}
set_ia32_ls_mode(load, mode);
- } else {
- floatent = get_entity_for_tv(env_cg, node);
-
- load = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem);
- set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_am_flavour(load, ia32_am_N);
- set_ia32_am_sc(load, floatent);
- set_ia32_ls_mode(load, mode);
- set_ia32_flags(load, get_ia32_flags(load) | arch_irn_flags_rematerializable);
-
- res = new_r_Proj(irg, block, load, mode_xmm, pn_ia32_xLoad_res);
}
SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
return res;
} else {
- ir_node *cnst = new_rd_ia32_Const(dbgi, irg, block);
+ ir_node *cnst;
+ tarval *tv = get_Const_tarval(node);
+ long val;
+
+ tv = tarval_convert_to(tv, mode_Iu);
+
+ if(tv == get_tarval_bad() || tv == get_tarval_undefined()
+ || tv == NULL) {
+ panic("couldn't convert constant tarval (%+F)", node);
+ }
+ val = get_tarval_long(tv);
+
+ cnst = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, val);
+ SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
/* see above */
if (get_irg_start_block(irg) == block) {
add_irn_dep(cnst, get_irg_frame(irg));
}
- set_ia32_Const_attr(cnst, node);
- SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
return cnst;
}
-
- assert(0);
- return new_r_Bad(irg);
}
/**
ir_node *cnst;
if (mode_is_float(mode)) {
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
+
if (USE_SSE2(env_cg))
- cnst = new_rd_ia32_xConst(dbgi, irg, block);
+ cnst = new_rd_ia32_xLoad(dbgi, irg, block, noreg, noreg, nomem, mode_E);
else
- cnst = new_rd_ia32_vfConst(dbgi, irg, block);
- //set_ia32_ls_mode(cnst, mode);
- set_ia32_ls_mode(cnst, mode_E);
+ cnst = new_rd_ia32_vfld(dbgi, irg, block, noreg, noreg, nomem, mode_E);
+ set_ia32_am_sc(cnst, get_SymConst_entity(node));
+ set_ia32_use_frame(cnst);
} else {
- cnst = new_rd_ia32_Const(dbgi, irg, block);
+ ir_entity *entity;
+
+ if(get_SymConst_kind(node) != symconst_addr_ent) {
+ panic("backend only support symconst_addr_ent (at %+F)", node);
+ }
+ entity = get_SymConst_entity(node);
+ cnst = new_rd_ia32_Const(dbgi, irg, block, entity, 0, 0);
}
/* Const Nodes before the initial IncSP are a bad idea, because
add_irn_dep(cnst, get_irg_frame(irg));
}
- set_ia32_Const_attr(cnst, node);
SET_IA32_ORIG_NODE(cnst, ia32_get_old_node_name(env_cg, node));
return cnst;
const char *tp_name;
const char *ent_name;
const char *cnst_str;
+ char mode;
+ char align;
} names [ia32_known_const_max] = {
- { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
- { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
- { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
- { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
+ { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
+ { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
+ { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
+ { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
+ { TP_INT_MAX, ENT_INT_MAX, DFP_INTMAX, 2, 4 } /* ia32_INTMAX */
};
static ir_entity *ent_cache[ia32_known_const_max];
tp_name = names[kct].tp_name;
cnst_str = names[kct].cnst_str;
- mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
- //mode = mode_xmm;
+ switch (names[kct].mode) {
+ case 0: mode = mode_Iu; break;
+ case 1: mode = mode_Lu; break;
+ default: mode = mode_F; break;
+ }
tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
tp = new_type_primitive(new_id_from_str(tp_name), mode);
+ /* set the specified alignment */
+ set_type_alignment_bytes(tp, names[kct].align);
+
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
set_entity_ld_ident(ent, get_entity_ident(ent));
}
#endif /* NDEBUG */
-/* determine if one operator is an Imm */
-static ir_node *get_immediate_op(ir_node *op1, ir_node *op2) {
- if (op1) {
- return is_ia32_Cnst(op1) ? op1 : (is_ia32_Cnst(op2) ? op2 : NULL);
- } else {
- return is_ia32_Cnst(op2) ? op2 : NULL;
+int ia32_use_source_address_mode(ir_node *block, ir_node *node, ir_node *other)
+{
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *load;
+ long pn;
+
+ /* float constants are always available */
+ if(is_Const(node) && mode_is_float(mode)) {
+ if(!is_simple_x87_Const(node))
+ return 0;
+ if(get_irn_n_edges(node) > 1)
+ return 0;
+ return 1;
}
+
+ if(!is_Proj(node))
+ return 0;
+ load = get_Proj_pred(node);
+ pn = get_Proj_proj(node);
+ if(!is_Load(load) || pn != pn_Load_res)
+ return 0;
+ if(get_nodes_block(load) != block)
+ return 0;
+ /* we only use address mode if we're the only user of the load */
+ if(get_irn_n_edges(node) > 1)
+ return 0;
+ /* in some edge cases with address mode we might reach the load normally
+ * and through some AM sequence, if it is already materialized then we
+ * can't create an AM node from it */
+ if(be_is_transformed(node))
+ return 0;
+
+ /* don't do AM if other node inputs depend on the load (via mem-proj) */
+ if(other != NULL && get_nodes_block(other) == block
+ && heights_reachable_in_block(heights, other, load))
+ return 0;
+
+ return 1;
}
-/* determine if one operator is not an Imm */
-static ir_node *get_expr_op(ir_node *op1, ir_node *op2) {
- return !is_ia32_Cnst(op1) ? op1 : (!is_ia32_Cnst(op2) ? op2 : NULL);
+typedef struct ia32_address_mode_t ia32_address_mode_t;
+struct ia32_address_mode_t {
+ ia32_address_t addr;
+ ir_mode *ls_mode;
+ ir_node *mem_proj;
+ ia32_op_type_t op_type;
+ ir_node *new_op1;
+ ir_node *new_op2;
+ op_pin_state pinned;
+ unsigned commutative : 1;
+ unsigned ins_permuted : 1;
+};
+
+static void build_address_ptr(ia32_address_t *addr, ir_node *ptr, ir_node *mem)
+{
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
+
+ /* construct load address */
+ memset(addr, 0, sizeof(addr[0]));
+ ia32_create_address_mode(addr, ptr, /*force=*/0);
+
+ if(addr->base == NULL) {
+ addr->base = noreg_gp;
+ } else {
+ addr->base = be_transform_node(addr->base);
+ }
+
+ if(addr->index == NULL) {
+ addr->index = noreg_gp;
+ } else {
+ addr->index = be_transform_node(addr->index);
+ }
+ addr->mem = be_transform_node(mem);
}
-static void fold_immediate(ir_node *node, int in1, int in2) {
- ir_node *left;
- ir_node *right;
+static void build_address(ia32_address_mode_t *am, ir_node *node)
+{
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
+ ia32_address_t *addr = &am->addr;
+ ir_node *load;
+ ir_node *ptr;
+ ir_node *mem;
+ ir_node *new_mem;
+ ir_node *base;
+ ir_node *index;
- if (!(env_cg->opt & IA32_OPT_IMMOPS))
+ if(is_Const(node)) {
+ ir_entity *entity = create_float_const_entity(node);
+ addr->base = noreg_gp;
+ addr->index = noreg_gp;
+ addr->mem = new_NoMem();
+ addr->symconst_ent = entity;
+ addr->use_frame = 1;
+ am->ls_mode = get_irn_mode(node);
+ am->pinned = op_pin_state_floats;
return;
+ }
- left = get_irn_n(node, in1);
- right = get_irn_n(node, in2);
- if (! is_ia32_Cnst(right) && is_ia32_Cnst(left)) {
- /* we can only set right operand to immediate */
- if(!is_ia32_commutative(node))
- return;
- /* exchange left/right */
- set_irn_n(node, in1, right);
- set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
- copy_ia32_Immop_attr(node, left);
- } else if(is_ia32_Cnst(right)) {
- set_irn_n(node, in2, ia32_get_admissible_noreg(env_cg, node, in2));
- copy_ia32_Immop_attr(node, right);
+ load = get_Proj_pred(node);
+ ptr = get_Load_ptr(load);
+ mem = get_Load_mem(load);
+ new_mem = be_transform_node(mem);
+ am->pinned = get_irn_pinned(load);
+ am->ls_mode = get_Load_mode(load);
+ am->mem_proj = be_get_Proj_for_pn(load, pn_Load_M);
+
+ /* construct load address */
+ ia32_create_address_mode(addr, ptr, /*force=*/0);
+ base = addr->base;
+ index = addr->index;
+
+ if(base == NULL) {
+ base = noreg_gp;
} else {
- return;
+ base = be_transform_node(base);
+ }
+
+ if(index == NULL) {
+ index = noreg_gp;
+ } else {
+ index = be_transform_node(index);
}
- clear_ia32_commutative(node);
- set_ia32_am_support(node, get_ia32_am_support(node) & ~ia32_am_Source,
- get_ia32_am_arity(node));
+ addr->base = base;
+ addr->index = index;
+ addr->mem = new_mem;
+}
+
+static void set_address(ir_node *node, const ia32_address_t *addr)
+{
+ set_ia32_am_scale(node, addr->scale);
+ set_ia32_am_sc(node, addr->symconst_ent);
+ set_ia32_am_offs_int(node, addr->offset);
+ if(addr->symconst_sign)
+ set_ia32_am_sc_sign(node);
+ if(addr->use_frame)
+ set_ia32_use_frame(node);
+ set_ia32_frame_ent(node, addr->frame_entity);
+}
+
+static void set_am_attributes(ir_node *node, const ia32_address_mode_t *am)
+{
+ set_address(node, &am->addr);
+
+ set_ia32_op_type(node, am->op_type);
+ set_ia32_ls_mode(node, am->ls_mode);
+ if(am->pinned == op_pin_state_pinned && get_irn_pinned(node) != op_pin_state_pinned) {
+ set_irn_pinned(node, am->pinned);
+ }
+ if(am->commutative)
+ set_ia32_commutative(node);
}
/**
- * Construct a standard binary operation, set AM and immediate if required.
+ * Check, if a given node is a Down-Conv, ie. a integer Conv
+ * from a mode with a mode with more bits to a mode with lesser bits.
+ * Moreover, we return only true if the node has not more than 1 user.
*
- * @param op1 The first operand
- * @param op2 The second operand
- * @param func The node constructor function
- * @return The constructed ia32 node.
+ * @param node the node
+ * @return non-zero if node is a Down-Conv
*/
-static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
- construct_binop_func *func, int commutative)
+static int is_downconv(const ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *new_node;
+ ir_mode *src_mode;
+ ir_mode *dest_mode;
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *new_op2 = create_immediate_or_transform(op2, 0);
- if (is_ia32_Immediate(new_op2)) {
- commutative = 0;
- }
+ if(!is_Conv(node))
+ return 0;
+
+ /* we only want to skip the conv when we're the only user
+ * (not optimal but for now...)
+ */
+ if(get_irn_n_edges(node) > 1)
+ return 0;
+
+ src_mode = get_irn_mode(get_Conv_op(node));
+ dest_mode = get_irn_mode(node);
+ return mode_needs_gp_reg(src_mode)
+ && mode_needs_gp_reg(dest_mode)
+ && get_mode_size_bits(dest_mode) < get_mode_size_bits(src_mode);
+}
+
+/* Skip all Down-Conv's on a given node and return the resulting node. */
+ir_node *ia32_skip_downconv(ir_node *node) {
+ while (is_downconv(node))
+ node = get_Conv_op(node);
+
+ return node;
+}
+
+#if 0
+static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
+{
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *block;
+ ir_mode *tgt_mode;
+ dbg_info *dbgi;
- new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
- if (func == new_rd_ia32_IMul) {
- set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
+ if(mode_is_signed(mode)) {
+ tgt_mode = mode_Is;
} else {
- set_ia32_am_support(new_node, ia32_am_Full, ia32_am_binary);
+ tgt_mode = mode_Iu;
}
+ block = get_nodes_block(node);
+ dbgi = get_irn_dbg_info(node);
- SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- if (commutative) {
- set_ia32_commutative(new_node);
+ return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
+}
+#endif
+
+static void match_arguments(ia32_address_mode_t *am, ir_node *block,
+ ir_node *op1, ir_node *op2, match_flags_t flags)
+{
+ ia32_address_t *addr = &am->addr;
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
+ ir_node *new_op1;
+ ir_node *new_op2;
+ ir_mode *mode = get_irn_mode(op2);
+ int use_am;
+ unsigned commutative;
+ int use_am_and_immediates;
+ int use_immediate;
+ int mode_bits = get_mode_size_bits(mode);
+
+ memset(am, 0, sizeof(am[0]));
+
+ commutative = (flags & match_commutative) != 0;
+ use_am_and_immediates = (flags & match_am_and_immediates) != 0;
+ use_am = (flags & match_am) != 0;
+ use_immediate = (flags & match_immediate) != 0;
+ assert(!use_am_and_immediates || use_immediate);
+
+ assert(op2 != NULL);
+ assert(!commutative || op1 != NULL);
+
+ if(mode_bits == 8) {
+ if (! (flags & match_8bit_am))
+ use_am = 0;
+ assert((flags & match_mode_neutral) || (flags & match_8bit));
+ } else if(mode_bits == 16) {
+ if(! (flags & match_16bit_am))
+ use_am = 0;
+ assert((flags & match_mode_neutral) || (flags & match_16bit));
}
- return new_node;
+ /* we can simply skip downconvs for mode neutral nodes: the upper bits
+ * can be random for these operations */
+ if(flags & match_mode_neutral) {
+ op2 = ia32_skip_downconv(op2);
+ if(op1 != NULL) {
+ op1 = ia32_skip_downconv(op1);
+ }
+ }
+
+ if(! (flags & match_try_am) && use_immediate)
+ new_op2 = try_create_Immediate(op2, 0);
+ else
+ new_op2 = NULL;
+
+ if(new_op2 == NULL && use_am && ia32_use_source_address_mode(block, op2, op1)) {
+ build_address(am, op2);
+ new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
+ if(mode_is_float(mode)) {
+ new_op2 = ia32_new_NoReg_vfp(env_cg);
+ } else {
+ new_op2 = noreg_gp;
+ }
+ am->op_type = ia32_AddrModeS;
+ } else if(commutative && (new_op2 == NULL || use_am_and_immediates) &&
+ use_am && ia32_use_source_address_mode(block, op1, op2)) {
+ ir_node *noreg;
+ build_address(am, op1);
+
+ if(mode_is_float(mode)) {
+ noreg = ia32_new_NoReg_vfp(env_cg);
+ } else {
+ noreg = noreg_gp;
+ }
+
+ if(new_op2 != NULL) {
+ new_op1 = noreg;
+ } else {
+ new_op1 = be_transform_node(op2);
+ new_op2 = noreg;
+ am->ins_permuted = 1;
+ }
+ am->op_type = ia32_AddrModeS;
+ } else {
+ if(flags & match_try_am) {
+ am->new_op1 = NULL;
+ am->new_op2 = NULL;
+ am->op_type = ia32_Normal;
+ return;
+ }
+
+ new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
+ if(new_op2 == NULL)
+ new_op2 = be_transform_node(op2);
+ am->op_type = ia32_Normal;
+ am->ls_mode = get_irn_mode(op2);
+ if(flags & match_mode_neutral)
+ am->ls_mode = mode_Iu;
+ }
+ if(addr->base == NULL)
+ addr->base = noreg_gp;
+ if(addr->index == NULL)
+ addr->index = noreg_gp;
+ if(addr->mem == NULL)
+ addr->mem = new_NoMem();
+
+ am->new_op1 = new_op1;
+ am->new_op2 = new_op2;
+ am->commutative = commutative;
+}
+
+static ir_node *fix_mem_proj(ir_node *node, ia32_address_mode_t *am)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_mode *mode;
+ ir_node *load;
+
+ if(am->mem_proj == NULL)
+ return node;
+
+ /* we have to create a mode_T so the old MemProj can attach to us */
+ mode = get_irn_mode(node);
+ load = get_Proj_pred(am->mem_proj);
+
+ mark_irn_visited(load);
+ be_set_transformed_node(load, node);
+
+ if(mode != mode_T) {
+ set_irn_mode(node, mode_T);
+ return new_rd_Proj(NULL, irg, get_nodes_block(node), node, mode, pn_ia32_res);
+ } else {
+ return node;
+ }
}
/**
* @param func The node constructor function
* @return The constructed ia32 node.
*/
-static ir_node *gen_binop_sse_float(ir_node *node, ir_node *op1, ir_node *op2,
- construct_binop_func *func)
+static ir_node *gen_binop(ir_node *node, ir_node *op1, ir_node *op2,
+ construct_binop_func *func, match_flags_t flags)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *new_op2 = be_transform_node(op2);
- ir_node *new_node = NULL;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_graph *irg = current_ir_graph;
- ir_mode *mode = get_irn_mode(node);
- ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
- new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
- nomem);
- set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
- if (is_op_commutative(get_irn_op(node))) {
- set_ia32_commutative(new_node);
- }
- set_ia32_ls_mode(new_node, mode);
+ match_arguments(&am, block, op1, op2, flags);
+
+ new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
+ am.new_op1, am.new_op2);
+ set_am_attributes(new_node, &am);
+ /* we can't use source address mode anymore when using immediates */
+ if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
+ set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ new_node = fix_mem_proj(new_node, &am);
+
+ return new_node;
+}
+
+enum {
+ n_ia32_l_binop_left,
+ n_ia32_l_binop_right,
+ n_ia32_l_binop_eflags
+};
+COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
+COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
+COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
+COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_left, n_Sbb_left)
+COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_right, n_Sbb_right)
+COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
+/**
+ * Construct a binary operation which also consumes the eflags.
+ *
+ * @param node The node to transform
+ * @param func The node constructor function
+ * @param flags The match flags
+ * @return The constructor ia32 node
+ */
+static ir_node *gen_binop_flags(ir_node *node, construct_binop_flags_func *func,
+ match_flags_t flags)
+{
+ ir_node *src_block = get_nodes_block(node);
+ ir_node *block = be_transform_node(src_block);
+ ir_node *op1 = get_irn_n(node, n_ia32_l_binop_left);
+ ir_node *op2 = get_irn_n(node, n_ia32_l_binop_right);
+ ir_node *eflags = get_irn_n(node, n_ia32_l_binop_eflags);
+ ir_node *new_eflags = be_transform_node(eflags);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+
+ match_arguments(&am, src_block, op1, op2, flags);
+
+ new_node = func(dbgi, irg, block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, new_eflags);
+ set_am_attributes(new_node, &am);
+ /* we can't use source address mode anymore when using immediates */
+ if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
+ set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = fix_mem_proj(new_node, &am);
+
return new_node;
}
* @return The constructed ia32 node.
*/
static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
- construct_binop_float_func *func)
+ construct_binop_float_func *func,
+ match_flags_t flags)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *new_op2 = be_transform_node(op2);
- ir_node *new_node = NULL;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_graph *irg = current_ir_graph;
- ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
- new_node = func(dbgi, irg, block, noreg_gp, noreg_gp, new_op1, new_op2,
- nomem, get_fpcw());
- set_ia32_am_support(new_node, ia32_am_Source, ia32_am_binary);
- if (is_op_commutative(get_irn_op(node))) {
- set_ia32_commutative(new_node);
- }
+ match_arguments(&am, block, op1, op2, flags);
+
+ new_node = func(dbgi, irg, new_block, addr->base, addr->index, addr->mem,
+ am.new_op1, am.new_op2, get_fpcw());
+ set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = fix_mem_proj(new_node, &am);
+
return new_node;
}
* @return The constructed ia32 node.
*/
static ir_node *gen_shift_binop(ir_node *node, ir_node *op1, ir_node *op2,
- construct_binop_func *func)
+ construct_shift_func *func,
+ match_flags_t flags)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op1 = be_transform_node(op1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_graph *irg = current_ir_graph;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *new_op1;
ir_node *new_op2;
- ir_node *new_op = NULL;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_graph *irg = current_ir_graph;
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
-
- assert(! mode_is_float(get_irn_mode(node))
- && "Shift/Rotate with float not supported");
-
- new_op2 = create_immediate_or_transform(op2, 'N');
+ ir_node *new_node;
- new_op = func(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
+ assert(! mode_is_float(mode));
+ assert(flags & match_immediate);
+ assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
+ if(flags & match_mode_neutral) {
+ op1 = ia32_skip_downconv(op1);
+ }
+ new_op1 = be_transform_node(op1);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ /* the shift amount can be any mode that is bigger than 5 bits, since all
+ * other bits are ignored anyway */
+ while (is_Conv(op2) && get_irn_n_edges(op2) == 1) {
+ op2 = get_Conv_op(op2);
+ assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
+ }
+ new_op2 = create_immediate_or_transform(op2, 0);
- set_ia32_emit_cl(new_op);
+ new_node = func(dbgi, irg, new_block, new_op1, new_op2);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
/* lowered shift instruction may have a dependency operand, handle it here */
if (get_irn_arity(node) == 3) {
/* we have a dependency */
ir_node *new_dep = be_transform_node(get_irn_n(node, 2));
- add_irn_dep(new_op, new_dep);
+ add_irn_dep(new_node, new_dep);
}
- return new_op;
+ return new_node;
}
* @param func The node constructor function
* @return The constructed ia32 node.
*/
-static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func)
+static ir_node *gen_unop(ir_node *node, ir_node *op, construct_unop_func *func,
+ match_flags_t flags)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op = be_transform_node(op);
- ir_node *new_node = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_op;
+ ir_node *new_node;
- new_node = func(dbgi, irg, block, noreg, noreg, new_op, nomem);
- DB((dbg, LEVEL_1, "INT unop ..."));
- set_ia32_am_support(new_node, ia32_am_Dest, ia32_am_unary);
+ assert(flags == 0 || flags == match_mode_neutral);
+ if(flags & match_mode_neutral) {
+ op = ia32_skip_downconv(op);
+ }
+
+ new_op = be_transform_node(op);
+ new_node = func(dbgi, irg, new_block, new_op);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
return new_node;
}
+static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
+ ia32_address_t *addr)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *base = addr->base;
+ ir_node *index = addr->index;
+ ir_node *res;
+
+ if(base == NULL) {
+ base = ia32_new_NoReg_gp(env_cg);
+ } else {
+ base = be_transform_node(base);
+ }
+
+ if(index == NULL) {
+ index = ia32_new_NoReg_gp(env_cg);
+ } else {
+ index = be_transform_node(index);
+ }
+
+ res = new_rd_ia32_Lea(dbgi, irg, block, base, index);
+ set_address(res, addr);
+
+ return res;
+}
+
+static int am_has_immediates(const ia32_address_t *addr)
+{
+ return addr->offset != 0 || addr->symconst_ent != NULL
+ || addr->frame_entity || addr->use_frame;
+}
+
/**
* Creates an ia32 Add.
*
* @return the created ia32 Add node
*/
static ir_node *gen_Add(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op1 = get_Add_left(node);
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *op2 = get_Add_right(node);
- ir_node *new_op2 = be_transform_node(op2);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *expr_op, *imm_op;
-
- /* Check if immediate optimization is on and */
- /* if it's an operation with immediate. */
- imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(new_op1, new_op2) : NULL;
- expr_op = get_expr_op(new_op1, new_op2);
-
- assert((expr_op || imm_op) && "invalid operands");
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *op1 = get_Add_left(node);
+ ir_node *op2 = get_Add_right(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *new_node;
+ ir_node *add_immediate_op;
+ ia32_address_t addr;
+ ia32_address_mode_t am;
if (mode_is_float(mode)) {
if (USE_SSE2(env_cg))
- return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xAdd);
+ return gen_binop(node, op1, op2, new_rd_ia32_xAdd,
+ match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd);
- }
-
- /* integer ADD */
- if (! expr_op) {
- ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
- ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
-
- /* No expr_op means, that we have two const - one symconst and */
- /* one tarval or another symconst - because this case is not */
- /* covered by constant folding */
- /* We need to check for: */
- /* 1) symconst + const -> becomes a LEA */
- /* 2) symconst + symconst -> becomes a const + LEA as the elf */
- /* linker doesn't support two symconsts */
-
- if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
- /* this is the 2nd case */
- new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_op_type(new_op, ia32_AddrModeS);
-
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- } else if (tp1 == ia32_ImmSymConst) {
- tarval *tv = get_ia32_Immop_tarval(new_op2);
- long offs = get_tarval_long(tv);
-
- new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
- add_irn_dep(new_op, get_irg_frame(irg));
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
-
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
- add_ia32_am_offs_int(new_op, offs);
- set_ia32_am_flavour(new_op, ia32_am_OB);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else if (tp2 == ia32_ImmSymConst) {
- tarval *tv = get_ia32_Immop_tarval(new_op1);
- long offs = get_tarval_long(tv);
-
- new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
- add_irn_dep(new_op, get_irg_frame(irg));
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
-
- add_ia32_am_offs_int(new_op, offs);
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
- set_ia32_am_flavour(new_op, ia32_am_OB);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else {
- tarval *tv1 = get_ia32_Immop_tarval(new_op1);
- tarval *tv2 = get_ia32_Immop_tarval(new_op2);
- tarval *restv = tarval_add(tv1, tv2);
+ return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfadd,
+ match_commutative | match_am);
+ }
- DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
+ ia32_mark_non_am(node);
- new_op = new_rd_ia32_Const(dbgi, irg, block);
- set_ia32_Const_tarval(new_op, restv);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- }
+ op2 = ia32_skip_downconv(op2);
+ op1 = ia32_skip_downconv(op1);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
- } else if (imm_op) {
- if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
- tarval_classification_t class_tv, class_negtv;
- tarval *tv = get_ia32_Immop_tarval(imm_op);
-
- /* optimize tarvals */
- class_tv = classify_tarval(tv);
- class_negtv = classify_tarval(tarval_neg(tv));
-
- if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
- DB((dbg, LEVEL_2, "Add(1) to Inc ... "));
- new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
- } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
- DB((dbg, LEVEL_2, "Add(-1) to Dec ... "));
- new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
- }
+ /**
+ * Rules for an Add:
+ * 0. Immediate Trees (example Add(Symconst, Const) -> Const)
+ * 1. Add with immediate -> Lea
+ * 2. Add with possible source address mode -> Add
+ * 3. Otherwise -> Lea
+ */
+ memset(&addr, 0, sizeof(addr));
+ ia32_create_address_mode(&addr, node, /*force=*/1);
+ add_immediate_op = NULL;
+ /* a constant? */
+ if(addr.base == NULL && addr.index == NULL) {
+ new_node = new_rd_ia32_Const(dbgi, irg, new_block, addr.symconst_ent,
+ addr.symconst_sign, addr.offset);
+ add_irn_dep(new_node, get_irg_frame(irg));
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ return new_node;
+ }
+ /* add with immediate? */
+ if(addr.index == NULL) {
+ add_immediate_op = addr.base;
+ } else if(addr.base == NULL && addr.scale == 0) {
+ add_immediate_op = addr.index;
+ }
+
+ if(add_immediate_op != NULL) {
+ if(!am_has_immediates(&addr)) {
+#ifdef DEBUG_libfirm
+ ir_fprintf(stderr, "Optimisation warning Add x,0 (%+F) found\n",
+ node);
+#endif
+ return be_transform_node(add_immediate_op);
}
+
+ new_node = create_lea_from_address(dbgi, new_block, &addr);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ return new_node;
}
- /* This is a normal add */
- new_op = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
+ /* test if we can use source address mode */
+ match_arguments(&am, block, op1, op2, match_commutative
+ | match_mode_neutral | match_am | match_immediate | match_try_am);
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
- set_ia32_commutative(new_op);
+ /* construct an Add with source address mode */
+ if (am.op_type == ia32_AddrModeS) {
+ ia32_address_t *am_addr = &am.addr;
+ new_node = new_rd_ia32_Add(dbgi, irg, new_block, am_addr->base,
+ am_addr->index, am_addr->mem, am.new_op1,
+ am.new_op2);
+ set_am_attributes(new_node, &am);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- fold_immediate(new_op, 2, 3);
+ new_node = fix_mem_proj(new_node, &am);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ return new_node;
+ }
- return new_op;
+ /* otherwise construct a lea */
+ new_node = create_lea_from_address(dbgi, new_block, &addr);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ return new_node;
}
/**
if (mode_is_float(mode)) {
if (USE_SSE2(env_cg))
- return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xMul);
+ return gen_binop(node, op1, op2, new_rd_ia32_xMul,
+ match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul);
+ return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfmul,
+ match_commutative | match_am);
}
/*
signed or unsigned multiplication so we use IMul as it has fewer
constraints
*/
- return gen_binop(node, op1, op2, new_rd_ia32_IMul, 1);
+ return gen_binop(node, op1, op2, new_rd_ia32_IMul,
+ match_commutative | match_am | match_mode_neutral |
+ match_immediate | match_am_and_immediates);
}
/**
*
* @return the created ia32 Mulh node
*/
-static ir_node *gen_Mulh(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op1 = get_irn_n(node, 0);
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *op2 = get_irn_n(node, 1);
- ir_node *new_op2 = be_transform_node(op2);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_mode *mode = get_irn_mode(node);
- ir_node *proj_EDX, *res;
+static ir_node *gen_Mulh(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *op1 = get_Mulh_left(node);
+ ir_node *op2 = get_Mulh_right(node);
+ ir_node *proj_EDX;
+ ir_node *new_node;
+ match_flags_t flags;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+
+ flags = match_commutative | match_am;
assert(!mode_is_float(mode) && "Mulh with float not supported");
+ assert(get_mode_size_bits(mode) == 32);
+
+ match_arguments(&am, block, op1, op2, flags);
+
if (mode_is_signed(mode)) {
- res = new_rd_ia32_IMul1OP(dbgi, irg, block, noreg, noreg, new_op1,
- new_op2, new_NoMem());
+ new_node = new_rd_ia32_IMul1OP(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2);
} else {
- res = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_op1, new_op2,
- new_NoMem());
+ new_node = new_rd_ia32_Mul(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2);
}
- set_ia32_commutative(res);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
+ set_am_attributes(new_node, &am);
+ /* we can't use source address mode anymore when using immediates */
+ if(is_ia32_Immediate(am.new_op1) || is_ia32_Immediate(am.new_op2))
+ set_ia32_am_support(new_node, ia32_am_None, ia32_am_arity_none);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ assert(get_irn_mode(new_node) == mode_T);
+
+ fix_mem_proj(new_node, &am);
- proj_EDX = new_rd_Proj(dbgi, irg, block, res, mode_Iu, pn_EDX);
+ assert(pn_ia32_IMul1OP_EDX == pn_ia32_Mul_EDX);
+ proj_EDX = new_rd_Proj(dbgi, irg, block, new_node,
+ mode_Iu, pn_ia32_IMul1OP_EDX);
return proj_EDX;
}
ir_node *op2 = get_And_right(node);
assert(! mode_is_float(get_irn_mode(node)));
- /* check for zero extension first */
+ /* is it a zero extension? */
if (is_Const(op2)) {
tarval *tv = get_Const_tarval(op2);
long v = get_tarval_long(tv);
if (v == 0xFF || v == 0xFFFF) {
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op = be_transform_node(op1);
+ ir_node *block = get_nodes_block(node);
ir_mode *src_mode;
ir_node *res;
assert(v == 0xFFFF);
src_mode = mode_Hu;
}
- res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, new_op);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ res = create_I2I_Conv(src_mode, mode_Iu, dbgi, block, op1, node);
return res;
}
}
- return gen_binop(node, op1, op2, new_rd_ia32_And, 1);
+ return gen_binop(node, op1, op2, new_rd_ia32_And,
+ match_commutative | match_mode_neutral | match_am
+ | match_immediate);
}
ir_node *op2 = get_Or_right(node);
assert (! mode_is_float(get_irn_mode(node)));
- return gen_binop(node, op1, op2, new_rd_ia32_Or, 1);
+ return gen_binop(node, op1, op2, new_rd_ia32_Or, match_commutative
+ | match_mode_neutral | match_am | match_immediate);
}
ir_node *op2 = get_Eor_right(node);
assert(! mode_is_float(get_irn_mode(node)));
- return gen_binop(node, op1, op2, new_rd_ia32_Xor, 1);
+ return gen_binop(node, op1, op2, new_rd_ia32_Xor, match_commutative
+ | match_mode_neutral | match_am | match_immediate);
}
* @return The created ia32 Sub node
*/
static ir_node *gen_Sub(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op1 = get_Sub_left(node);
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *op2 = get_Sub_right(node);
- ir_node *new_op2 = be_transform_node(op2);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *expr_op, *imm_op;
-
- /* Check if immediate optimization is on and */
- /* if it's an operation with immediate. */
- imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_op2) : NULL;
- expr_op = get_expr_op(new_op1, new_op2);
-
- assert((expr_op || imm_op) && "invalid operands");
+ ir_node *op1 = get_Sub_left(node);
+ ir_node *op2 = get_Sub_right(node);
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
if (USE_SSE2(env_cg))
- return gen_binop_sse_float(node, op1, op2, new_rd_ia32_xSub);
+ return gen_binop(node, op1, op2, new_rd_ia32_xSub, match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub);
- }
-
- /* integer SUB */
- if (! expr_op) {
- ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
- ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
-
- /* No expr_op means, that we have two const - one symconst and */
- /* one tarval or another symconst - because this case is not */
- /* covered by constant folding */
- /* We need to check for: */
- /* 1) symconst - const -> becomes a LEA */
- /* 2) symconst - symconst -> becomes a const - LEA as the elf */
- /* linker doesn't support two symconsts */
- if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
- /* this is the 2nd case */
- new_op = new_rd_ia32_Lea(dbgi, irg, block, new_op1, noreg);
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
- set_ia32_am_sc_sign(new_op);
- set_ia32_am_flavour(new_op, ia32_am_B);
-
- DBG_OPT_LEA3(op1, op2, node, new_op);
- } else if (tp1 == ia32_ImmSymConst) {
- tarval *tv = get_ia32_Immop_tarval(new_op2);
- long offs = get_tarval_long(tv);
-
- new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
- add_irn_dep(new_op, get_irg_frame(irg));
- DBG_OPT_LEA3(op1, op2, node, new_op);
-
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
- add_ia32_am_offs_int(new_op, -offs);
- set_ia32_am_flavour(new_op, ia32_am_OB);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else if (tp2 == ia32_ImmSymConst) {
- tarval *tv = get_ia32_Immop_tarval(new_op1);
- long offs = get_tarval_long(tv);
-
- new_op = new_rd_ia32_Lea(dbgi, irg, block, noreg, noreg);
- add_irn_dep(new_op, get_irg_frame(irg));
- DBG_OPT_LEA3(op1, op2, node, new_op);
-
- add_ia32_am_offs_int(new_op, offs);
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
- set_ia32_am_sc_sign(new_op);
- set_ia32_am_flavour(new_op, ia32_am_OB);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else {
- tarval *tv1 = get_ia32_Immop_tarval(new_op1);
- tarval *tv2 = get_ia32_Immop_tarval(new_op2);
- tarval *restv = tarval_sub(tv1, tv2);
-
- DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
-
- new_op = new_rd_ia32_Const(dbgi, irg, block);
- set_ia32_Const_tarval(new_op, restv);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- }
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
- } else if (imm_op) {
- if ((env_cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
- tarval_classification_t class_tv, class_negtv;
- tarval *tv = get_ia32_Immop_tarval(imm_op);
-
- /* optimize tarvals */
- class_tv = classify_tarval(tv);
- class_negtv = classify_tarval(tarval_neg(tv));
-
- if (class_tv == TV_CLASSIFY_ONE) {
- DB((dbg, LEVEL_2, "Sub(1) to Dec ... "));
- new_op = new_rd_ia32_Dec(dbgi, irg, block, noreg, noreg, expr_op, nomem);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
- } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
- DB((dbg, LEVEL_2, "Sub(-1) to Inc ... "));
- new_op = new_rd_ia32_Inc(dbgi, irg, block, noreg, noreg, expr_op, nomem);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
- }
- }
+ return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfsub,
+ match_am);
}
- /* This is a normal sub */
- new_op = new_rd_ia32_Sub(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
-
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Full, ia32_am_binary);
-
- fold_immediate(new_op, 2, 3);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ if(is_Const(op2)) {
+ ir_fprintf(stderr, "Optimisation warning: found sub with const (%+F)\n",
+ node);
+ }
- return new_op;
+ return gen_binop(node, op1, op2, new_rd_ia32_Sub, match_mode_neutral
+ | match_am | match_immediate);
}
-
-
/**
* Generates an ia32 DivMod with additional infrastructure for the
* register allocator if needed.
- *
- * @param dividend -no comment- :)
- * @param divisor -no comment- :)
- * @param dm_flav flavour_Div/Mod/DivMod
- * @return The created ia32 DivMod node
*/
-static ir_node *generate_DivMod(ir_node *node, ir_node *dividend,
- ir_node *divisor, ia32_op_flavour_t dm_flav)
+static ir_node *create_Div(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_dividend = be_transform_node(dividend);
- ir_node *new_divisor = be_transform_node(divisor);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *res, *proj_div, *proj_mod;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *mem;
+ ir_node *new_mem;
+ ir_node *op1;
+ ir_node *op2;
+ ir_node *new_node;
+ ir_mode *mode;
ir_node *sign_extension;
- ir_node *mem, *new_mem;
- ir_node *projs[pn_DivMod_max];
int has_exc;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+
+ /* the upper bits have random contents for smaller modes */
+ has_exc = 0;
+ switch (get_irn_opcode(node)) {
+ case iro_Div:
+ op1 = get_Div_left(node);
+ op2 = get_Div_right(node);
+ mem = get_Div_mem(node);
+ mode = get_Div_resmode(node);
+ has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
+ break;
+ case iro_Mod:
+ op1 = get_Mod_left(node);
+ op2 = get_Mod_right(node);
+ mem = get_Mod_mem(node);
+ mode = get_Mod_resmode(node);
+ has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
+ break;
+ case iro_DivMod:
+ op1 = get_DivMod_left(node);
+ op2 = get_DivMod_right(node);
+ mem = get_DivMod_mem(node);
+ mode = get_DivMod_resmode(node);
+ has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
+ break;
+ default:
+ panic("invalid divmod node %+F", node);
+ }
- ia32_collect_Projs(node, projs, pn_DivMod_max);
+ match_arguments(&am, block, op1, op2, match_am);
- proj_div = proj_mod = NULL;
- has_exc = 0;
- switch (dm_flav) {
- case flavour_Div:
- mem = get_Div_mem(node);
- mode = get_Div_resmode(node);
- proj_div = be_get_Proj_for_pn(node, pn_Div_res);
- has_exc = be_get_Proj_for_pn(node, pn_Div_X_except) != NULL;
- break;
- case flavour_Mod:
- mem = get_Mod_mem(node);
- mode = get_Mod_resmode(node);
- proj_mod = be_get_Proj_for_pn(node, pn_Mod_res);
- has_exc = be_get_Proj_for_pn(node, pn_Mod_X_except) != NULL;
- break;
- case flavour_DivMod:
- mem = get_DivMod_mem(node);
- mode = get_DivMod_resmode(node);
- proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
- proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
- has_exc = be_get_Proj_for_pn(node, pn_DivMod_X_except) != NULL;
- break;
- default:
- panic("invalid divmod flavour!");
+ if(!is_NoMem(mem)) {
+ new_mem = be_transform_node(mem);
+ if(!is_NoMem(addr->mem)) {
+ ir_node *in[2];
+ in[0] = new_mem;
+ in[1] = addr->mem;
+ new_mem = new_rd_Sync(dbgi, irg, new_block, 2, in);
+ }
+ } else {
+ new_mem = addr->mem;
}
- new_mem = be_transform_node(mem);
if (mode_is_signed(mode)) {
- /* in signed mode, we need to sign extend the dividend */
- ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
+ ir_node *produceval = new_rd_ia32_ProduceVal(dbgi, irg, new_block);
add_irn_dep(produceval, get_irg_frame(irg));
- sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_dividend,
- produceval);
- } else {
- sign_extension = new_rd_ia32_Const(dbgi, irg, block);
- set_ia32_Immop_tarval(sign_extension, get_tarval_null(mode_Iu));
+ sign_extension = new_rd_ia32_Cltd(dbgi, irg, new_block, am.new_op1,
+ produceval);
+ new_node = new_rd_ia32_IDiv(dbgi, irg, new_block, addr->base,
+ addr->index, new_mem, am.new_op1,
+ sign_extension, am.new_op2);
+ } else {
+ sign_extension = new_rd_ia32_Const(dbgi, irg, new_block, NULL, 0, 0);
add_irn_dep(sign_extension, get_irg_frame(irg));
- }
- if (mode_is_signed(mode)) {
- res = new_rd_ia32_IDiv(dbgi, irg, block, noreg, noreg, new_dividend,
- sign_extension, new_divisor, new_mem, dm_flav);
- } else {
- res = new_rd_ia32_Div(dbgi, irg, block, noreg, noreg, new_dividend,
- sign_extension, new_divisor, new_mem, dm_flav);
+ new_node = new_rd_ia32_Div(dbgi, irg, new_block, addr->base,
+ addr->index, new_mem, am.new_op1,
+ sign_extension, am.new_op2);
}
- set_ia32_exc_label(res, has_exc);
- set_irn_pinned(res, get_irn_pinned(node));
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
+ set_ia32_exc_label(new_node, has_exc);
+ set_irn_pinned(new_node, get_irn_pinned(node));
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ set_am_attributes(new_node, &am);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return res;
+ new_node = fix_mem_proj(new_node, &am);
+
+ return new_node;
}
-/**
- * Wrapper for generate_DivMod. Sets flavour_Mod.
- *
- */
static ir_node *gen_Mod(ir_node *node) {
- return generate_DivMod(node, get_Mod_left(node),
- get_Mod_right(node), flavour_Mod);
+ return create_Div(node);
}
-/**
- * Wrapper for generate_DivMod. Sets flavour_Div.
- *
- */
static ir_node *gen_Div(ir_node *node) {
- return generate_DivMod(node, get_Div_left(node),
- get_Div_right(node), flavour_Div);
+ return create_Div(node);
}
-/**
- * Wrapper for generate_DivMod. Sets flavour_DivMod.
- */
static ir_node *gen_DivMod(ir_node *node) {
- return generate_DivMod(node, get_DivMod_left(node),
- get_DivMod_right(node), flavour_DivMod);
+ return create_Div(node);
}
*
* @return The created ia32 xDiv node
*/
-static ir_node *gen_Quot(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
+static ir_node *gen_Quot(ir_node *node)
+{
ir_node *op1 = get_Quot_left(node);
- ir_node *new_op1 = be_transform_node(op1);
ir_node *op2 = get_Quot_right(node);
- ir_node *new_op2 = be_transform_node(op2);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(current_ir_graph);
- ir_node *new_op;
if (USE_SSE2(env_cg)) {
- ir_mode *mode = get_irn_mode(op1);
- if (is_ia32_xConst(new_op2)) {
- new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, noreg, nomem);
- set_ia32_am_support(new_op, ia32_am_None, ia32_am_arity_none);
- copy_ia32_Immop_attr(new_op, new_op2);
- } else {
- new_op = new_rd_ia32_xDiv(dbgi, irg, block, noreg, noreg, new_op1, new_op2, nomem);
- // Matze: disabled for now, spillslot coalescer fails
- set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
- }
- set_ia32_ls_mode(new_op, mode);
+ return gen_binop(node, op1, op2, new_rd_ia32_xDiv, match_am);
} else {
- new_op = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_op1,
- new_op2, nomem, get_fpcw());
- // Matze: disabled for now (spillslot coalescer fails)
- set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
+ return gen_binop_x87_float(node, op1, op2, new_rd_ia32_vfdiv, match_am);
}
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
- return new_op;
}
* @return The created ia32 Shl node
*/
static ir_node *gen_Shl(ir_node *node) {
- return gen_shift_binop(node, get_Shl_left(node), get_Shl_right(node),
- new_rd_ia32_Shl);
-}
-
+ ir_node *left = get_Shl_left(node);
+ ir_node *right = get_Shl_right(node);
+ return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
+ match_mode_neutral | match_immediate);
+}
/**
* Creates an ia32 Shr.
* @return The created ia32 Shr node
*/
static ir_node *gen_Shr(ir_node *node) {
- return gen_shift_binop(node, get_Shr_left(node),
- get_Shr_right(node), new_rd_ia32_Shr);
+ ir_node *left = get_Shr_left(node);
+ ir_node *right = get_Shr_right(node);
+
+ return gen_shift_binop(node, left, right, new_rd_ia32_Shr, match_immediate);
}
ir_node *left = get_Shrs_left(node);
ir_node *right = get_Shrs_right(node);
ir_mode *mode = get_irn_mode(node);
+
if(is_Const(right) && mode == mode_Is) {
tarval *tv = get_Const_tarval(right);
long val = get_tarval_long(tv);
return new_rd_ia32_Cltd(dbgi, irg, block, new_op, pval);
}
}
-#if 1
+
/* 8 or 16 bit sign extension? */
if(is_Const(right) && is_Shl(left) && mode == mode_Is) {
ir_node *shl_left = get_Shl_left(left);
long val = get_tarval_long(tv1);
if(val == 16 || val == 24) {
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op = be_transform_node(shl_left);
+ ir_node *block = get_nodes_block(node);
ir_mode *src_mode;
ir_node *res;
src_mode = mode_Hs;
}
res = create_I2I_Conv(src_mode, mode_Is, dbgi, block,
- new_op);
- SET_IA32_ORIG_NODE(res,
- ia32_get_old_node_name(env_cg, node));
+ shl_left, node);
return res;
}
}
}
}
-#endif
- return gen_shift_binop(node, left, right, new_rd_ia32_Sar);
+ return gen_shift_binop(node, left, right, new_rd_ia32_Sar, match_immediate);
}
* @param op2 The second operator
* @return The created ia32 RotL node
*/
-static ir_node *gen_RotL(ir_node *node,
- ir_node *op1, ir_node *op2) {
- return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol);
+static ir_node *gen_RotL(ir_node *node, ir_node *op1, ir_node *op2) {
+ return gen_shift_binop(node, op1, op2, new_rd_ia32_Rol, match_immediate);
}
* @param op2 The second operator
* @return The created ia32 RotR node
*/
-static ir_node *gen_RotR(ir_node *node, ir_node *op1,
- ir_node *op2) {
- return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror);
+static ir_node *gen_RotR(ir_node *node, ir_node *op1, ir_node *op2) {
+ return gen_shift_binop(node, op1, op2, new_rd_ia32_Ror, match_immediate);
}
if (get_irn_op(left) == op_Minus &&
tarval_is_long(tv) &&
- get_tarval_long(tv) == bits)
+ get_tarval_long(tv) == bits &&
+ bits == 32)
{
DB((dbg, LEVEL_1, "RotL into RotR ... "));
rotate = gen_RotR(node, op1, get_Minus_op(left));
/**
* Transforms a Minus node.
*
- * @param op The Minus operand
* @return The created ia32 Minus node
*/
-ir_node *gen_Minus_ex(ir_node *node, ir_node *op) {
+static ir_node *gen_Minus(ir_node *node)
+{
+ ir_node *op = get_Minus_op(node);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_irn_mode(node);
ir_entity *ent;
- ir_node *res;
- int size;
+ ir_node *new_node;
+ int size;
if (mode_is_float(mode)) {
ir_node *new_op = be_transform_node(op);
if (USE_SSE2(env_cg)) {
- ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
- ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
+ /* TODO: non-optimal... if we have many xXors, then we should
+ * rather create a load for the const and use that instead of
+ * several AM nodes... */
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
+ ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
+ ir_node *nomem = new_rd_NoMem(irg);
- res = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
+ new_node = new_rd_ia32_xXor(dbgi, irg, block, noreg_gp, noreg_gp,
+ nomem, new_op, noreg_xmm);
size = get_mode_size_bits(mode);
ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
- set_ia32_am_sc(res, ent);
- set_ia32_op_type(res, ia32_AddrModeS);
- set_ia32_ls_mode(res, mode);
+ set_ia32_am_sc(new_node, ent);
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode);
} else {
- res = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
+ new_node = new_rd_ia32_vfchs(dbgi, irg, block, new_op);
}
} else {
- res = gen_unop(node, op, new_rd_ia32_Neg);
+ new_node = gen_unop(node, op, new_rd_ia32_Neg, match_mode_neutral);
}
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
-
- return res;
-}
-
-/**
- * Transforms a Minus node.
- *
- * @return The created ia32 Minus node
- */
-static ir_node *gen_Minus(ir_node *node) {
- return gen_Minus_ex(node, get_Minus_op(node));
-}
-
-static ir_node *create_Immediate_from_int(int val)
-{
- ir_graph *irg = current_ir_graph;
- ir_node *start_block = get_irg_start_block(irg);
- ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL, 0, val);
- arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
-
- return immediate;
-}
-
-static ir_node *gen_bin_Not(ir_node *node)
-{
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = get_Not_op(node);
- ir_node *new_op = be_transform_node(op);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *one = create_Immediate_from_int(1);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_op, one, nomem);
+ return new_node;
}
/**
*/
static ir_node *gen_Not(ir_node *node) {
ir_node *op = get_Not_op(node);
- ir_mode *mode = get_irn_mode(node);
-
- if(mode == mode_b) {
- return gen_bin_Not(node);
- }
+ assert(get_irn_mode(node) != mode_b); /* should be lowered already */
assert (! mode_is_float(get_irn_mode(node)));
- return gen_unop(node, op, new_rd_ia32_Not);
+
+ return gen_unop(node, op, new_rd_ia32_Not, match_mode_neutral);
}
*
* @return The created ia32 Abs node
*/
-static ir_node *gen_Abs(ir_node *node) {
+static ir_node *gen_Abs(ir_node *node)
+{
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *op = get_Abs_op(node);
ir_node *new_op = be_transform_node(op);
ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
ir_node *noreg_fp = ia32_new_NoReg_fp(env_cg);
ir_node *nomem = new_NoMem();
- ir_node *res;
- int size;
+ ir_node *new_node;
+ int size;
ir_entity *ent;
if (mode_is_float(mode)) {
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
+ new_node = new_rd_ia32_xAnd(dbgi,irg, block, noreg_gp, noreg_gp,
+ nomem, new_op, noreg_fp);
size = get_mode_size_bits(mode);
ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_am_sc(res, ent);
+ set_ia32_am_sc(new_node, ent);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- set_ia32_op_type(res, ia32_AddrModeS);
- set_ia32_ls_mode(res, mode);
- }
- else {
- res = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode);
+ } else {
+ new_node = new_rd_ia32_vfabs(dbgi, irg, block, new_op);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
}
} else {
ir_node *xor;
ir_node *sign_extension = new_rd_ia32_Cltd(dbgi, irg, block, new_op,
pval);
+ assert(get_mode_size_bits(mode) == 32);
+
add_irn_dep(pval, get_irg_frame(irg));
- SET_IA32_ORIG_NODE(sign_extension,
- ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(sign_extension,ia32_get_old_node_name(env_cg, node));
- xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, new_op,
- sign_extension, nomem);
+ xor = new_rd_ia32_Xor(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
+ new_op, sign_extension);
SET_IA32_ORIG_NODE(xor, ia32_get_old_node_name(env_cg, node));
- res = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, xor,
- sign_extension, nomem);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ new_node = new_rd_ia32_Sub(dbgi, irg, block, noreg_gp, noreg_gp, nomem,
+ xor, sign_extension);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
}
- return res;
+ return new_node;
}
+static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *flags;
+ ir_node *new_op;
+ ir_node *noreg;
+ ir_node *nomem;
+ ir_node *new_block;
+ dbg_info *dbgi;
+
+ /* we have a Cmp as input */
+ if(is_Proj(node)) {
+ ir_node *pred = get_Proj_pred(node);
+ if(is_Cmp(pred)) {
+ flags = be_transform_node(pred);
+ *pnc_out = get_Proj_proj(node);
+ return flags;
+ }
+ }
+ /* a mode_b value, we have to compare it against 0 */
+ dbgi = get_irn_dbg_info(node);
+ new_block = be_transform_node(get_nodes_block(node));
+ new_op = be_transform_node(node);
+ noreg = ia32_new_NoReg_gp(env_cg);
+ nomem = new_NoMem();
+ flags = new_rd_ia32_Test(dbgi, irg, new_block, noreg, noreg, nomem,
+ new_op, new_op, 0, 0);
+ *pnc_out = pn_Cmp_Lg;
+ return flags;
+}
/**
* Transforms a Load.
* @return the created ia32 Load node
*/
static ir_node *gen_Load(ir_node *node) {
- ir_node *old_block = get_nodes_block(node);
+ ir_node *old_block = get_nodes_block(node);
ir_node *block = be_transform_node(old_block);
ir_node *ptr = get_Load_ptr(node);
- ir_node *new_ptr = be_transform_node(ptr);
ir_node *mem = get_Load_mem(node);
ir_node *new_mem = be_transform_node(mem);
+ ir_node *base;
+ ir_node *index;
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
ir_mode *mode = get_Load_mode(node);
ir_mode *res_mode;
- ir_node *lptr = new_ptr;
- int is_imm = 0;
- ir_node *new_op;
- ia32_am_flavour_t am_flav = ia32_am_B;
+ ir_node *new_node;
+ ia32_address_t addr;
+
+ /* construct load address */
+ memset(&addr, 0, sizeof(addr));
+ ia32_create_address_mode(&addr, ptr, /*force=*/0);
+ base = addr.base;
+ index = addr.index;
+
+ if(base == NULL) {
+ base = noreg;
+ } else {
+ base = be_transform_node(base);
+ }
- /* address might be a constant (symconst or absolute address) */
- if (is_ia32_Const(new_ptr)) {
- lptr = noreg;
- is_imm = 1;
+ if(index == NULL) {
+ index = noreg;
+ } else {
+ index = be_transform_node(index);
}
if (mode_is_float(mode)) {
if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xLoad(dbgi, irg, block, lptr, noreg, new_mem);
+ new_node = new_rd_ia32_xLoad(dbgi, irg, block, base, index, new_mem,
+ mode);
res_mode = mode_xmm;
} else {
- new_op = new_rd_ia32_vfld(dbgi, irg, block, lptr, noreg, new_mem, mode);
+ new_node = new_rd_ia32_vfld(dbgi, irg, block, base, index, new_mem,
+ mode);
res_mode = mode_vfp;
}
} else {
- if(mode == mode_b)
- mode = mode_Iu;
+ assert(mode != mode_b);
/* create a conv node with address mode for smaller modes */
if(get_mode_size_bits(mode) < 32) {
- new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, lptr, noreg, noreg,
- new_mem, mode);
+ new_node = new_rd_ia32_Conv_I2I(dbgi, irg, block, base, index,
+ new_mem, noreg, mode);
} else {
- new_op = new_rd_ia32_Load(dbgi, irg, block, lptr, noreg, new_mem);
+ new_node = new_rd_ia32_Load(dbgi, irg, block, base, index, new_mem);
}
res_mode = mode_Iu;
}
- /* base is a constant address */
- if (is_imm) {
- if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
- am_flav = ia32_am_N;
- } else {
- tarval *tv = get_ia32_Immop_tarval(new_ptr);
- long offs = get_tarval_long(tv);
-
- add_ia32_am_offs_int(new_op, offs);
- am_flav = ia32_am_O;
- }
- }
-
- set_irn_pinned(new_op, get_irn_pinned(node));
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, am_flav);
- set_ia32_ls_mode(new_op, mode);
+ set_irn_pinned(new_node, get_irn_pinned(node));
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode);
+ set_address(new_node, &addr);
/* make sure we are scheduled behind the initial IncSP/Barrier
* to avoid spills being placed before it
*/
if (block == get_irg_start_block(irg)) {
- add_irn_dep(new_op, get_irg_frame(irg));
+ add_irn_dep(new_node, get_irg_frame(irg));
}
- set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ set_ia32_exc_label(new_node,
+ be_get_Proj_for_pn(node, pn_Load_X_except) != NULL);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return new_op;
+ return new_node;
}
+static int use_dest_am(ir_node *block, ir_node *node, ir_node *mem,
+ ir_node *ptr, ir_node *other)
+{
+ ir_node *load;
+
+ if(!is_Proj(node))
+ return 0;
+ /* we only use address mode if we're the only user of the load */
+ if(get_irn_n_edges(node) > 1)
+ return 0;
-/**
- * Transforms a Store.
- *
- * @return the created ia32 Store node
- */
-static ir_node *gen_Store(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *ptr = get_Store_ptr(node);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *val = get_Store_value(node);
- ir_node *new_val;
- ir_node *mem = get_Store_mem(node);
- ir_node *new_mem = be_transform_node(mem);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *sptr = new_ptr;
- ir_mode *mode = get_irn_mode(val);
- int is_imm = 0;
+ load = get_Proj_pred(node);
+ if(!is_Load(load))
+ return 0;
+ if(get_nodes_block(load) != block)
+ return 0;
+
+ /* Store should be attached to the load */
+ if(!is_Proj(mem) || get_Proj_pred(mem) != load)
+ return 0;
+ /* store should have the same pointer as the load */
+ if(get_Load_ptr(load) != ptr)
+ return 0;
+
+ /* don't do AM if other node inputs depend on the load (via mem-proj) */
+ if(other != NULL && get_nodes_block(other) == block
+ && heights_reachable_in_block(heights, other, load))
+ return 0;
+
+ return 1;
+}
+
+static ir_node *dest_am_binop(ir_node *node, ir_node *op1, ir_node *op2,
+ ir_node *mem, ir_node *ptr, ir_mode *mode,
+ construct_binop_dest_func *func,
+ construct_binop_dest_func *func8bit,
+ match_flags_t flags)
+{
+ ir_node *src_block = get_nodes_block(node);
+ ir_node *block;
+ ir_node *noreg_gp = ia32_new_NoReg_gp(env_cg);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi;
+ ir_node *new_node;
ir_node *new_op;
- ia32_am_flavour_t am_flav = ia32_am_B;
+ int commutative;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+ memset(&am, 0, sizeof(am));
+
+ assert(flags & match_dest_am);
+ assert(flags & match_immediate); /* there is no destam node without... */
+ commutative = (flags & match_commutative) != 0;
+
+ if(use_dest_am(src_block, op1, mem, ptr, op2)) {
+ build_address(&am, op1);
+ new_op = create_immediate_or_transform(op2, 0);
+ } else if(commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
+ build_address(&am, op2);
+ new_op = create_immediate_or_transform(op1, 0);
+ } else {
+ return NULL;
+ }
+
+ if(addr->base == NULL)
+ addr->base = noreg_gp;
+ if(addr->index == NULL)
+ addr->index = noreg_gp;
+ if(addr->mem == NULL)
+ addr->mem = new_NoMem();
- /* address might be a constant (symconst or absolute address) */
- if (is_ia32_Const(new_ptr)) {
- sptr = noreg;
- is_imm = 1;
+ dbgi = get_irn_dbg_info(node);
+ block = be_transform_node(src_block);
+ if(get_mode_size_bits(mode) == 8) {
+ new_node = func8bit(dbgi, irg, block, addr->base, addr->index,
+ addr->mem, new_op);
+ } else {
+ new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem,
+ new_op);
}
+ set_address(new_node, addr);
+ set_ia32_op_type(new_node, ia32_AddrModeD);
+ set_ia32_ls_mode(new_node, mode);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- if (mode_is_float(mode)) {
- new_val = be_transform_node(val);
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xStore(dbgi, irg, block, sptr, noreg, new_val,
- new_mem);
- } else {
- new_op = new_rd_ia32_vfst(dbgi, irg, block, sptr, noreg, new_val,
- new_mem, mode);
- }
+ return new_node;
+}
+
+static ir_node *dest_am_unop(ir_node *node, ir_node *op, ir_node *mem,
+ ir_node *ptr, ir_mode *mode,
+ construct_unop_dest_func *func)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *src_block = get_nodes_block(node);
+ ir_node *block;
+ dbg_info *dbgi;
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+ memset(&am, 0, sizeof(am));
+
+ if(!use_dest_am(src_block, op, mem, ptr, NULL))
+ return NULL;
+
+ build_address(&am, op);
+
+ dbgi = get_irn_dbg_info(node);
+ block = be_transform_node(src_block);
+ new_node = func(dbgi, irg, block, addr->base, addr->index, addr->mem);
+ set_address(new_node, addr);
+ set_ia32_op_type(new_node, ia32_AddrModeD);
+ set_ia32_ls_mode(new_node, mode);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ return new_node;
+}
+
+static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem) {
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *psi_true = get_Psi_val(node, 0);
+ ir_node *psi_default = get_Psi_default(node);
+ ir_graph *irg;
+ ir_node *cond;
+ ir_node *new_mem;
+ dbg_info *dbgi;
+ ir_node *block;
+ ir_node *new_block;
+ ir_node *flags;
+ ir_node *new_node;
+ int negated;
+ pn_Cmp pnc;
+ ia32_address_t addr;
+
+ if(get_mode_size_bits(mode) != 8)
+ return NULL;
+
+ if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
+ negated = 0;
+ } else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
+ negated = 1;
} else {
- new_val = create_immediate_or_transform(val, 0);
- if(mode == mode_b)
- mode = mode_Iu;
+ return NULL;
+ }
- if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, sptr, noreg,
- new_val, new_mem);
- } else {
- new_op = new_rd_ia32_Store(dbgi, irg, block, sptr, noreg, new_val,
- new_mem);
+ build_address_ptr(&addr, ptr, mem);
+
+ irg = current_ir_graph;
+ dbgi = get_irn_dbg_info(node);
+ block = get_nodes_block(node);
+ new_block = be_transform_node(block);
+ cond = get_Psi_cond(node, 0);
+ flags = get_flags_node(cond, &pnc);
+ new_mem = be_transform_node(mem);
+ new_node = new_rd_ia32_SetMem(dbgi, irg, new_block, addr.base,
+ addr.index, addr.mem, flags, pnc, negated);
+ set_address(new_node, &addr);
+ set_ia32_op_type(new_node, ia32_AddrModeD);
+ set_ia32_ls_mode(new_node, mode);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ return new_node;
+}
+
+static ir_node *try_create_dest_am(ir_node *node) {
+ ir_node *val = get_Store_value(node);
+ ir_node *mem = get_Store_mem(node);
+ ir_node *ptr = get_Store_ptr(node);
+ ir_mode *mode = get_irn_mode(val);
+ int bits = get_mode_size_bits(mode);
+ ir_node *op1;
+ ir_node *op2;
+ ir_node *new_node;
+
+ /* handle only GP modes for now... */
+ if(!mode_needs_gp_reg(mode))
+ return NULL;
+
+ while(1) {
+ /* store must be the only user of the val node */
+ if(get_irn_n_edges(val) > 1)
+ return NULL;
+ /* skip pointless convs */
+ if(is_Conv(val)) {
+ ir_node *conv_op = get_Conv_op(val);
+ ir_mode *pred_mode = get_irn_mode(conv_op);
+ if(pred_mode == mode_b || bits <= get_mode_size_bits(pred_mode)) {
+ val = conv_op;
+ continue;
+ }
}
+ break;
}
- /* base is an constant address */
- if (is_imm) {
- if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
- set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
- am_flav = ia32_am_N;
- } else {
- tarval *tv = get_ia32_Immop_tarval(new_ptr);
- long offs = get_tarval_long(tv);
+ /* value must be in the same block */
+ if(get_nodes_block(node) != get_nodes_block(val))
+ return NULL;
- add_ia32_am_offs_int(new_op, offs);
- am_flav = ia32_am_O;
+ switch(get_irn_opcode(val)) {
+ case iro_Add:
+ op1 = get_Add_left(val);
+ op2 = get_Add_right(val);
+ if(is_Const_1(op2)) {
+ new_node = dest_am_unop(val, op1, mem, ptr, mode,
+ new_rd_ia32_IncMem);
+ break;
+ } else if(is_Const_Minus_1(op2)) {
+ new_node = dest_am_unop(val, op1, mem, ptr, mode,
+ new_rd_ia32_DecMem);
+ break;
+ }
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_AddMem, new_rd_ia32_AddMem8Bit,
+ match_dest_am | match_commutative |
+ match_immediate);
+ break;
+ case iro_Sub:
+ op1 = get_Sub_left(val);
+ op2 = get_Sub_right(val);
+ if(is_Const(op2)) {
+ ir_fprintf(stderr, "Optimisation warning: not-normalize sub ,C"
+ "found\n");
}
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_SubMem, new_rd_ia32_SubMem8Bit,
+ match_dest_am | match_immediate |
+ match_immediate);
+ break;
+ case iro_And:
+ op1 = get_And_left(val);
+ op2 = get_And_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_AndMem, new_rd_ia32_AndMem8Bit,
+ match_dest_am | match_commutative |
+ match_immediate);
+ break;
+ case iro_Or:
+ op1 = get_Or_left(val);
+ op2 = get_Or_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_OrMem, new_rd_ia32_OrMem8Bit,
+ match_dest_am | match_commutative |
+ match_immediate);
+ break;
+ case iro_Eor:
+ op1 = get_Eor_left(val);
+ op2 = get_Eor_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_XorMem, new_rd_ia32_XorMem8Bit,
+ match_dest_am | match_commutative |
+ match_immediate);
+ break;
+ case iro_Shl:
+ op1 = get_Shl_left(val);
+ op2 = get_Shl_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_ShlMem, new_rd_ia32_ShlMem,
+ match_dest_am | match_immediate);
+ break;
+ case iro_Shr:
+ op1 = get_Shr_left(val);
+ op2 = get_Shr_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_ShrMem, new_rd_ia32_ShrMem,
+ match_dest_am | match_immediate);
+ break;
+ case iro_Shrs:
+ op1 = get_Shrs_left(val);
+ op2 = get_Shrs_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_SarMem, new_rd_ia32_SarMem,
+ match_dest_am | match_immediate);
+ break;
+ case iro_Rot:
+ op1 = get_Rot_left(val);
+ op2 = get_Rot_right(val);
+ new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
+ new_rd_ia32_RolMem, new_rd_ia32_RolMem,
+ match_dest_am | match_immediate);
+ break;
+ /* TODO: match ROR patterns... */
+ case iro_Psi:
+ new_node = try_create_SetMem(val, ptr, mem);
+ break;
+ case iro_Minus:
+ op1 = get_Minus_op(val);
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NegMem);
+ break;
+ case iro_Not:
+ /* should be lowered already */
+ assert(mode != mode_b);
+ op1 = get_Not_op(val);
+ new_node = dest_am_unop(val, op1, mem, ptr, mode, new_rd_ia32_NotMem);
+ break;
+ default:
+ return NULL;
}
- set_irn_pinned(new_op, get_irn_pinned(node));
- set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, am_flav);
- set_ia32_ls_mode(new_op, mode);
-
- set_ia32_exc_label(new_op, be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ if(new_node != NULL) {
+ if(get_irn_pinned(new_node) != op_pin_state_pinned &&
+ get_irn_pinned(node) == op_pin_state_pinned) {
+ set_irn_pinned(new_node, op_pin_state_pinned);
+ }
+ }
- return new_op;
+ return new_node;
}
-static ir_node *maybe_scale_up(ir_node *new_op, ir_mode *mode, dbg_info *dbgi)
+static int is_float_to_int32_conv(const ir_node *node)
{
- ir_mode *tgt_mode;
- ir_node *block;
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *conv_op;
+ ir_mode *conv_mode;
- if(get_mode_size_bits(mode) == 32)
- return new_op;
- if(mode == mode_b)
- return new_op;
- if(is_ia32_Immediate(new_op))
- return new_op;
+ if(get_mode_size_bits(mode) != 32 || !mode_needs_gp_reg(mode))
+ return 0;
- if(mode_is_signed(mode))
- tgt_mode = mode_Is;
- else
- tgt_mode = mode_Iu;
+ if(!is_Conv(node))
+ return 0;
+ conv_op = get_Conv_op(node);
+ conv_mode = get_irn_mode(conv_op);
+
+ if(!mode_is_float(conv_mode))
+ return 0;
- block = get_nodes_block(new_op);
- return create_I2I_Conv(mode, tgt_mode, dbgi, block, new_op);
+ return 1;
}
-static ir_node *try_create_TestJmp(ir_node *block, dbg_info *dbgi, long pnc,
- ir_node *cmp_left, ir_node *cmp_right)
+/**
+ * Transforms a Store.
+ *
+ * @return the created ia32 Store node
+ */
+static ir_node *gen_Store(ir_node *node)
{
- ir_node *new_cmp_left;
- ir_node *new_cmp_right;
- ir_node *and_left;
- ir_node *and_right;
- ir_node *res;
- ir_node *noreg;
- ir_node *nomem;
- ir_mode *mode;
- long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *ptr = get_Store_ptr(node);
+ ir_node *val = get_Store_value(node);
+ ir_node *mem = get_Store_mem(node);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_mode *mode = get_irn_mode(val);
+ ir_node *new_val;
+ ir_node *new_node;
+ ia32_address_t addr;
- if(cmp_right != NULL && !is_Const_0(cmp_right))
- return NULL;
+ /* check for destination address mode */
+ new_node = try_create_dest_am(node);
+ if(new_node != NULL)
+ return new_node;
- if(is_And(cmp_left) && (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
- and_left = get_And_left(cmp_left);
- and_right = get_And_right(cmp_left);
+ /* construct store address */
+ memset(&addr, 0, sizeof(addr));
+ ia32_create_address_mode(&addr, ptr, /*force=*/0);
- mode = get_irn_mode(and_left);
- new_cmp_left = be_transform_node(and_left);
- new_cmp_right = create_immediate_or_transform(and_right, 0);
+ if(addr.base == NULL) {
+ addr.base = noreg;
} else {
- mode = get_irn_mode(cmp_left);
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = be_transform_node(cmp_left);
+ addr.base = be_transform_node(addr.base);
}
- assert(get_mode_size_bits(mode) <= 32);
- new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
- new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
- noreg = ia32_new_NoReg_gp(env_cg);
- nomem = new_NoMem();
+ if(addr.index == NULL) {
+ addr.index = noreg;
+ } else {
+ addr.index = be_transform_node(addr.index);
+ }
+ addr.mem = be_transform_node(mem);
- res = new_rd_ia32_TestJmp(dbgi, current_ir_graph, block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem, pnc);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
+ if (mode_is_float(mode)) {
+ /* convs (and strict-convs) before stores are unnecessary if the mode
+ is the same */
+ while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
+ val = get_Conv_op(val);
+ }
+ new_val = be_transform_node(val);
+ if (USE_SSE2(env_cg)) {
+ new_node = new_rd_ia32_xStore(dbgi, irg, new_block, addr.base,
+ addr.index, addr.mem, new_val);
+ } else {
+ new_node = new_rd_ia32_vfst(dbgi, irg, new_block, addr.base,
+ addr.index, addr.mem, new_val, mode);
+ }
+ } else if(is_float_to_int32_conv(val)) {
+ ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
+ val = get_Conv_op(val);
+
+ /* convs (and strict-convs) before stores are unnecessary if the mode
+ is the same */
+ while(is_Conv(val) && mode == get_irn_mode(get_Conv_op(val))) {
+ val = get_Conv_op(val);
+ }
+ new_val = be_transform_node(val);
- return res;
+ new_node = new_rd_ia32_vfist(dbgi, irg, new_block, addr.base,
+ addr.index, addr.mem, new_val, trunc_mode);
+ } else {
+ new_val = create_immediate_or_transform(val, 0);
+ assert(mode != mode_b);
+
+ if (get_mode_size_bits(mode) == 8) {
+ new_node = new_rd_ia32_Store8Bit(dbgi, irg, new_block, addr.base,
+ addr.index, addr.mem, new_val);
+ } else {
+ new_node = new_rd_ia32_Store(dbgi, irg, new_block, addr.base,
+ addr.index, addr.mem, new_val);
+ }
+ }
+
+ set_irn_pinned(new_node, get_irn_pinned(node));
+ set_ia32_op_type(new_node, ia32_AddrModeD);
+ set_ia32_ls_mode(new_node, mode);
+
+ set_ia32_exc_label(new_node,
+ be_get_Proj_for_pn(node, pn_Store_X_except) != NULL);
+ set_address(new_node, &addr);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ return new_node;
}
static ir_node *create_Switch(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *sel = get_Cond_selector(node);
- ir_node *new_sel = be_transform_node(sel);
- ir_node *res;
- int switch_min = INT_MAX;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *sel = get_Cond_selector(node);
+ ir_node *new_sel = be_transform_node(sel);
+ int switch_min = INT_MAX;
+ ir_node *new_node;
const ir_edge_t *edge;
assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
}
if (switch_min != 0) {
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
/* if smallest switch case is not 0 we need an additional sub */
new_sel = new_rd_ia32_Lea(dbgi, irg, block, new_sel, noreg);
add_ia32_am_offs_int(new_sel, -switch_min);
- set_ia32_am_flavour(new_sel, ia32_am_OB);
set_ia32_op_type(new_sel, ia32_AddrModeS);
SET_IA32_ORIG_NODE(new_sel, ia32_get_old_node_name(env_cg, node));
}
- res = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel);
- set_ia32_pncode(res, get_Cond_defaultProj(node));
-
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ new_node = new_rd_ia32_SwitchJmp(dbgi, irg, block, new_sel,
+ get_Cond_defaultProj(node));
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return res;
+ return new_node;
}
-/**
- * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
- *
- * @return The transformed node.
- */
static ir_node *gen_Cond(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *sel = get_Cond_selector(node);
- ir_mode *sel_mode = get_irn_mode(sel);
- ir_node *res = NULL;
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *cmp;
- ir_node *cmp_a;
- ir_node *cmp_b;
- ir_node *new_cmp_a;
- ir_node *new_cmp_b;
- ir_mode *cmp_mode;
- ir_node *nomem = new_NoMem();
- long pnc;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *sel = get_Cond_selector(node);
+ ir_mode *sel_mode = get_irn_mode(sel);
+ ir_node *flags = NULL;
+ ir_node *new_node;
+ pn_Cmp pnc;
if (sel_mode != mode_b) {
return create_Switch(node);
}
- if(!is_Proj(sel) || !is_Cmp(get_Proj_pred(sel))) {
- /* it's some mode_b value but not a direct comparison -> create a
- * testjmp */
- res = try_create_TestJmp(block, dbgi, pn_Cmp_Lg, sel, NULL);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
- return res;
- }
-
- cmp = get_Proj_pred(sel);
- cmp_a = get_Cmp_left(cmp);
- cmp_b = get_Cmp_right(cmp);
- cmp_mode = get_irn_mode(cmp_a);
- pnc = get_Proj_proj(sel);
- if(mode_is_float(cmp_mode) || !mode_is_signed(cmp_mode)) {
- pnc |= ia32_pn_Cmp_Unsigned;
- }
-
- if(mode_needs_gp_reg(cmp_mode)) {
- res = try_create_TestJmp(block, dbgi, pnc, cmp_a, cmp_b);
- if(res != NULL) {
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
- return res;
- }
- }
-
- new_cmp_a = be_transform_node(cmp_a);
- new_cmp_b = create_immediate_or_transform(cmp_b, 0);
-
- if (mode_is_float(cmp_mode)) {
- if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_xCondJmp(dbgi, irg, block, noreg, noreg, cmp_a,
- cmp_b, nomem, pnc);
- set_ia32_commutative(res);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
- set_ia32_ls_mode(res, cmp_mode);
- } else {
- res = new_rd_ia32_vfCondJmp(dbgi, irg, block, cmp_a, cmp_b, pnc);
- set_ia32_commutative(res);
- }
- } else {
- /** workaround smaller compare modes with converts...
- * We could easily support 16bit compares, for 8 bit we have to set
- * additional register constraints, which we don't do yet
- */
- new_cmp_a = maybe_scale_up(new_cmp_a, cmp_mode, dbgi);
- new_cmp_b = maybe_scale_up(new_cmp_b, cmp_mode, dbgi);
-
- res = new_rd_ia32_CondJmp(dbgi, irg, block, noreg, noreg,
- new_cmp_a, new_cmp_b, nomem, pnc);
- set_ia32_commutative(res);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
- }
+ /* we get flags from a cmp */
+ flags = get_flags_node(sel, &pnc);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ new_node = new_rd_ia32_Jcc(dbgi, irg, new_block, flags, pnc);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return res;
+ return new_node;
}
rem = size & 0x3; /* size % 4 */
size >>= 2;
- res = new_rd_ia32_Const(dbgi, irg, block);
- add_irn_dep(res, be_abi_get_start_barrier(env_cg->birg->abi));
- set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
+ res = new_rd_ia32_Const(dbgi, irg, block, NULL, 0, size);
+ add_irn_dep(res, get_irg_frame(irg));
+
+ res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem, rem);
+ } else {
+ if(size == 0) {
+ ir_fprintf(stderr, "Optimisation warning copyb %+F with size <4\n",
+ node);
+ }
+ res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem, size);
+ }
+
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+
+ return res;
+}
+
+static ir_node *gen_be_Copy(ir_node *node)
+{
+ ir_node *new_node = be_duplicate_node(node);
+ ir_mode *mode = get_irn_mode(new_node);
+
+ if (mode_needs_gp_reg(mode)) {
+ set_irn_mode(new_node, mode_Iu);
+ }
+
+ return new_node;
+}
+
+static ir_node *create_Fucom(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *left = get_Cmp_left(node);
+ ir_node *new_left = be_transform_node(left);
+ ir_node *right = get_Cmp_right(node);
+ ir_node *new_right;
+ ir_node *new_node;
+
+ if(transform_config.use_fucomi) {
+ new_right = be_transform_node(right);
+ new_node = new_rd_ia32_vFucomi(dbgi, irg, new_block, new_left,
+ new_right, 0);
+ set_ia32_commutative(new_node);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ } else {
+ if(transform_config.use_ftst && is_Const_null(right)) {
+ new_node = new_rd_ia32_vFtstFnstsw(dbgi, irg, new_block, new_left,
+ 0);
+ } else {
+ new_right = be_transform_node(right);
+ new_node = new_rd_ia32_vFucomFnstsw(dbgi, irg, new_block, new_left,
+ new_right, 0);
+ }
+
+ set_ia32_commutative(new_node);
- res = new_rd_ia32_CopyB(dbgi, irg, block, new_dst, new_src, res, new_mem);
- set_ia32_Immop_tarval(res, new_tarval_from_long(rem, mode_Is));
- } else {
- res = new_rd_ia32_CopyB_i(dbgi, irg, block, new_dst, new_src, new_mem);
- set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ new_node = new_rd_ia32_Sahf(dbgi, irg, new_block, new_node);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
}
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ return new_node;
+}
- return res;
+static ir_node *create_Ucomi(ir_node *node)
+{
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *src_block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(src_block);
+ ir_node *left = get_Cmp_left(node);
+ ir_node *right = get_Cmp_right(node);
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+
+ match_arguments(&am, src_block, left, right, match_commutative | match_am);
+
+ new_node = new_rd_ia32_Ucomi(dbgi, irg, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2,
+ am.ins_permuted);
+ set_am_attributes(new_node, &am);
+
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+
+ new_node = fix_mem_proj(new_node, &am);
+
+ return new_node;
}
-static
-ir_node *gen_be_Copy(ir_node *node)
+/**
+ * helper function: checks wether all Cmp projs are Lg or Eq which is needed
+ * to fold an and into a test node
+ */
+static int can_fold_test_and(ir_node *node)
{
- ir_node *result = be_duplicate_node(node);
- ir_mode *mode = get_irn_mode(result);
+ const ir_edge_t *edge;
- if (mode_needs_gp_reg(mode)) {
- set_irn_mode(result, mode_Iu);
+ /** we can only have eq and lg projs */
+ foreach_out_edge(node, edge) {
+ ir_node *proj = get_edge_src_irn(edge);
+ pn_Cmp pnc = get_Proj_proj(proj);
+ if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
+ return 0;
}
- return result;
+ return 1;
}
-
-static ir_node *create_set(long pnc, ir_node *cmp_left, ir_node *cmp_right,
- dbg_info *dbgi, ir_node *block)
+static ir_node *gen_Cmp(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
- ir_mode *mode;
- ir_node *new_cmp_left;
- ir_node *new_cmp_right;
- ir_node *res;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *left = get_Cmp_left(node);
+ ir_node *right = get_Cmp_right(node);
+ ir_mode *cmp_mode = get_irn_mode(left);
+ ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+ int cmp_unsigned;
- /* can we use a test instruction? */
- if(cmp_right == NULL || is_Const_0(cmp_right)) {
- long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
- if(is_And(cmp_left) &&
- (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
- ir_node *and_left = get_And_left(cmp_left);
- ir_node *and_right = get_And_right(cmp_left);
-
- mode = get_irn_mode(and_left);
- new_cmp_left = be_transform_node(and_left);
- new_cmp_right = create_immediate_or_transform(and_right, 0);
+ if(mode_is_float(cmp_mode)) {
+ if (USE_SSE2(env_cg)) {
+ return create_Ucomi(node);
} else {
- mode = get_irn_mode(cmp_left);
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = be_transform_node(cmp_left);
+ return create_Fucom(node);
}
-
- assert(get_mode_size_bits(mode) <= 32);
- new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
- new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
-
- res = new_rd_ia32_TestSet(dbgi, current_ir_graph, block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem, pnc);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
-
- return res;
}
- mode = get_irn_mode(cmp_left);
-
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = create_immediate_or_transform(cmp_right, 0);
+ assert(mode_needs_gp_reg(cmp_mode));
+
+ /* we prefer the Test instruction where possible except cases where
+ * we can use SourceAM */
+ cmp_unsigned = !mode_is_signed(cmp_mode);
+ if (is_Const_0(right)) {
+ if (is_And(left) &&
+ get_irn_n_edges(left) == 1 &&
+ can_fold_test_and(node)) {
+ /* Test(and_left, and_right) */
+ ir_node *and_left = get_And_left(left);
+ ir_node *and_right = get_And_right(left);
+ ir_mode *mode = get_irn_mode(and_left);
+
+ match_arguments(&am, block, and_left, and_right, match_commutative |
+ match_am | match_8bit_am | match_16bit_am |
+ match_am_and_immediates | match_immediate |
+ match_8bit | match_16bit);
+ if (get_mode_size_bits(mode) == 8) {
+ new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.ins_permuted,
+ cmp_unsigned);
+ } else {
+ new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.ins_permuted, cmp_unsigned);
+ }
+ } else {
+ match_arguments(&am, block, NULL, left, match_am | match_8bit_am |
+ match_16bit_am | match_8bit | match_16bit);
+ if (am.op_type == ia32_AddrModeS) {
+ /* Cmp(AM, 0) */
+ ir_node *imm_zero = try_create_Immediate(right, 0);
+ if (get_mode_size_bits(cmp_mode) == 8) {
+ new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op2,
+ imm_zero, am.ins_permuted,
+ cmp_unsigned);
+ } else {
+ new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op2,
+ imm_zero, am.ins_permuted, cmp_unsigned);
+ }
+ } else {
+ /* Test(left, left) */
+ if (get_mode_size_bits(cmp_mode) == 8) {
+ new_node = new_rd_ia32_Test8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op2,
+ am.new_op2, am.ins_permuted,
+ cmp_unsigned);
+ } else {
+ new_node = new_rd_ia32_Test(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op2,
+ am.new_op2, am.ins_permuted,
+ cmp_unsigned);
+ }
+ }
+ }
+ } else {
+ /* Cmp(left, right) */
+ match_arguments(&am, block, left, right, match_commutative | match_am |
+ match_8bit_am | match_16bit_am | match_am_and_immediates |
+ match_immediate | match_8bit | match_16bit);
+ if (get_mode_size_bits(cmp_mode) == 8) {
+ new_node = new_rd_ia32_Cmp8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.ins_permuted,
+ cmp_unsigned);
+ } else {
+ new_node = new_rd_ia32_Cmp(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op1,
+ am.new_op2, am.ins_permuted, cmp_unsigned);
+ }
+ }
+ set_am_attributes(new_node, &am);
+ assert(cmp_mode != NULL);
+ set_ia32_ls_mode(new_node, cmp_mode);
- assert(get_mode_size_bits(mode) <= 32);
- new_cmp_left = maybe_scale_up(new_cmp_left, mode, dbgi);
- new_cmp_right = maybe_scale_up(new_cmp_right, mode, dbgi);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- res = new_rd_ia32_CmpSet(dbgi, irg, block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem, pnc);
+ new_node = fix_mem_proj(new_node, &am);
- return res;
+ return new_node;
}
-static ir_node *create_cmov(long pnc, ir_node *cmp_left, ir_node *cmp_right,
- ir_node *val_true, ir_node *val_false,
- dbg_info *dbgi, ir_node *block)
+static ir_node *create_CMov(ir_node *node, ir_node *new_flags, pn_Cmp pnc)
{
- ir_graph *irg = current_ir_graph;
- ir_node *new_val_true = be_transform_node(val_true);
- ir_node *new_val_false = be_transform_node(val_false);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *new_cmp_left;
- ir_node *new_cmp_right;
- ir_node *res;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *val_true = get_Psi_val(node, 0);
+ ir_node *val_false = get_Psi_default(node);
+ ir_node *new_node;
+ match_flags_t match_flags;
+ ia32_address_mode_t am;
+ ia32_address_t *addr;
- /* cmovs with unknowns are pointless... */
- if(is_Unknown(val_true)) {
-#ifdef DEBUG_libfirm
- ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
-#endif
- return new_val_false;
- }
- if(is_Unknown(val_false)) {
-#ifdef DEBUG_libfirm
- ir_fprintf(stderr, "Optimisation warning: psi with unknown operand\n");
-#endif
- return new_val_true;
- }
+ assert(transform_config.use_cmov);
+ assert(mode_needs_gp_reg(get_irn_mode(val_true)));
- /* can we use a test instruction? */
- if(is_Const_0(cmp_right)) {
- long pure_pnc = pnc & ~ia32_pn_Cmp_Unsigned;
- if(is_And(cmp_left) &&
- (pure_pnc == pn_Cmp_Eq || pure_pnc == pn_Cmp_Lg)) {
- ir_node *and_left = get_And_left(cmp_left);
- ir_node *and_right = get_And_right(cmp_left);
+ addr = &am.addr;
- new_cmp_left = be_transform_node(and_left);
- new_cmp_right = create_immediate_or_transform(and_right, 0);
- } else {
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = be_transform_node(cmp_left);
- }
+ match_flags = match_commutative | match_am | match_16bit_am |
+ match_mode_neutral;
- res = new_rd_ia32_TestCMov(dbgi, current_ir_graph, block, noreg, noreg,
- new_cmp_left, new_cmp_right, nomem,
- new_val_true, new_val_false, pnc);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
+ match_arguments(&am, block, val_false, val_true, match_flags);
- return res;
- }
+ new_node = new_rd_ia32_CMov(dbgi, irg, new_block, addr->base, addr->index,
+ addr->mem, am.new_op1, am.new_op2, new_flags,
+ am.ins_permuted, pnc);
+ set_am_attributes(new_node, &am);
- new_cmp_left = be_transform_node(cmp_left);
- new_cmp_right = create_immediate_or_transform(cmp_right, 0);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- res = new_rd_ia32_CmpCMov(dbgi, irg, block, noreg, noreg, new_cmp_left,
- new_cmp_right, nomem, new_val_true, new_val_false,
- pnc);
- set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);
+ new_node = fix_mem_proj(new_node, &am);
- return res;
+ return new_node;
}
+
+static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
+ ir_node *flags, pn_Cmp pnc, ir_node *orig_node,
+ int ins_permuted)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_NoMem();
+ ir_mode *mode = get_irn_mode(orig_node);
+ ir_node *new_node;
+
+ new_node = new_rd_ia32_Set(dbgi, irg, new_block, flags, pnc, ins_permuted);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
+
+ /* we might need to conv the result up */
+ if(get_mode_size_bits(mode) > 8) {
+ new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_node, mode_Bu);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, orig_node));
+ }
+
+ return new_node;
+}
+
/**
* Transforms a Psi node into CMov.
*
* @return The transformed node.
*/
-static ir_node *gen_Psi(ir_node *node) {
+static ir_node *gen_Psi(ir_node *node)
+{
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
ir_node *psi_true = get_Psi_val(node, 0);
ir_node *psi_default = get_Psi_default(node);
- ia32_code_gen_t *cg = env_cg;
ir_node *cond = get_Psi_cond(node, 0);
- ir_node *block = be_transform_node(get_nodes_block(node));
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_op;
- ir_node *cmp_left;
- ir_node *cmp_right;
- ir_mode *cmp_mode;
- long pnc;
+ ir_node *flags = NULL;
+ ir_node *new_node;
+ pn_Cmp pnc;
assert(get_Psi_n_conds(node) == 1);
assert(get_irn_mode(cond) == mode_b);
assert(mode_needs_gp_reg(get_irn_mode(node)));
- if(!is_Proj(cond) || !is_Cmp(get_Proj_pred(cond))) {
- /* a mode_b value, we have to compare it against 0 */
- cmp_left = cond;
- cmp_right = new_Const_long(mode_Iu, 0);
- pnc = pn_Cmp_Lg;
- cmp_mode = mode_Iu;
- } else {
- ir_node *cmp = get_Proj_pred(cond);
-
- cmp_left = get_Cmp_left(cmp);
- cmp_right = get_Cmp_right(cmp);
- cmp_mode = get_irn_mode(cmp_left);
- pnc = get_Proj_proj(cond);
-
- assert(!mode_is_float(cmp_mode));
-
- if (!mode_is_signed(cmp_mode)) {
- pnc |= ia32_pn_Cmp_Unsigned;
- }
- }
+ flags = get_flags_node(cond, &pnc);
if(is_Const_1(psi_true) && is_Const_0(psi_default)) {
- new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 0);
} else if(is_Const_0(psi_true) && is_Const_1(psi_default)) {
- pnc = get_negated_pnc(pnc, cmp_mode);
- new_op = create_set(pnc, cmp_left, cmp_right, dbgi, block);
+ new_node = create_set_32bit(dbgi, new_block, flags, pnc, node, 1);
} else {
- new_op = create_cmov(pnc, cmp_left, cmp_right, psi_true, psi_default,
- dbgi, block);
+ new_node = create_CMov(node, flags, pnc);
}
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
- return new_op;
+ return new_node;
}
-/**
- * Following conversion rules apply:
- *
- * INT -> INT
- * ============
- * 1) n bit -> m bit n > m (downscale)
- * always ignored
- * 2) n bit -> m bit n == m (sign change)
- * always ignored
- * 3) n bit -> m bit n < m (upscale)
- * a) source is signed: movsx
- * b) source is unsigned: and with lower bits sets
- *
- * INT -> FLOAT
- * ==============
- * SSE(1/2) convert to float or double (cvtsi2ss/sd)
- *
- * FLOAT -> INT
- * ==============
- * SSE(1/2) convert from float or double to 32bit int (cvtss/sd2si)
- *
- * FLOAT -> FLOAT
- * ================
- * SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
- * x87 is mode_E internally, conversions happen only at load and store
- * in non-strict semantic
- */
-
/**
* Create a conversion from x87 state register to general purpose.
*/
ir_node *fist, *load;
/* do a fist */
- fist = new_rd_ia32_vfist(dbgi, irg, block,
- get_irg_frame(irg), noreg, new_op, trunc_mode, new_NoMem());
+ fist = new_rd_ia32_vfist(dbgi, irg, block, get_irg_frame(irg), noreg,
+ new_NoMem(), new_op, trunc_mode);
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
- set_ia32_am_flavour(fist, ia32_am_B);
assert(get_mode_size_bits(mode) <= 32);
/* exception we can only store signed 32 bit integers, so for unsigned
set_irn_pinned(load, op_pin_state_floats);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_am_flavour(load, ia32_am_B);
set_ia32_ls_mode(load, mode_Is);
+ if(get_ia32_ls_mode(fist) == mode_Ls) {
+ ia32_attr_t *attr = get_ia32_attr(load);
+ attr->data.need_64bit_stackent = 1;
+ } else {
+ ia32_attr_t *attr = get_ia32_attr(load);
+ attr->data.need_32bit_stackent = 1;
+ }
SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(cg, node));
return new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
}
-static ir_node *create_strict_conv(ir_mode *tgt_mode, ir_node *node)
+/**
+ * Creates a x87 strict Conv by placing a Sore and a Load
+ */
+static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
{
ir_node *block = get_nodes_block(node);
ir_graph *irg = current_ir_graph;
ir_node *nomem = new_NoMem();
ir_node *frame = get_irg_frame(irg);
ir_node *store, *load;
- ir_node *res;
+ ir_node *new_node;
- store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, node, nomem,
+ store = new_rd_ia32_vfst(dbgi, irg, block, frame, noreg, nomem, node,
tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_am_OB);
SET_IA32_ORIG_NODE(store, ia32_get_old_node_name(env_cg, node));
load = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, store,
tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
- set_ia32_am_flavour(load, ia32_am_OB);
SET_IA32_ORIG_NODE(load, ia32_get_old_node_name(env_cg, node));
- res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
- return res;
+ new_node = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
+ return new_node;
+}
+
+static ir_node *create_Immediate(ir_entity *symconst, int symconst_sign, long val)
+{
+ ir_graph *irg = current_ir_graph;
+ ir_node *start_block = get_irg_start_block(irg);
+ ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block,
+ symconst, symconst_sign, val);
+ arch_set_irn_register(env_cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
+
+ return immediate;
}
/**
* Create a conversion from general purpose to x87 register
*/
static ir_node *gen_x87_gp_to_fp(ir_node *node, ir_mode *src_mode) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = get_Conv_op(node);
- ir_node *new_op = be_transform_node(op);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_mode *mode = get_irn_mode(op);
- ir_mode *store_mode;
- ir_node *fild, *store;
- ir_node *res;
- int src_bits;
+ ir_node *src_block = get_nodes_block(node);
+ ir_node *block = be_transform_node(src_block);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *op = get_Conv_op(node);
+ ir_node *new_op = NULL;
+ ir_node *noreg;
+ ir_node *nomem;
+ ir_mode *mode;
+ ir_mode *store_mode;
+ ir_node *fild;
+ ir_node *store;
+ ir_node *new_node;
+ int src_bits;
+
+ /* fild can use source AM if the operand is a signed 32bit integer */
+ if (src_mode == mode_Is) {
+ ia32_address_mode_t am;
+
+ match_arguments(&am, src_block, NULL, op, match_am | match_try_am);
+ if (am.op_type == ia32_AddrModeS) {
+ ia32_address_t *addr = &am.addr;
+
+ fild = new_rd_ia32_vfild(dbgi, irg, block, addr->base,
+ addr->index, addr->mem);
+ new_node = new_r_Proj(irg, block, fild, mode_vfp,
+ pn_ia32_vfild_res);
+
+ set_am_attributes(fild, &am);
+ SET_IA32_ORIG_NODE(fild, ia32_get_old_node_name(env_cg, node));
+
+ fix_mem_proj(fild, &am);
+
+ return new_node;
+ }
+ }
+ if(new_op == NULL) {
+ new_op = be_transform_node(op);
+ }
+
+ noreg = ia32_new_NoReg_gp(env_cg);
+ nomem = new_NoMem();
+ mode = get_irn_mode(op);
/* first convert to 32 bit signed if necessary */
src_bits = get_mode_size_bits(src_mode);
if (src_bits == 8) {
- new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, new_op, nomem,
- src_mode);
- set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
+ new_op = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, block, noreg, noreg, nomem,
+ new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
mode = mode_Is;
} else if (src_bits < 32) {
- new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, new_op, nomem, src_mode);
- set_ia32_am_support(new_op, ia32_am_Source, ia32_am_unary);
+ new_op = new_rd_ia32_Conv_I2I(dbgi, irg, block, noreg, noreg, nomem,
+ new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
mode = mode_Is;
}
assert(get_mode_size_bits(mode) == 32);
/* do a store */
- store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, new_op, nomem);
+ store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg, nomem,
+ new_op);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_am_flavour(store, ia32_am_OB);
set_ia32_ls_mode(store, mode_Iu);
/* exception for 32bit unsigned, do a 64bit spill+load */
if(!mode_is_signed(mode)) {
ir_node *in[2];
/* store a zero */
- ir_node *zero_const = create_Immediate_from_int(0);
+ ir_node *zero_const = create_Immediate(NULL, 0, 0);
- ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block, get_irg_frame(irg), noreg,
- zero_const, nomem);
+ ir_node *zero_store = new_rd_ia32_Store(dbgi, irg, block,
+ get_irg_frame(irg), noreg, nomem,
+ zero_const);
set_ia32_use_frame(zero_store);
set_ia32_op_type(zero_store, ia32_AddrModeD);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
- set_ia32_am_flavour(fild, ia32_am_OB);
set_ia32_ls_mode(fild, store_mode);
- res = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
+ new_node = new_r_Proj(irg, block, fild, mode_vfp, pn_ia32_vfild_res);
- return res;
+ return new_node;
}
/**
- * Crete a conversion from one integer mode into another one
+ * Create a conversion from one integer mode into another one
*/
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
- dbg_info *dbgi, ir_node *new_block,
- ir_node *new_op)
+ dbg_info *dbgi, ir_node *block, ir_node *op,
+ ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
- ir_node *res;
+ ir_graph *irg = current_ir_graph;
+ int src_bits = get_mode_size_bits(src_mode);
+ int tgt_bits = get_mode_size_bits(tgt_mode);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_node;
ir_mode *smaller_mode;
int smaller_bits;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
if (src_bits < tgt_bits) {
smaller_mode = src_mode;
smaller_bits = tgt_bits;
}
- DB((dbg, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
+#ifdef DEBUG_libfirm
+ if(is_Const(op)) {
+ ir_fprintf(stderr, "Optimisation warning: conv after constant %+F\n",
+ op);
+ }
+#endif
+
+ match_arguments(&am, block, NULL, op,
+ match_8bit | match_16bit | match_8bit_am | match_16bit_am);
if (smaller_bits == 8) {
- res = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, noreg, noreg,
- new_op, nomem, smaller_mode);
+ new_node = new_rd_ia32_Conv_I2I8Bit(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op2,
+ smaller_mode);
} else {
- res = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, noreg, noreg, new_op,
- nomem, smaller_mode);
+ new_node = new_rd_ia32_Conv_I2I(dbgi, irg, new_block, addr->base,
+ addr->index, addr->mem, am.new_op2,
+ smaller_mode);
}
- set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
-
- return res;
+ set_am_attributes(new_node, &am);
+ /* match_arguments assume that out-mode = in-mode, this isn't true here
+ * so fix it */
+ set_ia32_ls_mode(new_node, smaller_mode);
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = fix_mem_proj(new_node, &am);
+ return new_node;
}
/**
* @return The created ia32 Conv node
*/
static ir_node *gen_Conv(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = get_Conv_op(node);
- ir_node *new_op = be_transform_node(op);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *src_mode = get_irn_mode(op);
- ir_mode *tgt_mode = get_irn_mode(node);
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_rd_NoMem(irg);
- ir_node *res;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *op = get_Conv_op(node);
+ ir_node *new_op = NULL;
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *src_mode = get_irn_mode(op);
+ ir_mode *tgt_mode = get_irn_mode(node);
+ int src_bits = get_mode_size_bits(src_mode);
+ int tgt_bits = get_mode_size_bits(tgt_mode);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *res = NULL;
if (src_mode == mode_b) {
assert(mode_is_int(tgt_mode));
/* nothing to do, we already model bools as 0/1 ints */
- return new_op;
+ return be_transform_node(op);
}
if (src_mode == tgt_mode) {
if (get_Conv_strict(node)) {
if (USE_SSE2(env_cg)) {
/* when we are in SSE mode, we can kill all strict no-op conversion */
- return new_op;
+ return be_transform_node(op);
}
} else {
/* this should be optimized already, but who knows... */
DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
- return new_op;
+ return be_transform_node(op);
}
}
if (mode_is_float(src_mode)) {
+ new_op = be_transform_node(op);
/* we convert from float ... */
if (mode_is_float(tgt_mode)) {
if(src_mode == mode_E && tgt_mode == mode_D
/* ... to float */
if (USE_SSE2(env_cg)) {
DB((dbg, LEVEL_1, "create Conv(float, float) ..."));
- res = new_rd_ia32_Conv_FP2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ res = new_rd_ia32_Conv_FP2FP(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
if(get_Conv_strict(node)) {
- res = create_strict_conv(tgt_mode, new_op);
+ res = gen_x87_strict_conv(tgt_mode, new_op);
SET_IA32_ORIG_NODE(get_Proj_pred(res), ia32_get_old_node_name(env_cg, node));
return res;
}
/* ... to int */
DB((dbg, LEVEL_1, "create Conv(float, int) ..."));
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_Conv_FP2I(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ res = new_rd_ia32_Conv_FP2I(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_op);
set_ia32_ls_mode(res, src_mode);
} else {
return gen_x87_fp_to_gp(node);
/* ... to float */
DB((dbg, LEVEL_1, "create Conv(int, float) ..."));
if (USE_SSE2(env_cg)) {
- res = new_rd_ia32_Conv_I2FP(dbgi, irg, block, noreg, noreg, new_op, nomem);
+ new_op = be_transform_node(op);
+ res = new_rd_ia32_Conv_I2FP(dbgi, irg, new_block, noreg, noreg,
+ nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
- if(src_bits == 32) {
- set_ia32_am_support(res, ia32_am_Source, ia32_am_unary);
- }
} else {
res = gen_x87_gp_to_fp(node, src_mode);
if(get_Conv_strict(node)) {
- res = create_strict_conv(tgt_mode, res);
+ res = gen_x87_strict_conv(tgt_mode, res);
SET_IA32_ORIG_NODE(get_Proj_pred(res),
ia32_get_old_node_name(env_cg, node));
}
/* mode_b lowering already took care that we only have 0/1 values */
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
- return new_op;
+ return be_transform_node(op);
} else {
/* to int */
if (src_bits == tgt_bits) {
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
- return new_op;
+ return be_transform_node(op);
}
- res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, new_op);
+ res = create_I2I_Conv(src_mode, tgt_mode, dbgi, block, op, node);
+ return res;
}
}
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
-
return res;
}
-static
-int check_immediate_constraint(long val, char immediate_constraint_type)
+static int check_immediate_constraint(long val, char immediate_constraint_type)
{
switch (immediate_constraint_type) {
case 0:
return 0;
}
-static
-ir_node *try_create_Immediate(ir_node *node, char immediate_constraint_type)
+static ir_node *try_create_Immediate(ir_node *node,
+ char immediate_constraint_type)
{
int minus = 0;
tarval *offset = NULL;
ir_mode *mode;
ir_node *cnst = NULL;
ir_node *symconst = NULL;
- ir_node *res;
- ir_graph *irg;
- dbg_info *dbgi;
- ir_node *block;
+ ir_node *new_node;
mode = get_irn_mode(node);
if(!mode_is_int(mode) && !mode_is_reference(mode)) {
offset = get_Const_tarval(cnst);
if(tarval_is_long(offset)) {
val = get_tarval_long(offset);
- } else if(tarval_is_null(offset)) {
- val = 0;
} else {
ir_fprintf(stderr, "Optimisation Warning: tarval from %+F is not a "
"long?\n", cnst);
return NULL;
}
+ /* unfortunately the assembler/linker doesn't support -symconst */
+ if(symconst_sign)
+ return NULL;
+
if(get_SymConst_kind(symconst) != symconst_addr_ent)
return NULL;
symconst_ent = get_SymConst_entity(symconst);
offset = tarval_neg(offset);
}
- irg = current_ir_graph;
- dbgi = get_irn_dbg_info(node);
- block = get_irg_start_block(irg);
- res = new_rd_ia32_Immediate(dbgi, irg, block, symconst_ent,
- symconst_sign, val);
- arch_set_irn_register(env_cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
+ new_node = create_Immediate(symconst_ent, symconst_sign, val);
- return res;
+ return new_node;
}
-static
-ir_node *create_immediate_or_transform(ir_node *node, char immediate_constraint_type)
+static ir_node *create_immediate_or_transform(ir_node *node,
+ char immediate_constraint_type)
{
ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
if (new_node == NULL) {
return new_node;
}
+static const arch_register_req_t no_register_req = {
+ arch_register_req_type_none,
+ NULL, /* regclass */
+ NULL, /* limit bitset */
+ { -1, -1 }, /* same pos */
+ -1 /* different pos */
+};
+
+/**
+ * An assembler constraint.
+ */
typedef struct constraint_t constraint_t;
struct constraint_t {
int is_in;
char immediate_type;
};
-void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
+static void parse_asm_constraint(int pos, constraint_t *constraint, const char *c)
{
int immediate_possible = 0;
char immediate_type = 0;
unsigned limited = 0;
const arch_register_class_t *cls = NULL;
- ir_graph *irg;
- struct obstack *obst;
+ ir_graph *irg = current_ir_graph;
+ struct obstack *obst = get_irg_obstack(irg);
arch_register_req_t *req;
unsigned *limited_ptr;
int p;
/* TODO: replace all the asserts with nice error messages */
- printf("Constraint: %s\n", c);
+ if(*c == 0) {
+ /* a memory constraint: no need to do anything in backend about it
+ * (the dependencies are already respected by the memory edge of
+ * the node) */
+ constraint->req = &no_register_req;
+ return;
+ }
while(*c != 0) {
switch(*c) {
}
break;
+ case 'm':
+ /* memory constraint no need to do anything in backend about it
+ * (the dependencies are already respected by the memory edge of
+ * the node) */
+ constraint->req = &no_register_req;
+ return;
+
case 'E': /* no float consts yet */
case 'F': /* no float consts yet */
case 's': /* makes no sense on x86 */
case 'X': /* we can't support that in firm */
- case 'm':
case 'o':
case 'V':
case '<': /* no autodecrement on x86 */
case 'y': /* we don't support mmx registers yet */
case 'Z': /* not available in 32 bit mode */
case 'e': /* not available in 32 bit mode */
- assert(0 && "asm constraint not supported");
+ panic("unsupported asm constraint '%c' found in (%+F)",
+ *c, current_ir_graph);
break;
default:
- assert(0 && "unknown asm constraint found");
+ panic("unknown asm constraint '%c' found in (%+F)", *c,
+ current_ir_graph);
break;
}
++c;
req->cls = other_constr->cls;
req->type = arch_register_req_type_should_be_same;
req->limited = NULL;
- req->other_same = pos;
+ req->other_same[0] = pos;
+ req->other_same[1] = -1;
req->other_different = -1;
/* switch constraints. This is because in firm we have same_as
if(immediate_possible) {
assert(constraint->is_in
- && "imeediates make no sense for output constraints");
+ && "immediate make no sense for output constraints");
}
- /* todo: check types (no float input on 'r' constrainted in and such... */
-
- irg = current_ir_graph;
- obst = get_irg_obstack(irg);
+ /* todo: check types (no float input on 'r' constrained in and such... */
if(limited != 0) {
req = obstack_alloc(obst, sizeof(req[0]) + sizeof(unsigned));
constraint->immediate_type = immediate_type;
}
-static
-void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
- const char *c)
+static void parse_clobber(ir_node *node, int pos, constraint_t *constraint,
+ const char *c)
{
(void) node;
(void) pos;
panic("Clobbers not supported yet");
}
-ir_node *gen_ASM(ir_node *node)
+static int is_memory_op(const ir_asm_constraint *constraint)
{
- int i, arity;
- ir_graph *irg = current_ir_graph;
- ir_node *block = be_transform_node(get_nodes_block(node));
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node **in;
- ir_node *res;
- int out_arity;
- int n_outs;
- int n_clobbers;
- void *generic_attr;
- ia32_asm_attr_t *attr;
- const arch_register_req_t **out_reqs;
- const arch_register_req_t **in_reqs;
- struct obstack *obst;
- constraint_t parsed_constraint;
+ ident *id = constraint->constraint;
+ const char *str = get_id_str(id);
+ const char *c;
+
+ for(c = str; *c != '\0'; ++c) {
+ if(*c == 'm')
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * generates code for a ASM node
+ */
+static ir_node *gen_ASM(ir_node *node)
+{
+ int i, arity;
+ ir_graph *irg = current_ir_graph;
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node **in;
+ ir_node *new_node;
+ int out_arity;
+ int n_out_constraints;
+ int n_clobbers;
+ const arch_register_req_t **out_reg_reqs;
+ const arch_register_req_t **in_reg_reqs;
+ ia32_asm_reg_t *register_map;
+ unsigned reg_map_size = 0;
+ struct obstack *obst;
+ const ir_asm_constraint *in_constraints;
+ const ir_asm_constraint *out_constraints;
+ ident **clobbers;
+ constraint_t parsed_constraint;
- /* transform inputs */
arity = get_irn_arity(node);
in = alloca(arity * sizeof(in[0]));
memset(in, 0, arity * sizeof(in[0]));
- n_outs = get_ASM_n_output_constraints(node);
- n_clobbers = get_ASM_n_clobbers(node);
- out_arity = n_outs + n_clobbers;
+ n_out_constraints = get_ASM_n_output_constraints(node);
+ n_clobbers = get_ASM_n_clobbers(node);
+ out_arity = n_out_constraints + n_clobbers;
+
+ in_constraints = get_ASM_input_constraints(node);
+ out_constraints = get_ASM_output_constraints(node);
+ clobbers = get_ASM_clobbers(node);
- /* construct register constraints */
- obst = get_irg_obstack(irg);
- out_reqs = obstack_alloc(obst, out_arity * sizeof(out_reqs[0]));
- parsed_constraint.out_reqs = out_reqs;
- parsed_constraint.n_outs = n_outs;
+ /* construct output constraints */
+ obst = get_irg_obstack(irg);
+ out_reg_reqs = obstack_alloc(obst, out_arity * sizeof(out_reg_reqs[0]));
+ parsed_constraint.out_reqs = out_reg_reqs;
+ parsed_constraint.n_outs = n_out_constraints;
parsed_constraint.is_in = 0;
+
for(i = 0; i < out_arity; ++i) {
const char *c;
- if(i < n_outs) {
- const ir_asm_constraint *constraint;
- constraint = & get_ASM_output_constraints(node) [i];
+ if(i < n_out_constraints) {
+ const ir_asm_constraint *constraint = &out_constraints[i];
c = get_id_str(constraint->constraint);
parse_asm_constraint(i, &parsed_constraint, c);
+
+ if(constraint->pos > reg_map_size)
+ reg_map_size = constraint->pos;
} else {
- ident *glob_id = get_ASM_clobbers(node) [i - n_outs];
+ ident *glob_id = clobbers [i - n_out_constraints];
c = get_id_str(glob_id);
parse_clobber(node, i, &parsed_constraint, c);
}
- out_reqs[i] = parsed_constraint.req;
+
+ out_reg_reqs[i] = parsed_constraint.req;
}
- in_reqs = obstack_alloc(obst, arity * sizeof(in_reqs[0]));
+ /* construct input constraints */
+ in_reg_reqs = obstack_alloc(obst, arity * sizeof(in_reg_reqs[0]));
parsed_constraint.is_in = 1;
for(i = 0; i < arity; ++i) {
- const ir_asm_constraint *constraint;
- ident *constr_id;
- const char *c;
+ const ir_asm_constraint *constraint = &in_constraints[i];
+ ident *constr_id = constraint->constraint;
+ const char *c = get_id_str(constr_id);
- constraint = & get_ASM_input_constraints(node) [i];
- constr_id = constraint->constraint;
- c = get_id_str(constr_id);
parse_asm_constraint(i, &parsed_constraint, c);
- in_reqs[i] = parsed_constraint.req;
+ in_reg_reqs[i] = parsed_constraint.req;
+
+ if(constraint->pos > reg_map_size)
+ reg_map_size = constraint->pos;
if(parsed_constraint.immediate_possible) {
ir_node *pred = get_irn_n(node, i);
if(immediate != NULL) {
in[i] = immediate;
}
- }
- }
-
- /* transform inputs */
- for(i = 0; i < arity; ++i) {
- ir_node *pred;
- ir_node *transformed;
-
- if(in[i] != NULL)
- continue;
-
- pred = get_irn_n(node, i);
- transformed = be_transform_node(pred);
- in[i] = transformed;
- }
-
- res = new_rd_ia32_Asm(dbgi, irg, block, arity, in, out_arity);
-
- generic_attr = get_irn_generic_attr(res);
- attr = CAST_IA32_ATTR(ia32_asm_attr_t, generic_attr);
- attr->asm_text = get_ASM_text(node);
- set_ia32_out_req_all(res, out_reqs);
- set_ia32_in_req_all(res, in_reqs);
-
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
-
- return res;
-}
-
-/********************************************
- * _ _
- * | | | |
- * | |__ ___ _ __ ___ __| | ___ ___
- * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
- * | |_) | __/ | | | (_) | (_| | __/\__ \
- * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
- *
- ********************************************/
-
-static ir_node *gen_be_StackParam(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *ptr = get_irn_n(node, be_pos_StackParam_ptr);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *nomem = new_rd_NoMem(current_ir_graph);
- ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
- ir_mode *load_mode = get_irn_mode(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_mode *proj_mode;
- long pn_res;
-
- if (mode_is_float(load_mode)) {
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, nomem);
- pn_res = pn_ia32_xLoad_res;
- proj_mode = mode_xmm;
- } else {
- new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, nomem, load_mode);
- pn_res = pn_ia32_vfld_res;
- proj_mode = mode_vfp;
- }
- } else {
- new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, nomem);
- proj_mode = mode_Iu;
- pn_res = pn_ia32_Load_res;
- }
-
- set_irn_pinned(new_op, op_pin_state_floats);
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
-
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_ls_mode(new_op, load_mode);
- set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
-
- return new_rd_Proj(dbgi, irg, block, new_op, proj_mode, pn_res);
-}
-
-/**
- * Transforms a FrameAddr into an ia32 Add.
- */
-static ir_node *gen_be_FrameAddr(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *op = be_get_FrameAddr_frame(node);
- ir_node *new_op = be_transform_node(op);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *res;
+ }
+ }
+ reg_map_size++;
- res = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
- set_ia32_frame_ent(res, arch_get_frame_entity(env_cg->arch_env, node));
- set_ia32_use_frame(res);
- set_ia32_am_flavour(res, ia32_am_OB);
+ register_map = NEW_ARR_D(ia32_asm_reg_t, obst, reg_map_size);
+ memset(register_map, 0, reg_map_size * sizeof(register_map[0]));
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, node));
+ for(i = 0; i < n_out_constraints; ++i) {
+ const ir_asm_constraint *constraint = &out_constraints[i];
+ unsigned pos = constraint->pos;
- return res;
-}
+ assert(pos < reg_map_size);
+ register_map[pos].use_input = 0;
+ register_map[pos].valid = 1;
+ register_map[pos].memory = is_memory_op(constraint);
+ register_map[pos].inout_pos = i;
+ register_map[pos].mode = constraint->mode;
+ }
-/**
- * Transforms a FrameLoad into an ia32 Load.
- */
-static ir_node *gen_be_FrameLoad(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *mem = get_irn_n(node, be_pos_FrameLoad_mem);
- ir_node *new_mem = be_transform_node(mem);
- ir_node *ptr = get_irn_n(node, be_pos_FrameLoad_ptr);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
- ir_mode *mode = get_type_mode(get_entity_type(ent));
- ir_node *projs[pn_Load_max];
+ /* transform inputs */
+ for(i = 0; i < arity; ++i) {
+ const ir_asm_constraint *constraint = &in_constraints[i];
+ unsigned pos = constraint->pos;
+ ir_node *pred = get_irn_n(node, i);
+ ir_node *transformed;
+
+ assert(pos < reg_map_size);
+ register_map[pos].use_input = 1;
+ register_map[pos].valid = 1;
+ register_map[pos].memory = is_memory_op(constraint);
+ register_map[pos].inout_pos = i;
+ register_map[pos].mode = constraint->mode;
- ia32_collect_Projs(node, projs, pn_Load_max);
+ if(in[i] != NULL)
+ continue;
- if (mode_is_float(mode)) {
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, new_mem);
- }
- else {
- new_op = new_rd_ia32_vfld(dbgi, irg, block, new_ptr, noreg, new_mem, mode);
- }
- }
- else {
- new_op = new_rd_ia32_Load(dbgi, irg, block, new_ptr, noreg, new_mem);
+ transformed = be_transform_node(pred);
+ in[i] = transformed;
}
- set_irn_pinned(new_op, op_pin_state_floats);
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
+ new_node = new_rd_ia32_Asm(dbgi, irg, new_block, arity, in, out_arity,
+ get_ASM_text(node), register_map);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_ls_mode(new_op, mode);
- set_ia32_flags(new_op, get_ia32_flags(new_op) | arch_irn_flags_rematerializable);
+ set_ia32_out_req_all(new_node, out_reg_reqs);
+ set_ia32_in_req_all(new_node, in_reg_reqs);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return new_op;
+ return new_node;
}
+/********************************************
+ * _ _
+ * | | | |
+ * | |__ ___ _ __ ___ __| | ___ ___
+ * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
+ * | |_) | __/ | | | (_) | (_| | __/\__ \
+ * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
+ *
+ ********************************************/
/**
- * Transforms a FrameStore into an ia32 Store.
+ * Transforms a FrameAddr into an ia32 Add.
*/
-static ir_node *gen_be_FrameStore(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *mem = get_irn_n(node, be_pos_FrameStore_mem);
- ir_node *new_mem = be_transform_node(mem);
- ir_node *ptr = get_irn_n(node, be_pos_FrameStore_ptr);
- ir_node *new_ptr = be_transform_node(ptr);
- ir_node *val = get_irn_n(node, be_pos_FrameStore_val);
- ir_node *new_val = be_transform_node(val);
- ir_node *new_op = NULL;
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_entity *ent = arch_get_frame_entity(env_cg->arch_env, node);
- ir_mode *mode = get_irn_mode(val);
-
- if (mode_is_float(mode)) {
- if (USE_SSE2(env_cg)) {
- new_op = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- } else {
- new_op = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, mode);
- }
- } else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- } else {
- new_op = new_rd_ia32_Store(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- }
-
- set_ia32_frame_ent(new_op, ent);
- set_ia32_use_frame(new_op);
+static ir_node *gen_be_FrameAddr(ir_node *node) {
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *op = be_get_FrameAddr_frame(node);
+ ir_node *new_op = be_transform_node(op);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *noreg = ia32_new_NoReg_gp(env_cg);
+ ir_node *new_node;
- set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, ia32_am_B);
- set_ia32_ls_mode(new_op, mode);
+ new_node = new_rd_ia32_Lea(dbgi, irg, block, new_op, noreg);
+ set_ia32_frame_ent(new_node, arch_get_frame_entity(env_cg->arch_env, node));
+ set_ia32_use_frame(new_node);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- return new_op;
+ return new_node;
}
/**
/* store xmm0 onto stack */
sse_store = new_rd_ia32_xStoreSimple(dbgi, irg, block, frame, noreg,
- new_ret_val, new_ret_mem);
+ new_ret_mem, new_ret_val);
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
- set_ia32_am_flavour(sse_store, ia32_am_B);
/* load into x87 register */
fld = new_rd_ia32_vfld(dbgi, irg, block, frame, noreg, sse_store, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
- set_ia32_am_flavour(fld, ia32_am_B);
mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_vfld_M);
fld = new_r_Proj(irg, block, fld, mode_vfp, pn_ia32_vfld_res);
}
/**
- * Transform a be_AddSP into an ia32_AddSP. Eat up const sizes.
+ * Transform a be_AddSP into an ia32_SubSP.
*/
-static ir_node *gen_be_AddSP(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
- ir_node *new_sz;
- ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
- ir_node *new_sp = be_transform_node(sp);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *new_op;
-
- new_sz = create_immediate_or_transform(sz, 0);
-
- /* ia32 stack grows in reverse direction, make a SubSP */
- new_op = new_rd_ia32_SubSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz,
- nomem);
- set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+static ir_node *gen_be_AddSP(ir_node *node)
+{
+ ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
+ ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
- return new_op;
+ return gen_binop(node, sp, sz, new_rd_ia32_SubSP, match_am);
}
/**
- * Transform a be_SubSP into an ia32_SubSP. Eat up const sizes.
+ * Transform a be_SubSP into an ia32_AddSP
*/
-static ir_node *gen_be_SubSP(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
- ir_node *new_sz;
- ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
- ir_node *new_sp = be_transform_node(sp);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *new_op;
-
- new_sz = create_immediate_or_transform(sz, 0);
-
- /* ia32 stack grows in reverse direction, make an AddSP */
- new_op = new_rd_ia32_AddSP(dbgi, irg, block, noreg, noreg, new_sp, new_sz, nomem);
- set_ia32_am_support(new_op, ia32_am_Source, ia32_am_binary);
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
+static ir_node *gen_be_SubSP(ir_node *node)
+{
+ ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
+ ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
- return new_op;
+ return gen_binop(node, sp, sz, new_rd_ia32_AddSP, match_am);
}
/**
ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
-#if 0
- /* Unknown nodes are buggy in x87 sim, use zero for now... */
- if (USE_SSE2(env_cg))
+ if (USE_SSE2(env_cg)) {
return ia32_new_Unknown_xmm(env_cg);
- else
- return ia32_new_Unknown_vfp(env_cg);
-#else
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_irg_start_block(irg);
- return new_rd_ia32_vfldz(dbgi, irg, block);
-#endif
+ } else {
+ /* Unknown nodes are buggy in x87 sim, use zero for now... */
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_irg_start_block(irg);
+ return new_rd_ia32_vfldz(dbgi, irg, block);
+ }
} else if (mode_needs_gp_reg(mode)) {
return ia32_new_Unknown_gp(env_cg);
} else {
- assert(0 && "unsupported Unknown-Mode");
+ panic("unsupported Unknown-Mode");
}
-
return NULL;
}
/* phi nodes allow loops, so we use the old arguments for now
* and fix this later */
- phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node), get_irn_in(node) + 1);
+ phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
+ get_irn_in(node) + 1);
copy_node_attr(node, phi);
be_duplicate_deps(node, phi);
/**
* Transform IJmp
*/
-static ir_node *gen_IJmp(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_op = be_transform_node(get_IJmp_target(node));
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
+static ir_node *gen_IJmp(ir_node *node)
+{
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *op = get_IJmp_target(node);
ir_node *new_node;
+ ia32_address_mode_t am;
+ ia32_address_t *addr = &am.addr;
+
+ assert(get_irn_mode(op) == mode_P);
- new_node = new_rd_ia32_IJmp(dbgi, irg, block, noreg, noreg, new_op, nomem);
- set_ia32_am_support(new_node, ia32_am_Source, ia32_am_unary);
+ match_arguments(&am, block, NULL, op,
+ match_am | match_8bit_am | match_16bit_am |
+ match_immediate | match_8bit | match_16bit);
+ new_node = new_rd_ia32_IJmp(dbgi, irg, new_block, addr->base, addr->index,
+ addr->mem, am.new_op2);
+ set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
+ new_node = fix_mem_proj(new_node, &am);
+
return new_node;
}
new_op = func(dbgi, irg, block, new_ptr, noreg, new_mem);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_OB);
- set_ia32_am_offs_int(new_op, 0);
- set_ia32_am_scale(new_op, 1);
+ set_ia32_am_offs_int(new_op, get_ia32_am_offs_int(node));
+ set_ia32_am_scale(new_op, get_ia32_am_scale(node));
set_ia32_am_sc(new_op, get_ia32_am_sc(node));
if (is_ia32_am_sc_sign(node))
set_ia32_am_sc_sign(new_op);
ir_mode *mode = get_ia32_ls_mode(node);
ir_node *new_op;
long am_offs;
- ia32_am_flavour_t am_flav = ia32_B;
new_op = func(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
- if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
- am_flav |= ia32_O;
- add_ia32_am_offs_int(new_op, am_offs);
- }
+ am_offs = get_ia32_am_offs_int(node);
+ add_ia32_am_offs_int(new_op, am_offs);
set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, am_flav);
set_ia32_ls_mode(new_op, mode);
set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
set_ia32_use_frame(new_op);
return new_op;
}
+static ir_node *gen_ia32_l_ShlDep(ir_node *node)
+{
+ ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_left);
+ ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_right);
-/**
- * Transforms an ia32_l_XXX into a "real" XXX node
- *
- * @param env The transformation environment
- * @return the created ia32 XXX node
- */
-#define GEN_LOWERED_OP(op) \
- static ir_node *gen_ia32_l_##op(ir_node *node) { \
- return gen_binop(node, get_binop_left(node), \
- get_binop_right(node), new_rd_ia32_##op,0); \
- }
+ return gen_shift_binop(node, left, right, new_rd_ia32_Shl,
+ match_immediate | match_mode_neutral);
+}
-#define GEN_LOWERED_x87_OP(op) \
- static ir_node *gen_ia32_l_##op(ir_node *node) { \
- ir_node *new_op; \
- new_op = gen_binop_x87_float(node, get_binop_left(node), \
- get_binop_right(node), new_rd_ia32_##op); \
- return new_op; \
- }
+static ir_node *gen_ia32_l_ShrDep(ir_node *node)
+{
+ ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_left);
+ ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_right);
+ return gen_shift_binop(node, left, right, new_rd_ia32_Shr,
+ match_immediate);
+}
-#define GEN_LOWERED_UNOP(op) \
- static ir_node *gen_ia32_l_##op(ir_node *node) {\
- return gen_unop(node, get_unop_op(node), new_rd_ia32_##op); \
- }
+static ir_node *gen_ia32_l_SarDep(ir_node *node)
+{
+ ir_node *left = get_irn_n(node, n_ia32_l_SarDep_left);
+ ir_node *right = get_irn_n(node, n_ia32_l_SarDep_right);
+ return gen_shift_binop(node, left, right, new_rd_ia32_Sar,
+ match_immediate);
+}
-#define GEN_LOWERED_SHIFT_OP(l_op, op) \
- static ir_node *gen_ia32_##l_op(ir_node *node) { \
- return gen_shift_binop(node, get_irn_n(node, 0), \
- get_irn_n(node, 1), new_rd_ia32_##op); \
- }
+static ir_node *gen_ia32_l_Add(ir_node *node) {
+ ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
+ ir_node *right = get_irn_n(node, n_ia32_l_Add_right);
+ ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Add,
+ match_commutative | match_am | match_immediate |
+ match_mode_neutral);
-#define GEN_LOWERED_LOAD(op) \
- static ir_node *gen_ia32_l_##op(ir_node *node) { \
- return gen_lowered_Load(node, new_rd_ia32_##op); \
+ if(is_Proj(lowered)) {
+ lowered = get_Proj_pred(lowered);
+ } else {
+ assert(is_ia32_Add(lowered));
+ set_irn_mode(lowered, mode_T);
}
-#define GEN_LOWERED_STORE(op) \
- static ir_node *gen_ia32_l_##op(ir_node *node) { \
- return gen_lowered_Store(node, new_rd_ia32_##op); \
- }
+ return lowered;
+}
+
+static ir_node *gen_ia32_l_Adc(ir_node *node)
+{
+ return gen_binop_flags(node, new_rd_ia32_Adc,
+ match_commutative | match_am | match_immediate |
+ match_mode_neutral);
+}
-GEN_LOWERED_OP(Adc)
-GEN_LOWERED_OP(Add)
-GEN_LOWERED_OP(Sbb)
-GEN_LOWERED_OP(Sub)
-GEN_LOWERED_OP(IMul)
-GEN_LOWERED_OP(Xor)
-GEN_LOWERED_x87_OP(vfprem)
-GEN_LOWERED_x87_OP(vfmul)
-GEN_LOWERED_x87_OP(vfsub)
+/**
+ * Transforms an ia32_l_vfild into a "real" ia32_vfild node
+ *
+ * @param node The node to transform
+ * @return the created ia32 vfild node
+ */
+static ir_node *gen_ia32_l_vfild(ir_node *node) {
+ return gen_lowered_Load(node, new_rd_ia32_vfild);
+}
-GEN_LOWERED_UNOP(Neg)
+/**
+ * Transforms an ia32_l_Load into a "real" ia32_Load node
+ *
+ * @param node The node to transform
+ * @return the created ia32 Load node
+ */
+static ir_node *gen_ia32_l_Load(ir_node *node) {
+ return gen_lowered_Load(node, new_rd_ia32_Load);
+}
-GEN_LOWERED_LOAD(vfild)
-GEN_LOWERED_LOAD(Load)
-GEN_LOWERED_STORE(Store)
+/**
+ * Transforms an ia32_l_Store into a "real" ia32_Store node
+ *
+ * @param node The node to transform
+ * @return the created ia32 Store node
+ */
+static ir_node *gen_ia32_l_Store(ir_node *node) {
+ return gen_lowered_Store(node, new_rd_ia32_Store);
+}
/**
* Transforms a l_vfist into a "real" vfist node.
*
- * @param env The transformation environment
+ * @param node The node to transform
* @return the created ia32 vfist node
*/
static ir_node *gen_ia32_l_vfist(ir_node *node) {
ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
ir_node *new_op;
long am_offs;
- ia32_am_flavour_t am_flav = ia32_B;
- new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_val, trunc_mode, new_mem);
+ new_op = new_rd_ia32_vfist(dbgi, irg, block, new_ptr, noreg, new_mem,
+ new_val, trunc_mode);
- if ((am_offs = get_ia32_am_offs_int(node)) != 0) {
- am_flav |= ia32_O;
- add_ia32_am_offs_int(new_op, am_offs);
- }
+ am_offs = get_ia32_am_offs_int(node);
+ add_ia32_am_offs_int(new_op, am_offs);
set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, am_flav);
set_ia32_ls_mode(new_op, mode);
set_ia32_frame_ent(new_op, get_ia32_frame_ent(node));
set_ia32_use_frame(new_op);
}
/**
- * Transforms a l_vfdiv into a "real" vfdiv node.
+ * Transforms a l_MulS into a "real" MulS node.
*
- * @param env The transformation environment
- * @return the created ia32 vfdiv node
+ * @return the created ia32 Mul node
*/
-static ir_node *gen_ia32_l_vfdiv(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *left = get_binop_left(node);
- ir_node *new_left = be_transform_node(left);
- ir_node *right = get_binop_right(node);
- ir_node *new_right = be_transform_node(right);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *fpcw = get_fpcw();
- ir_node *vfdiv;
-
- vfdiv = new_rd_ia32_vfdiv(dbgi, irg, block, noreg, noreg, new_left,
- new_right, new_NoMem(), fpcw);
- clear_ia32_commutative(vfdiv);
- set_ia32_am_support(vfdiv, ia32_am_Source, ia32_am_binary);
-
- SET_IA32_ORIG_NODE(vfdiv, ia32_get_old_node_name(env_cg, node));
+static ir_node *gen_ia32_l_Mul(ir_node *node) {
+ ir_node *left = get_binop_left(node);
+ ir_node *right = get_binop_right(node);
- return vfdiv;
+ return gen_binop(node, left, right, new_rd_ia32_Mul,
+ match_commutative | match_am | match_mode_neutral);
}
/**
- * Transforms a l_MulS into a "real" MulS node.
+ * Transforms a l_IMulS into a "real" IMul1OPS node.
*
- * @param env The transformation environment
- * @return the created ia32 Mul node
+ * @return the created ia32 IMul1OP node
*/
-static ir_node *gen_ia32_l_Mul(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
+static ir_node *gen_ia32_l_IMul(ir_node *node) {
ir_node *left = get_binop_left(node);
- ir_node *new_left = be_transform_node(left);
ir_node *right = get_binop_right(node);
- ir_node *new_right = be_transform_node(right);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
- /* and then skip the result Proj, because all needed Projs are already there. */
- ir_node *muls = new_rd_ia32_Mul(dbgi, irg, block, noreg, noreg, new_left,
- new_right, new_NoMem());
- clear_ia32_commutative(muls);
- set_ia32_am_support(muls, ia32_am_Source, ia32_am_binary);
+ return gen_binop(node, left, right, new_rd_ia32_IMul1OP,
+ match_commutative | match_am | match_mode_neutral);
+}
+
+static ir_node *gen_ia32_l_Sub(ir_node *node) {
+ ir_node *left = get_irn_n(node, n_ia32_l_Sub_left);
+ ir_node *right = get_irn_n(node, n_ia32_l_Sub_right);
+ ir_node *lowered = gen_binop(node, left, right, new_rd_ia32_Sub,
+ match_am | match_immediate | match_mode_neutral);
- SET_IA32_ORIG_NODE(muls, ia32_get_old_node_name(env_cg, node));
+ if(is_Proj(lowered)) {
+ lowered = get_Proj_pred(lowered);
+ } else {
+ assert(is_ia32_Sub(lowered));
+ set_irn_mode(lowered, mode_T);
+ }
- return muls;
+ return lowered;
}
-GEN_LOWERED_SHIFT_OP(l_ShlDep, Shl)
-GEN_LOWERED_SHIFT_OP(l_ShrDep, Shr)
-GEN_LOWERED_SHIFT_OP(l_Sar, Sar)
-GEN_LOWERED_SHIFT_OP(l_SarDep, Sar)
+static ir_node *gen_ia32_l_Sbb(ir_node *node) {
+ return gen_binop_flags(node, new_rd_ia32_Sbb,
+ match_am | match_immediate | match_mode_neutral);
+}
/**
* Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
* op3 - shift count
* Only op3 can be an immediate.
*/
-static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *op1,
- ir_node *op2, ir_node *count)
+static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
+ ir_node *low, ir_node *count)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_op1 = be_transform_node(op1);
- ir_node *new_op2 = be_transform_node(op2);
- ir_node *new_op = NULL;
- ir_node *new_count = be_transform_node(count);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *noreg = ia32_new_NoReg_gp(env_cg);
- ir_node *nomem = new_NoMem();
- ir_node *imm_op;
- tarval *tv;
-
- assert(! mode_is_float(get_irn_mode(node)) && "Shift/Rotate with float not supported");
-
- /* Check if immediate optimization is on and */
- /* if it's an operation with immediate. */
- imm_op = (env_cg->opt & IA32_OPT_IMMOPS) ? get_immediate_op(NULL, new_count) : NULL;
-
- /* Limit imm_op within range imm8 */
- if (imm_op) {
- tv = get_ia32_Immop_tarval(imm_op);
+ ir_node *new_high = be_transform_node(high);
+ ir_node *new_low = be_transform_node(low);
+ ir_node *new_count;
+ ir_node *new_node;
- if (tv) {
- tv = tarval_mod(tv, new_tarval_from_long(32, get_tarval_mode(tv)));
- set_ia32_Immop_tarval(imm_op, tv);
- }
- else {
- imm_op = NULL;
- }
+ /* the shift amount can be any mode that is bigger than 5 bits, since all
+ * other bits are ignored anyway */
+ while (is_Conv(count) && get_irn_n_edges(count) == 1) {
+ assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
+ count = get_Conv_op(count);
}
+ new_count = create_immediate_or_transform(count, 0);
- /* integer operations */
- if (imm_op) {
- /* This is ShiftD with const */
- DB((dbg, LEVEL_1, "ShiftD with immediate ..."));
-
- if (is_ia32_l_ShlD(node))
- new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
- new_op1, new_op2, noreg, nomem);
- else
- new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
- new_op1, new_op2, noreg, nomem);
- copy_ia32_Immop_attr(new_op, imm_op);
- }
- else {
- /* This is a normal ShiftD */
- DB((dbg, LEVEL_1, "ShiftD binop ..."));
- if (is_ia32_l_ShlD(node))
- new_op = new_rd_ia32_ShlD(dbgi, irg, block, noreg, noreg,
- new_op1, new_op2, new_count, nomem);
- else
- new_op = new_rd_ia32_ShrD(dbgi, irg, block, noreg, noreg,
- new_op1, new_op2, new_count, nomem);
+ if (is_ia32_l_ShlD(node)) {
+ new_node = new_rd_ia32_ShlD(dbgi, irg, new_block, new_high, new_low,
+ new_count);
+ } else {
+ new_node = new_rd_ia32_ShrD(dbgi, irg, new_block, new_high, new_low,
+ new_count);
}
+ SET_IA32_ORIG_NODE(new_node, ia32_get_old_node_name(env_cg, node));
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Dest, ia32_am_binary);
-
- SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env_cg, node));
-
- set_ia32_emit_cl(new_op);
-
- return new_op;
+ return new_node;
}
-static ir_node *gen_ia32_l_ShlD(ir_node *node) {
- return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
- get_irn_n(node, 1), get_irn_n(node, 2));
+static ir_node *gen_ia32_l_ShlD(ir_node *node)
+{
+ ir_node *high = get_irn_n(node, n_ia32_l_ShlD_high);
+ ir_node *low = get_irn_n(node, n_ia32_l_ShlD_low);
+ ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
+ return gen_lowered_64bit_shifts(node, high, low, count);
}
-static ir_node *gen_ia32_l_ShrD(ir_node *node) {
- return gen_lowered_64bit_shifts(node, get_irn_n(node, 0),
- get_irn_n(node, 1), get_irn_n(node, 2));
+static ir_node *gen_ia32_l_ShrD(ir_node *node)
+{
+ ir_node *high = get_irn_n(node, n_ia32_l_ShrD_high);
+ ir_node *low = get_irn_n(node, n_ia32_l_ShrD_low);
+ ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
+ return gen_lowered_64bit_shifts(node, high, low, count);
}
/**
dbgi = get_irn_dbg_info(node);
/* Store x87 -> MEM */
- res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_val, new_mem, get_ia32_ls_mode(node));
+ res = new_rd_ia32_vfst(dbgi, irg, block, new_ptr, noreg, new_mem, new_val,
+ get_ia32_ls_mode(node));
set_ia32_frame_ent(res, get_ia32_frame_ent(node));
set_ia32_use_frame(res);
set_ia32_ls_mode(res, get_ia32_ls_mode(node));
- set_ia32_am_flavour(res, ia32_B);
set_ia32_op_type(res, ia32_AddrModeD);
/* Load MEM -> SSE */
- res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res);
+ res = new_rd_ia32_xLoad(dbgi, irg, block, new_ptr, noreg, res,
+ get_ia32_ls_mode(node));
set_ia32_frame_ent(res, get_ia32_frame_ent(node));
set_ia32_use_frame(res);
- set_ia32_ls_mode(res, get_ia32_ls_mode(node));
- set_ia32_am_flavour(res, ia32_B);
set_ia32_op_type(res, ia32_AddrModeS);
res = new_rd_Proj(dbgi, irg, block, res, mode_xmm, pn_ia32_xLoad_res);
ptr = get_irn_n(ld, 0);
offs = get_ia32_am_offs_int(ld);
} else {
- res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_val, new_mem);
+ res = new_rd_ia32_xStore(dbgi, irg, block, new_ptr, noreg, new_mem,
+ new_val);
set_ia32_frame_ent(res, fent);
set_ia32_use_frame(res);
set_ia32_ls_mode(res, lsmode);
- set_ia32_am_flavour(res, ia32_B);
set_ia32_op_type(res, ia32_AddrModeD);
mem = res;
}
set_ia32_frame_ent(res, fent);
set_ia32_use_frame(res);
add_ia32_am_offs_int(res, offs);
- set_ia32_am_flavour(res, ia32_B);
set_ia32_op_type(res, ia32_AddrModeS);
res = new_rd_Proj(dbgi, irg, block, res, mode_vfp, pn_ia32_vfld_res);
* Transform and renumber the Projs from a Load.
*/
static ir_node *gen_Proj_Load(ir_node *node) {
+ ir_node *new_pred;
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
- ir_node *new_pred = be_transform_node(pred);
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
+
+ /* loads might be part of source address mode matches, so we don't
+ transform the ProjMs yet (with the exception of loads whose result is
+ not used)
+ */
+ if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
+ ir_node *res;
+
+ assert(pn_ia32_Load_M == 1); /* convention: mem-result of Source-AM
+ nodes is 1 */
+ /* this is needed, because sometimes we have loops that are only
+ reachable through the ProjM */
+ be_enqueue_preds(node);
+ /* do it in 2 steps, to silence firm verifier */
+ res = new_rd_Proj(dbgi, irg, block, pred, mode_M, pn_Load_M);
+ set_Proj_proj(res, pn_ia32_Load_M);
+ return res;
+ }
+
/* renumber the proj */
+ new_pred = be_transform_node(pred);
if (is_ia32_Load(new_pred)) {
if (proj == pn_Load_res) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_Load_res);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu,
+ pn_ia32_Load_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_Load_M);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
+ pn_ia32_Load_M);
}
- } else if(is_ia32_Conv_I2I(new_pred)) {
+ } else if(is_ia32_Conv_I2I(new_pred)
+ || is_ia32_Conv_I2I8Bit(new_pred)) {
set_irn_mode(new_pred, mode_T);
if (proj == pn_Load_res) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, 0);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_Iu, pn_ia32_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_mem);
}
} else if (is_ia32_xLoad(new_pred)) {
if (proj == pn_Load_res) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_xmm,
+ pn_ia32_xLoad_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
+ pn_ia32_xLoad_M);
}
} else if (is_ia32_vfld(new_pred)) {
if (proj == pn_Load_res) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfld_res);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp,
+ pn_ia32_vfld_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M,
+ pn_ia32_vfld_M);
+ }
+ } else {
+ /* can happen for ProJMs when source address mode happened for the
+ node */
+
+ /* however it should not be the result proj, as that would mean the
+ load had multiple users and should not have been used for
+ SourceAM */
+ if(proj != pn_Load_M) {
+ panic("internal error: transformed node not a Load");
}
+ return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, 1);
}
assert(0);
return new_rd_Unknown(irg, mode);
}
-/**
- * Transform and renumber the Projs from a vfdiv.
- */
-static ir_node *gen_Proj_l_vfdiv(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *pred = get_Proj_pred(node);
- ir_node *new_pred = be_transform_node(pred);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- long proj = get_Proj_proj(node);
-
- switch (proj) {
- case pn_ia32_l_vfdiv_M:
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
- case pn_ia32_l_vfdiv_res:
- return new_rd_Proj(dbgi, irg, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
- default:
- assert(0);
- }
-
- return new_rd_Unknown(irg, mode);
-}
-
/**
* Transform and renumber the Projs from a Quot.
*/
return res;
}
+static ir_node *gen_be_Call(ir_node *node) {
+ ir_node *res = be_duplicate_node(node);
+ be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
+
+ return res;
+}
+
+static ir_node *gen_be_IncSP(ir_node *node) {
+ ir_node *res = be_duplicate_node(node);
+ be_node_add_flags(res, -1, arch_irn_flags_modify_flags);
+
+ return res;
+}
+
/**
* Transform the Projs from a be_Call.
*/
static ir_node *gen_Proj_be_Call(ir_node *node) {
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *call = get_Proj_pred(node);
- ir_node *new_call = be_transform_node(call);
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- long proj = get_Proj_proj(node);
- ir_mode *mode = get_irn_mode(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *call = get_Proj_pred(node);
+ ir_node *new_call = be_transform_node(call);
+ ir_graph *irg = current_ir_graph;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_type *method_type = be_Call_get_type(call);
+ int n_res = get_method_n_ress(method_type);
+ long proj = get_Proj_proj(node);
+ ir_mode *mode = get_irn_mode(node);
ir_node *sse_load;
const arch_register_class_t *cls;
pn_ia32_xLoad_M);
}
}
- if (proj == pn_be_Call_first_res && mode_is_float(mode) && USE_SSE2(env_cg)) {
+ if (USE_SSE2(env_cg) && proj >= pn_be_Call_first_res
+ && proj < (pn_be_Call_first_res + n_res) && mode_is_float(mode)
+ && USE_SSE2(env_cg)) {
ir_node *fstp;
ir_node *frame = get_irg_frame(irg);
ir_node *noreg = ia32_new_NoReg_gp(env_cg);
call_res, mode);
set_ia32_op_type(fstp, ia32_AddrModeD);
set_ia32_use_frame(fstp);
- set_ia32_am_flavour(fstp, ia32_am_B);
/* load into SSE register */
- sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp);
- set_ia32_ls_mode(sse_load, mode);
+ sse_load = new_rd_ia32_xLoad(dbgi, irg, block, frame, noreg, fstp,
+ mode);
set_ia32_op_type(sse_load, ia32_AddrModeS);
set_ia32_use_frame(sse_load);
- set_ia32_am_flavour(sse_load, ia32_am_B);
sse_load = new_rd_Proj(dbgi, irg, block, sse_load, mode_xmm,
pn_ia32_xLoad_res);
-#if 0
- /* now: create new Keep whith all former ins and one additional in - the result Proj */
-
- /* get a Proj representing a caller save register */
- p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
- assert(is_Proj(p) && "Proj expected.");
-
- /* user of the the proj is the Keep */
- p = get_edge_src_irn(get_irn_out_edge_first(p));
- assert(be_is_Keep(p) && "Keep expected.");
-#endif
-
return sse_load;
}
/* transform call modes */
if (mode_is_data(mode)) {
- cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
+ cls = arch_get_irn_reg_class(env_cg->arch_env, node, -1);
mode = cls->mode;
}
*/
static ir_node *gen_Proj_Cmp(ir_node *node)
{
+ (void) node;
+ panic("not all mode_b nodes are lowered");
+
+#if 0
/* normally Cmps are processed when looking at Cond nodes, but this case
* can happen in complicated Psi conditions */
-
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
ir_node *cmp = get_Proj_pred(node);
+ ir_node *new_cmp = be_transform_node(cmp);
long pnc = get_Proj_proj(node);
- ir_node *cmp_left = get_Cmp_left(cmp);
- ir_node *cmp_right = get_Cmp_right(cmp);
- ir_mode *cmp_mode = get_irn_mode(cmp_left);
- dbg_info *dbgi = get_irn_dbg_info(cmp);
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *res;
- assert(!mode_is_float(cmp_mode));
-
- if(!mode_is_signed(cmp_mode)) {
- pnc |= ia32_pn_Cmp_Unsigned;
- }
-
- res = create_set(pnc, cmp_left, cmp_right, dbgi, block);
- SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env_cg, cmp));
+ res = create_set_32bit(dbgi, new_block, new_cmp, pnc, node, 0);
return res;
+#endif
}
/**
ir_node *pred = get_Proj_pred(node);
long proj = get_Proj_proj(node);
- if (is_Store(pred) || be_is_FrameStore(pred)) {
+ if (is_Store(pred)) {
if (proj == pn_Store_M) {
return be_transform_node(pred);
} else {
assert(0);
return new_r_Bad(irg);
}
- } else if (is_Load(pred) || be_is_FrameLoad(pred)) {
+ } else if (is_Load(pred)) {
return gen_Proj_Load(node);
} else if (is_Div(pred) || is_Mod(pred) || is_DivMod(pred)) {
return gen_Proj_DivMod(node);
return gen_Proj_CopyB(node);
} else if (is_Quot(pred)) {
return gen_Proj_Quot(node);
- } else if (is_ia32_l_vfdiv(pred)) {
- return gen_Proj_l_vfdiv(node);
} else if (be_is_SubSP(pred)) {
return gen_Proj_be_SubSP(node);
} else if (be_is_AddSP(pred)) {
GEN(Store);
GEN(Cond);
+ GEN(Cmp);
GEN(ASM);
GEN(CopyB);
BAD(Mux);
/* transform ops from intrinsic lowering */
GEN(ia32_l_Add);
GEN(ia32_l_Adc);
- GEN(ia32_l_Sub);
- GEN(ia32_l_Sbb);
- GEN(ia32_l_Neg);
GEN(ia32_l_Mul);
- GEN(ia32_l_Xor);
GEN(ia32_l_IMul);
GEN(ia32_l_ShlDep);
GEN(ia32_l_ShrDep);
- GEN(ia32_l_Sar);
GEN(ia32_l_SarDep);
GEN(ia32_l_ShlD);
GEN(ia32_l_ShrD);
- GEN(ia32_l_vfdiv);
- GEN(ia32_l_vfprem);
- GEN(ia32_l_vfmul);
- GEN(ia32_l_vfsub);
+ GEN(ia32_l_Sub);
+ GEN(ia32_l_Sbb);
GEN(ia32_l_vfild);
GEN(ia32_l_Load);
GEN(ia32_l_vfist);
GEN(Const);
GEN(SymConst);
+ GEN(Unknown);
/* we should never see these nodes */
BAD(Raise);
/* handle generic backend nodes */
GEN(be_FrameAddr);
- //GEN(be_Call);
+ GEN(be_Call);
+ GEN(be_IncSP);
GEN(be_Return);
- GEN(be_FrameLoad);
- GEN(be_FrameStore);
- GEN(be_StackParam);
GEN(be_AddSP);
GEN(be_SubSP);
GEN(be_Copy);
- /* set the register for all Unknown nodes */
- GEN(Unknown);
-
op_Mulh = get_op_Mulh();
if (op_Mulh)
GEN(Mulh);
* Walker, checks if all ia32 nodes producing more than one result have
* its Projs, other wise creates new projs and keep them using a be_Keep node.
*/
-static
-void add_missing_keep_walker(ir_node *node, void *data)
+static void add_missing_keep_walker(ir_node *node, void *data)
{
int n_outs, i;
unsigned found_projs = 0;
ir_node *proj = get_edge_src_irn(edge);
int pn = get_Proj_proj(proj);
- assert(pn < n_outs);
+ assert(get_irn_mode(proj) == mode_M || pn < n_outs);
found_projs |= 1 << pn;
}
if(class == NULL) {
continue;
}
+ if(class == &ia32_reg_classes[CLASS_ia32_flags]) {
+ continue;
+ }
block = get_nodes_block(node);
in[0] = new_r_Proj(current_ir_graph, block, node,
be_Keep_add_node(last_keep, class, in[0]);
} else {
last_keep = be_new_Keep(class, current_ir_graph, block, 1, in);
+ if(sched_is_scheduled(node)) {
+ sched_add_after(node, last_keep);
+ }
}
}
}
* Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
* and keeps them.
*/
-static
-void add_missing_keeps(ia32_code_gen_t *cg)
+void ia32_add_missing_keeps(ia32_code_gen_t *cg)
{
ir_graph *irg = be_get_birg_irg(cg->birg);
irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
/* do the transformation */
void ia32_transform_graph(ia32_code_gen_t *cg) {
+ int cse_last;
+ ir_graph *irg = cg->irg;
+ int opt_arch = cg->isa->opt_arch;
+ int arch = cg->isa->arch;
+
+ /* TODO: look at cpu and fill transform config in with that... */
+ transform_config.use_incdec = 1;
+ transform_config.use_sse2 = 0;
+ transform_config.use_ffreep = ARCH_ATHLON(opt_arch);
+ transform_config.use_ftst = 0;
+ transform_config.use_femms = ARCH_ATHLON(opt_arch) && ARCH_MMX(arch) && ARCH_AMD(arch);
+ transform_config.use_fucomi = 1;
+ transform_config.use_cmov = IS_P6_ARCH(arch);
+
register_transformers();
- env_cg = cg;
+ env_cg = cg;
initial_fpcw = NULL;
+
+ heights = heights_new(irg);
+ ia32_calculate_non_address_mode_nodes(irg);
+
+ /* the transform phase is not safe for CSE (yet) because several nodes get
+ * attributes set after their creation */
+ cse_last = get_opt_cse();
+ set_opt_cse(0);
+
be_transform_graph(cg->birg, ia32_pretransform_node, cg);
- edges_verify(cg->irg);
- add_missing_keeps(cg);
- edges_verify(cg->irg);
+
+ set_opt_cse(cse_last);
+
+ ia32_free_non_address_mode_nodes();
+ heights_free(heights);
+ heights = NULL;
}
void ia32_init_transform(void)
projects / libfirm / blobdiff