#include "config.h"
#endif
+#include <limits.h>
+
#include "irargs_t.h"
#include "irnode_t.h"
#include "irgraph_t.h"
#include "gen_ia32_regalloc_if.h"
-#ifdef NDEBUG
-#define SET_IA32_ORIG_NODE(n, o)
-#else
-#define SET_IA32_ORIG_NODE(n, o) set_ia32_orig_node(n, o);
-#endif /* NDEBUG */
-
-
#define SFP_SIGN "0x80000000"
#define DFP_SIGN "0x8000000000000000"
#define SFP_ABS "0x7FFFFFFF"
/**
* Prints the old node name on cg obst and returns a pointer to it.
*/
-const char *get_old_node_name(ia32_transform_env_t *env) {
- ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
+const char *ia32_get_old_node_name(ia32_code_gen_t *cg, ir_node *irn) {
+ ia32_isa_t *isa = (ia32_isa_t *)cg->arch_env->isa;
- lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
+ lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", irn);
obstack_1grow(isa->name_obst, 0);
isa->name_obst_size += obstack_object_size(isa->name_obst);
return obstack_finish(isa->name_obst);
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
- firm_dbg_module_t *mod = env->mod;
ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* Check if immediate optimization is on and */
/* if it's an operation with immediate. */
}
}
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, mode);
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
- firm_dbg_module_t *mod = env->mod;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_NoMem();
ir_node *expr_op, *imm_op;
tarval *tv;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
assert(! mode_is_float(mode) && "Shift/Rotate with float not supported");
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Dest);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, mode);
+ set_ia32_emit_cl(new_op);
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
ir_node *new_op = NULL;
ir_mode *mode = env->mode;
dbg_info *dbg = env->dbg;
- firm_dbg_module_t *mod = env->mod;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_NoMem();
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
new_op = func(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
set_ia32_am_support(new_op, ia32_am_Dest);
}
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, mode);
static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
ir_node *new_op = NULL;
tarval *tv = get_ia32_Immop_tarval(const_op);
- firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *nomem = new_NoMem();
int normal_add = 1;
tarval_classification_t class_tv, class_negtv;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
if (env->cg->opt.incdec && tv) {
assert((expr_op || imm_op) && "invalid operands");
if (mode_is_float(mode)) {
- return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ return gen_binop(env, op1, op2, new_rd_ia32_fAdd);
+ else
+ return gen_binop(env, op1, op2, new_rd_ia32_vfadd);
}
else {
/* integer ADD */
/* No expr_op means, that we have two const - one symconst and */
/* one tarval or another symconst - because this case is not */
/* covered by constant folding */
+ /* We need to check for: */
+ /* 1) symconst + const -> becomes a LEA */
+ /* 2) symconst + symconst -> becomes a const + LEA as the elf */
+ /* linker doesn't support two symconsts */
+
+ if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
+ /* this is the 2nd case */
+ new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
+ set_ia32_am_flavour(new_op, ia32_am_OB);
+ }
+ else {
+ /* this is the 1st case */
+ new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- add_ia32_am_offs(new_op, get_ia32_cnst(op1));
- add_ia32_am_offs(new_op, get_ia32_cnst(op2));
+ if (get_ia32_op_type(op1) == ia32_SymConst) {
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
+ add_ia32_am_offs(new_op, get_ia32_cnst(op2));
+ }
+ else {
+ add_ia32_am_offs(new_op, get_ia32_cnst(op1));
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
+ }
+ set_ia32_am_flavour(new_op, ia32_am_O);
+ }
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_O);
/* Lea doesn't need a Proj */
return new_op;
}
}
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, mode);
ir_node *new_op;
if (mode_is_float(env->mode)) {
- new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = gen_binop(env, op1, op2, new_rd_ia32_fMul);
+ else
+ new_op = gen_binop(env, op1, op2, new_rd_ia32_vfmul);
}
else {
new_op = gen_binop(env, op1, op2, new_rd_ia32_Mul);
* @return The created ia32 And node
*/
static ir_node *gen_And(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- if (mode_is_float(env->mode)) {
- return gen_binop(env, op1, op2, new_rd_ia32_fAnd);
- }
- else {
- return gen_binop(env, op1, op2, new_rd_ia32_And);
- }
+ assert (! mode_is_float(env->mode));
+ return gen_binop(env, op1, op2, new_rd_ia32_And);
}
* @return The created ia32 Or node
*/
static ir_node *gen_Or(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- if (mode_is_float(env->mode)) {
- return gen_binop(env, op1, op2, new_rd_ia32_fOr);
- }
- else {
- return gen_binop(env, op1, op2, new_rd_ia32_Or);
- }
+ assert (! mode_is_float(env->mode));
+ return gen_binop(env, op1, op2, new_rd_ia32_Or);
}
* @return The created ia32 Eor node
*/
static ir_node *gen_Eor(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
- if (mode_is_float(env->mode)) {
- return gen_binop(env, op1, op2, new_rd_ia32_fEor);
- }
- else {
- return gen_binop(env, op1, op2, new_rd_ia32_Eor);
- }
+ assert(! mode_is_float(env->mode));
+ return gen_binop(env, op1, op2, new_rd_ia32_Eor);
}
ir_node *new_op;
if (mode_is_float(env->mode)) {
- new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = gen_binop(env, op1, op2, new_rd_ia32_fMax);
+ else {
+ assert(0);
+ }
}
else {
new_op = new_rd_ia32_Max(env->dbg, env->irg, env->block, op1, op2, env->mode);
set_ia32_am_support(new_op, ia32_am_None);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
}
return new_op;
ir_node *new_op;
if (mode_is_float(env->mode)) {
- new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = gen_binop(env, op1, op2, new_rd_ia32_fMin);
+ else {
+ assert(0);
+ }
}
else {
new_op = new_rd_ia32_Min(env->dbg, env->irg, env->block, op1, op2, env->mode);
set_ia32_am_support(new_op, ia32_am_None);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
}
return new_op;
static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *expr_op, ir_node *const_op) {
ir_node *new_op = NULL;
tarval *tv = get_ia32_Immop_tarval(const_op);
- firm_dbg_module_t *mod = env->mod;
dbg_info *dbg = env->dbg;
ir_graph *irg = env->irg;
ir_node *block = env->block;
ir_node *nomem = new_NoMem();
int normal_sub = 1;
tarval_classification_t class_tv, class_negtv;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
if (env->cg->opt.incdec && tv) {
assert((expr_op || imm_op) && "invalid operands");
if (mode_is_float(mode)) {
- return gen_binop(env, op1, op2, new_rd_ia32_fSub);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ return gen_binop(env, op1, op2, new_rd_ia32_fSub);
+ else
+ return gen_binop(env, op1, op2, new_rd_ia32_vfsub);
}
else {
/* integer SUB */
/* No expr_op means, that we have two const - one symconst and */
/* one tarval or another symconst - because this case is not */
/* covered by constant folding */
+ /* We need to check for: */
+ /* 1) symconst + const -> becomes a LEA */
+ /* 2) symconst + symconst -> becomes a const + LEA as the elf */
+ /* linker doesn't support two symconsts */
+
+ if (get_ia32_op_type(op1) == ia32_SymConst && get_ia32_op_type(op2) == ia32_SymConst) {
+ /* this is the 2nd case */
+ new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
+ set_ia32_am_sc_sign(new_op);
+ set_ia32_am_flavour(new_op, ia32_am_OB);
+ }
+ else {
+ /* this is the 1st case */
+ new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
- add_ia32_am_offs(new_op, get_ia32_cnst(op1));
- sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
+ if (get_ia32_op_type(op1) == ia32_SymConst) {
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
+ sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
+ }
+ else {
+ add_ia32_am_offs(new_op, get_ia32_cnst(op1));
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
+ set_ia32_am_sc_sign(new_op);
+ }
+ set_ia32_am_flavour(new_op, ia32_am_O);
+ }
/* set AM support */
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_am_O);
/* Lea doesn't need a Proj */
return new_op;
}
}
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(new_op, mode);
be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in_keep);
}
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode_Is);
*/
static ir_node *gen_Quot(ia32_transform_env_t *env, ir_node *op1, ir_node *op2) {
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *nomem = new_rd_NoMem(env->irg);
ir_node *new_op;
+ ir_node *nomem = new_rd_NoMem(env->irg);
- if (is_ia32_fConst(op2)) {
- new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
- set_ia32_am_support(new_op, ia32_am_None);
- set_ia32_Immop_attr(new_op, op2);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg)) {
+ if (is_ia32_fConst(op2)) {
+ new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, noreg, nomem, mode_T);
+ set_ia32_am_support(new_op, ia32_am_None);
+ set_ia32_Immop_attr(new_op, op2);
+ }
+ else {
+ new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ }
}
else {
- new_op = new_rd_ia32_fDiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
+ new_op = new_rd_ia32_vfdiv(env->dbg, env->irg, env->block, noreg, noreg, op1, op2, nomem, mode_T);
set_ia32_am_support(new_op, ia32_am_Source);
}
set_ia32_res_mode(new_op, get_irn_mode(get_proj_for_pn(env->irn, pn_Quot_res)));
-
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
}
int size;
if (mode_is_float(env->mode)) {
- new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg)) {
+ new_op = new_rd_ia32_fEor(env->dbg, env->irg, env->block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
- size = get_mode_size_bits(env->mode);
- name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
+ size = get_mode_size_bits(env->mode);
+ name = gen_fp_known_const(env->mode, size == 32 ? ia32_SSIGN : ia32_DSIGN);
- set_ia32_sc(new_op, name);
+ set_ia32_sc(new_op, name);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
- set_ia32_res_mode(new_op, env->mode);
- set_ia32_immop_type(new_op, ia32_ImmSymConst);
+ set_ia32_res_mode(new_op, env->mode);
+ set_ia32_immop_type(new_op, ia32_ImmSymConst);
- new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
+ new_op = new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
+ }
+ else {
+ new_op = new_rd_ia32_vfchs(env->dbg, env->irg, env->block, op, env->mode);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+ }
}
else {
new_op = gen_unop(env, op, new_rd_ia32_Minus);
* @return The created ia32 Not node
*/
static ir_node *gen_Not(ia32_transform_env_t *env, ir_node *op) {
- ir_node *new_op;
-
- if (mode_is_float(env->mode)) {
- assert(0);
- }
- else {
- new_op = gen_unop(env, op, new_rd_ia32_Not);
- }
-
- return new_op;
+ assert (! mode_is_float(env->mode));
+ return gen_unop(env, op, new_rd_ia32_Not);
}
ident *name;
if (mode_is_float(mode)) {
- res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg)) {
+ res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
- size = get_mode_size_bits(mode);
- name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
+ size = get_mode_size_bits(mode);
+ name = gen_fp_known_const(mode, size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_sc(res, name);
+ set_ia32_sc(res, name);
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
- set_ia32_res_mode(res, mode);
- set_ia32_immop_type(res, ia32_ImmSymConst);
+ set_ia32_res_mode(res, mode);
+ set_ia32_immop_type(res, ia32_ImmSymConst);
- res = new_rd_Proj(dbg, irg, block, res, mode, 0);
+ res = new_rd_Proj(dbg, irg, block, res, mode, 0);
+ }
+ else {
+ res = new_rd_ia32_vfabs(dbg, irg, block, op, mode);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
+ }
}
else {
res = new_rd_ia32_Cdq(dbg, irg, block, op, mode_T);
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
p_eax = new_rd_Proj(dbg, irg, block, res, mode, pn_EAX);
p_edx = new_rd_Proj(dbg, irg, block, res, mode, pn_EDX);
res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem, mode_T);
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem, mode_T);
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_res_mode(res, mode);
res = new_rd_Proj(dbg, irg, block, res, mode, 0);
* @return the created ia32 Load node
*/
static ir_node *gen_Load(ia32_transform_env_t *env) {
- ir_node *node = env->irn;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_mode *mode = get_Load_mode(node);
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *ptr = get_Load_ptr(node);
+ ir_node *lptr = ptr;
+ ir_mode *mode = get_Load_mode(node);
+ int is_imm = 0;
ir_node *new_op;
+ ia32_am_flavour_t am_flav = ia32_B;
+
+ /* address might be a constant (symconst or absolute address) */
+ if (is_ia32_Const(ptr)) {
+ lptr = noreg;
+ is_imm = 1;
+ }
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ else
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
}
else {
- new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, get_Load_ptr(node), noreg, get_Load_mem(node), env->mode);
+ new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, lptr, noreg, get_Load_mem(node), env->mode);
+ }
+
+ /* base is an constant address */
+ if (is_imm) {
+ if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
+ }
+ else {
+ add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
+ }
+
+ am_flav = ia32_O;
}
set_ia32_am_support(new_op, ia32_am_Source);
set_ia32_op_type(new_op, ia32_AddrModeS);
- set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_am_flavour(new_op, am_flav);
set_ia32_ls_mode(new_op, mode);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
}
* @return the created ia32 Store node
*/
static ir_node *gen_Store(ia32_transform_env_t *env) {
- ir_node *node = env->irn;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *val = get_Store_value(node);
- ir_node *ptr = get_Store_ptr(node);
- ir_node *mem = get_Store_mem(node);
- ir_mode *mode = get_irn_mode(val);
- ir_node *sval = val;
+ ir_node *node = env->irn;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *val = get_Store_value(node);
+ ir_node *ptr = get_Store_ptr(node);
+ ir_node *sptr = ptr;
+ ir_node *mem = get_Store_mem(node);
+ ir_mode *mode = get_irn_mode(val);
+ ir_node *sval = val;
+ int is_imm = 0;
ir_node *new_op;
+ ia32_am_flavour_t am_flav = ia32_B;
+ ia32_immop_type_t immop = ia32_ImmNone;
+
+ if (! mode_is_float(mode)) {
+ /* in case of storing a const (but not a symconst) -> make it an attribute */
+ if (is_ia32_Cnst(val)) {
+ switch (get_ia32_op_type(val)) {
+ case ia32_Const:
+ immop = ia32_ImmConst;
+ break;
+ case ia32_SymConst:
+ immop = ia32_ImmSymConst;
+ break;
+ default:
+ assert(0 && "unsupported Const type");
+ }
+ sval = noreg;
+ }
+ }
- /* in case of storing a const (but not a symconst) -> make it an attribute */
- if (is_ia32_Const(val)) {
- sval = noreg;
+ /* address might be a constant (symconst or absolute address) */
+ if (is_ia32_Const(ptr)) {
+ sptr = noreg;
+ is_imm = 0;
}
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
+ else
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
}
else if (get_mode_size_bits(mode) == 8) {
- new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem, mode_T);
}
else {
new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
}
/* stored const is an attribute (saves a register) */
- if (is_ia32_Const(val)) {
+ if (! mode_is_float(mode) && is_ia32_Cnst(val)) {
set_ia32_Immop_attr(new_op, val);
}
+ /* base is an constant address */
+ if (is_imm) {
+ if (get_ia32_immop_type(ptr) == ia32_ImmSymConst) {
+ set_ia32_am_sc(new_op, get_ia32_id_cnst(ptr));
+ }
+ else {
+ add_ia32_am_offs(new_op, get_ia32_cnst(ptr));
+ }
+
+ am_flav = ia32_O;
+ }
+
set_ia32_am_support(new_op, ia32_am_Dest);
set_ia32_op_type(new_op, ia32_AddrModeD);
- set_ia32_am_flavour(new_op, ia32_B);
+ set_ia32_am_flavour(new_op, am_flav);
set_ia32_ls_mode(new_op, get_irn_mode(val));
+ set_ia32_immop_type(new_op, immop);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
}
}
res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
set_ia32_pncode(res, get_Proj_proj(sel));
+ set_ia32_res_mode(res, get_irn_mode(op1));
if (cnst) {
copy_ia32_Immop_attr(res, and);
}
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
return res;
}
}
if (mode_is_float(get_irn_mode(expr))) {
- res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
+ else {
+ assert(0);
+ }
}
else {
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
}
set_ia32_Immop_attr(res, cnst);
+ set_ia32_res_mode(res, get_irn_mode(expr));
}
else {
if (mode_is_float(get_irn_mode(cmp_a))) {
- res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ res = new_rd_ia32_fCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
+ else {
+ assert(0);
+ }
}
else {
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem, mode_T);
}
+ set_ia32_res_mode(res, get_irn_mode(cmp_a));
}
set_ia32_pncode(res, get_Proj_proj(sel));
set_ia32_am_support(res, ia32_am_Source);
}
else {
- res = new_rd_ia32_SwitchJmp(dbg, irg, block, sel, mode_T);
+ /* determine the smallest switch case value */
+ int switch_min = INT_MAX;
+ const ir_edge_t *edge;
+ char buf[64];
+
+ foreach_out_edge(node, edge) {
+ int pn = get_Proj_proj(get_edge_src_irn(edge));
+ switch_min = pn < switch_min ? pn : switch_min;
+ }
+
+ if (switch_min) {
+ /* if smallest switch case is not 0 we need an additional sub */
+ snprintf(buf, sizeof(buf), "%d", switch_min);
+ res = new_rd_ia32_Lea(dbg, irg, block, sel, noreg, mode_Is);
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
+ sub_ia32_am_offs(res, buf);
+ set_ia32_am_flavour(res, ia32_am_OB);
+ set_ia32_am_support(res, ia32_am_Source);
+ set_ia32_op_type(res, ia32_AddrModeS);
+ }
+
+ res = new_rd_ia32_SwitchJmp(dbg, irg, block, switch_min ? res : sel, mode_T);
set_ia32_pncode(res, get_Cond_defaultProj(node));
+ set_ia32_res_mode(res, get_irn_mode(sel));
}
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
return res;
}
set_ia32_immop_type(res, ia32_ImmConst);
}
- SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, env->irn));
return res;
}
ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
}
* FLOAT -> FLOAT
* ================
* SSE(1/2) convert from float or double to double or float (cvtss/sd2sd/ss)
+ * x87 is mode_E internally, conversions happen only at load and store
+ * in non-strict semantic
*/
-//static ir_node *gen_int_downscale_conv(ia32_transform_env_t *env, ir_node *op,
-// ir_mode *src_mode, ir_mode *tgt_mode)
-//{
-// int n = get_mode_size_bits(src_mode);
-// int m = get_mode_size_bits(tgt_mode);
-// dbg_info *dbg = env->dbg;
-// ir_graph *irg = env->irg;
-// ir_node *block = env->block;
-// ir_node *noreg = ia32_new_NoReg_gp(env->cg);
-// ir_node *nomem = new_rd_NoMem(irg);
-// ir_node *new_op, *proj;
-// assert(n > m && "downscale expected");
-// if (mode_is_signed(src_mode) && mode_is_signed(tgt_mode)) {
-// /* ASHL Sn, n - m */
-// new_op = new_rd_ia32_Shl(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
-// proj = new_rd_Proj(dbg, irg, block, new_op, src_mode, 0);
-// set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
-// set_ia32_am_support(new_op, ia32_am_Source);
-// SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
-// /* ASHR Sn, n - m */
-// new_op = new_rd_ia32_Shrs(dbg, irg, block, noreg, noreg, proj, noreg, nomem, mode_T);
-// set_ia32_Immop_tarval(new_op, new_tarval_from_long(n - m, mode_Is));
-// }
-// else {
-// new_op = new_rd_ia32_And(dbg, irg, block, noreg, noreg, op, noreg, nomem, mode_T);
-// set_ia32_Immop_tarval(new_op, new_tarval_from_long((1 << m) - 1, mode_Is));
-// }
-// return new_op;
-//}
+/**
+ * Create a conversion from x87 state register to general purpose.
+ */
+static ir_node *gen_x87_fp_to_gp(ia32_transform_env_t *env, ir_mode *tgt_mode) {
+ ia32_code_gen_t *cg = env->cg;
+ entity *ent = cg->fp_to_gp;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *op = get_Conv_op(env->irn);
+ ir_node *fist, *mem, *load;
+
+ if (! ent) {
+ int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_vfp].mode);
+ ent = cg->fp_to_gp =
+ frame_alloc_area(get_irg_frame_type(env->irg), size, 16, 0);
+ }
+
+ /* do a fist */
+ fist = new_rd_ia32_vfist(env->dbg, irg, block, get_irg_frame(irg), noreg, op, get_irg_no_mem(irg), mode_T);
+
+ set_ia32_frame_ent(fist, ent);
+ set_ia32_use_frame(fist);
+ set_ia32_am_support(fist, ia32_am_Dest);
+ set_ia32_op_type(fist, ia32_AddrModeD);
+ set_ia32_am_flavour(fist, ia32_B);
+ set_ia32_ls_mode(fist, mode_E);
+
+ mem = new_r_Proj(irg, block, fist, mode_M, 0);
+
+ /* do a Load */
+ load = new_rd_ia32_Load(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
+
+ set_ia32_frame_ent(load, ent);
+ set_ia32_use_frame(load);
+ set_ia32_am_support(load, ia32_am_Source);
+ set_ia32_op_type(load, ia32_AddrModeS);
+ set_ia32_am_flavour(load, ia32_B);
+ set_ia32_ls_mode(load, tgt_mode);
+
+ return new_r_Proj(irg, block, load, tgt_mode, 0);
+}
+
+/**
+ * Create a conversion from x87 state register to general purpose.
+ */
+static ir_node *gen_x87_gp_to_fp(ia32_transform_env_t *env, ir_mode *src_mode) {
+ ia32_code_gen_t *cg = env->cg;
+ entity *ent = cg->gp_to_fp;
+ ir_graph *irg = env->irg;
+ ir_node *block = env->block;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = get_irg_no_mem(irg);
+ ir_node *op = get_Conv_op(env->irn);
+ ir_node *fild, *store, *mem;
+ int src_bits;
+
+ if (! ent) {
+ int size = get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode);
+ ent = cg->gp_to_fp =
+ frame_alloc_area(get_irg_frame_type(env->irg), size, size, 0);
+ }
+
+ /* first convert to 32 bit */
+ src_bits = get_mode_size_bits(src_mode);
+ if (src_bits == 8) {
+ op = new_rd_ia32_Conv_I2I8Bit(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ op = new_r_Proj(irg, block, op, mode_Is, 0);
+ }
+ else if (src_bits < 32) {
+ op = new_rd_ia32_Conv_I2I(env->dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ op = new_r_Proj(irg, block, op, mode_Is, 0);
+ }
+
+ /* do a store */
+ store = new_rd_ia32_Store(env->dbg, irg, block, get_irg_frame(irg), noreg, op, nomem, mode_T);
+
+ set_ia32_frame_ent(store, ent);
+ set_ia32_use_frame(store);
+
+ set_ia32_am_support(store, ia32_am_Dest);
+ set_ia32_op_type(store, ia32_AddrModeD);
+ set_ia32_am_flavour(store, ia32_B);
+ set_ia32_ls_mode(store, mode_Is);
+
+ mem = new_r_Proj(irg, block, store, mode_M, 0);
+
+ /* do a fild */
+ fild = new_rd_ia32_vfild(env->dbg, irg, block, get_irg_frame(irg), noreg, mem, mode_T);
+
+ set_ia32_frame_ent(fild, ent);
+ set_ia32_use_frame(fild);
+ set_ia32_am_support(fild, ia32_am_Source);
+ set_ia32_op_type(fild, ia32_AddrModeS);
+ set_ia32_am_flavour(fild, ia32_B);
+ set_ia32_ls_mode(fild, mode_E);
+
+ return new_r_Proj(irg, block, fild, mode_E, 0);
+}
/**
* Transforms a Conv node.
ir_node *new_op = NULL;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *nomem = new_rd_NoMem(irg);
- firm_dbg_module_t *mod = env->mod;
ir_node *proj;
+ DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
if (src_mode == tgt_mode) {
/* this can happen when changing mode_P to mode_Is */
/* we convert from float ... */
if (mode_is_float(tgt_mode)) {
/* ... to float */
- DB((mod, LEVEL_1, "create Conv(float, float) ..."));
- new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ if (USE_SSE2(env->cg)) {
+ DB((mod, LEVEL_1, "create Conv(float, float) ..."));
+ new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ }
+ else {
+ DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
+ edges_reroute(env->irn, op, irg);
+ }
}
else {
/* ... to int */
DB((mod, LEVEL_1, "create Conv(float, int) ..."));
- new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ else
+ return gen_x87_fp_to_gp(env, tgt_mode);
+
/* if target mode is not int: add an additional downscale convert */
if (tgt_bits < 32) {
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
- set_ia32_res_mode(new_op, tgt_mode);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_tgt_mode(new_op, tgt_mode);
+ set_ia32_src_mode(new_op, src_mode);
- proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
+ proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
if (tgt_bits == 8 || src_bits == 8) {
new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem, mode_T);
else {
/* we convert from int ... */
if (mode_is_float(tgt_mode)) {
+ FP_USED(env->cg);
/* ... to float */
DB((mod, LEVEL_1, "create Conv(int, float) ..."));
- new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem, mode_T);
+ else
+ return gen_x87_gp_to_fp(env, src_mode);
}
else {
/* ... to int */
}
if (new_op) {
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
- set_ia32_res_mode(new_op, tgt_mode);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+ set_ia32_tgt_mode(new_op, tgt_mode);
+ set_ia32_src_mode(new_op, src_mode);
set_ia32_am_support(new_op, ia32_am_Source);
entity *ent = be_get_frame_entity(node);
ir_mode *mode = env->mode;
+// /* If the StackParam has only one user -> */
+// /* put it in the Block where the user resides */
+// if (get_irn_n_edges(node) == 1) {
+// env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
+// }
+
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ else
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
else {
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, mode);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_rd_Proj(env->dbg, env->irg, env->block, new_op, mode, 0);
}
set_ia32_use_frame(new_op);
set_ia32_immop_type(new_op, ia32_ImmConst);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_rd_Proj(env->dbg, env->irg, env->block, new_op, env->mode, 0);
}
ir_mode *mode = get_type_mode(get_entity_type(ent));
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fLoad(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
+ else
+ new_op = new_rd_ia32_vfld(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
}
- else {
+ else
new_op = new_rd_ia32_Load(env->dbg, env->irg, env->block, ptr, noreg, mem, mode_T);
- }
set_ia32_frame_ent(new_op, ent);
set_ia32_use_frame(new_op);
set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, mode);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
}
ir_mode *mode = get_irn_mode(val);
if (mode_is_float(mode)) {
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ FP_USED(env->cg);
+ if (USE_SSE2(env->cg))
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ else
+ new_op = new_rd_ia32_vfst(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
}
else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
set_ia32_am_flavour(new_op, ia32_B);
set_ia32_ls_mode(new_op, mode);
- SET_IA32_ORIG_NODE(new_op, get_old_node_name(env));
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
return new_op;
}
tenv.dbg = get_irn_dbg_info(irn);
tenv.irg = cg->irg;
tenv.irn = irn;
- tenv.mod = cg->mod;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
tenv.mode = get_ia32_res_mode(irn);
tenv.cg = cg;
set_ia32_am_support(res, ia32_am_Full);
}
- SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
/* copy register */
slots = get_ia32_slots(res);
slots[0] = in2_reg;
tenv.dbg = get_irn_dbg_info(irn);
tenv.irg = cg->irg;
tenv.irn = irn;
- tenv.mod = cg->mod;
+ DEBUG_ONLY(tenv.mod = cg->mod;)
tenv.mode = get_irn_mode(irn);
tenv.cg = cg;
set_ia32_immop_type(res, ia32_ImmConst);
}
- SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
+ SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
/* add Add to schedule */
sched_add_before(irn, res);
tenv.dbg = get_irn_dbg_info(node);
tenv.irg = current_ir_graph;
tenv.irn = node;
- tenv.mod = cgenv->mod;
+ DEBUG_ONLY(tenv.mod = cgenv->mod;)
tenv.mode = get_irn_mode(node);
tenv.cg = cgenv;