/**
- * This file implements the IR transformation from firm into
- * ia32-Firm.
- *
+ * This file implements the IR transformation from firm into ia32-Firm.
+ * @author Christian Wuerdig
* $Id$
*/
#include "dbginfo.h"
#include "irprintf.h"
#include "debug.h"
+#include "irdom.h"
+#include "archop.h" /* we need this for Min and Max nodes */
#include "../benode_t.h"
#include "../besched.h"
+#include "../beabi.h"
#include "bearch_ia32_t.h"
-
#include "ia32_nodes_attr.h"
-#include "../arch/archop.h" /* we need this for Min and Max nodes */
#include "ia32_transform.h"
#include "ia32_new_nodes.h"
#include "ia32_map_regs.h"
#include "ia32_dbg_stat.h"
+#include "ia32_optimize.h"
#include "gen_ia32_regalloc_if.h"
*
****************************************************************************************************/
+/**
+ * Returns 1 if irn is a Const representing 0, 0 otherwise
+ */
+static INLINE int is_ia32_Const_0(ir_node *irn) {
+ return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
+}
+
+/**
+ * Returns 1 if irn is a Const representing 1, 0 otherwise
+ */
+static INLINE int is_ia32_Const_1(ir_node *irn) {
+ return is_ia32_Const(irn) ? classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
+}
+
+/**
+ * Returns the Proj representing the UNKNOWN register for given mode.
+ */
+static ir_node *be_get_unknown_for_mode(ia32_code_gen_t *cg, ir_mode *mode) {
+ be_abi_irg_t *babi = cg->birg->abi;
+ const arch_register_t *unknwn_reg = NULL;
+
+ if (mode_is_float(mode)) {
+ unknwn_reg = USE_SSE2(cg) ? &ia32_xmm_regs[REG_XMM_UKNWN] : &ia32_vfp_regs[REG_VFP_UKNWN];
+ }
+ else {
+ unknwn_reg = &ia32_gp_regs[REG_GP_UKNWN];
+ }
+
+ return be_abi_get_callee_save_irn(babi, unknwn_reg);
+}
+
/**
* Gets the Proj with number pn from irn.
*/
return NULL;
}
+/**
+ * SSE convert of an integer node into a floating point node.
+ */
+static ir_node *gen_sse_conv_int2float(ia32_code_gen_t *cg, dbg_info *dbg, ir_graph *irg, ir_node *block,
+ ir_node *in, ir_node *old_node, ir_mode *tgt_mode)
+{
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+
+ ir_node *conv = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, in, nomem);
+ set_ia32_src_mode(conv, get_irn_mode(in));
+ set_ia32_tgt_mode(conv, tgt_mode);
+ set_ia32_am_support(conv, ia32_am_Source);
+ SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
+
+ return new_rd_Proj(dbg, irg, block, conv, tgt_mode, pn_ia32_Conv_I2FP_res);
+}
+
/* Generates an entity for a known FP const (used for FP Neg + Abs) */
static ident *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
static const struct {
new_op = func(dbg, irg, block, noreg_gp, noreg_gp, op1, op2, nomem);
set_ia32_am_support(new_op, ia32_am_Source);
}
+ set_ia32_ls_mode(new_op, mode);
}
else {
/* integer operations */
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
/* try to optimize to inc/dec */
- if ((env->cg->opt & IA32_OPT_INCDEC) && tv) {
+ if ((env->cg->opt & IA32_OPT_INCDEC) && (get_ia32_op_type(const_op) == ia32_Const)) {
/* optimize tarvals */
class_tv = classify_tarval(tv);
class_negtv = classify_tarval(tarval_neg(tv));
if (normal_add) {
new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
set_ia32_Immop_attr(new_op, const_op);
+ set_ia32_commutative(new_op);
}
return new_op;
new_op = new_rd_ia32_Lea(dbg, irg, block, op1, noreg, mode);
set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
set_ia32_am_flavour(new_op, ia32_am_OB);
+
+ DBG_OPT_LEA1(op2, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
+ DBG_OPT_LEA2(op1, op2, new_op);
+
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
add_ia32_am_offs(new_op, get_ia32_cnst(op2));
set_ia32_res_mode(new_op, mode);
- return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
+ return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Add_res);
+}
+
+/**
+ * Transforms an ia32_l_AddC (created in intrinsic lowering) into a "real" AddC
+ *
+ * @param env The transformation environment
+ * @return the created ia32 Add node
+ */
+static ir_node *gen_ia32_l_AddC(ia32_transform_env_t *env) {
+ return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_AddC);
+}
+
+/**
+ * Transforms an ia32_l_Add (created in intrinsic lowering) into a "real" Add
+ *
+ * @param env The transformation environment
+ * @return the created ia32 Add node
+ */
+static ir_node *gen_ia32_l_Add(ia32_transform_env_t *env) {
+ return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_Add);
}
set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
set_ia32_am_sc_sign(new_op);
set_ia32_am_flavour(new_op, ia32_am_OB);
+
+ DBG_OPT_LEA1(op2, new_op);
}
else {
/* this is the 1st case */
new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg, mode);
+ DBG_OPT_LEA2(op1, op2, new_op);
+
if (get_ia32_op_type(op1) == ia32_SymConst) {
set_ia32_am_sc(new_op, get_ia32_id_cnst(op1));
sub_ia32_am_offs(new_op, get_ia32_cnst(op2));
set_ia32_res_mode(new_op, mode);
- return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
+ return new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_Sub_res);
+}
+
+/**
+ * Transforms an ia32_l_SubC (created in intrinsic lowering) into a "real" SubC
+ *
+ * @param env The transformation environment
+ * @return the created ia32 SubC node
+ */
+static ir_node *gen_ia32_l_SubC(ia32_transform_env_t *env) {
+ return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_SubC);
+}
+
+/**
+ * Transforms an ia32_l_Sub (created in intrinsic lowering) into a "real" Sub
+ *
+ * @param env The transformation environment
+ * @return the created ia32 Sub node
+ */
+static ir_node *gen_ia32_l_Sub(ia32_transform_env_t *env) {
+ return gen_binop(env, get_binop_left(env->irn), get_binop_right(env->irn), new_rd_ia32_Sub);
}
edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Is, pn_ia32_Cdq_EDX);
}
else {
- edx_node = new_rd_ia32_Const(dbg, irg, block, mode_Iu);
+ edx_node = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Iu);
set_ia32_Const_type(edx_node, ia32_Const);
set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
}
proj = get_edge_src_irn(get_irn_out_edge_first(irn));
assert(is_Proj(proj) && "non-Proj to Div/Mod node");
- if (get_Proj_proj(proj) == pn_DivMod_res_div) {
+ if (get_irn_op(irn) == op_Div) {
+ set_Proj_proj(proj, pn_DivMod_res_div);
in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_mod);
}
else {
+ set_Proj_proj(proj, pn_DivMod_res_mod);
in_keep[0] = new_rd_Proj(dbg, irg, block, res, mode_Is, pn_DivMod_res_div);
}
/* address might be a constant (symconst or absolute address) */
if (is_ia32_Const(ptr)) {
sptr = noreg;
- is_imm = 0;
+ is_imm = 1;
}
if (mode_is_float(mode)) {
new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, sptr, noreg, sval, mem);
}
/* stored const is an attribute (saves a register) */
if (USE_SSE2(env->cg))
res = new_rd_ia32_xCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
else {
+ ir_node *proj_eax;
res = new_rd_ia32_vfCondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
+ proj_eax = new_r_Proj(irg, block, res, mode_Is, pn_ia32_vfCondJmp_temp_reg_eax);
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, &proj_eax);
}
}
else {
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
+ set_ia32_commutative(res);
}
set_ia32_res_mode(res, get_irn_mode(cmp_a));
}
set_ia32_pncode(res, get_Proj_proj(sel));
- set_ia32_am_support(res, ia32_am_Source);
+ //set_ia32_am_support(res, ia32_am_Source);
}
else {
/* determine the smallest switch case value */
rem = size & 0x3; /* size % 4 */
size >>= 2;
- res = new_rd_ia32_Const(dbg, irg, block, mode_Is);
+ res = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode_Is);
set_ia32_op_type(res, ia32_Const);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
* @return The transformed node.
*/
static ir_node *gen_Mux(ia32_transform_env_t *env) {
+#if 0
ir_node *node = env->irn;
ir_node *new_op = new_rd_ia32_CMov(env->dbg, env->irg, env->block, \
get_Mux_sel(node), get_Mux_false(node), get_Mux_true(node), env->mode);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, env->irn));
+ return new_op;
+#endif
+ return NULL;
+}
+
+typedef ir_node *cmov_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *cmp_a, ir_node *cmp_b, \
+ ir_node *psi_true, ir_node *psi_default, ir_mode *mode);
+
+/**
+ * Transforms a Psi node into CMov.
+ *
+ * @param env The transformation environment
+ * @return The transformed node.
+ */
+static ir_node *gen_Psi(ia32_transform_env_t *env) {
+ ia32_code_gen_t *cg = env->cg;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_mode *mode = env->mode;
+ ir_node *block = env->block;
+ ir_node *node = env->irn;
+ ir_node *cmp_proj = get_Mux_sel(node);
+ ir_node *psi_true = get_Psi_val(node, 0);
+ ir_node *psi_default = get_Psi_default(node);
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *cmp, *cmp_a, *cmp_b, *and1, *and2, *new_op = NULL;
+ int pnc;
+
+ assert(get_irn_mode(cmp_proj) == mode_b && "Condition for Psi must have mode_b");
+
+ cmp = get_Proj_pred(cmp_proj);
+ cmp_a = get_Cmp_left(cmp);
+ cmp_b = get_Cmp_right(cmp);
+ pnc = get_Proj_proj(cmp_proj);
+
+ if (mode_is_float(mode)) {
+ /* floating point psi */
+ FP_USED(cg);
+
+ /* 1st case: compare operands are float too */
+ if (USE_SSE2(cg)) {
+ /* psi(cmp(a, b), t, f) can be done as: */
+ /* tmp = cmp a, b */
+ /* tmp2 = t and tmp */
+ /* tmp3 = f and not tmp */
+ /* res = tmp2 or tmp3 */
+
+ /* in case the compare operands are int, we move them into xmm register */
+ if (! mode_is_float(get_irn_mode(cmp_a))) {
+ cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, node, mode_D);
+ cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, node, mode_D);
+
+ pnc |= 8; /* transform integer compare to fp compare */
+ }
+
+ new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
+ set_ia32_pncode(new_op, pnc);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_res_mode(new_op, mode);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
+ new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xCmp_res);
+
+ and1 = new_rd_ia32_xAnd(dbg, irg, block, noreg, noreg, psi_true, new_op, nomem);
+ set_ia32_am_support(and1, ia32_am_Source);
+ set_ia32_res_mode(and1, mode);
+ SET_IA32_ORIG_NODE(and1, ia32_get_old_node_name(cg, node));
+ and1 = new_rd_Proj(dbg, irg, block, and1, mode, pn_ia32_xAnd_res);
+
+ and2 = new_rd_ia32_xAndNot(dbg, irg, block, noreg, noreg, new_op, psi_default, nomem);
+ set_ia32_am_support(and2, ia32_am_Source);
+ set_ia32_res_mode(and2, mode);
+ SET_IA32_ORIG_NODE(and2, ia32_get_old_node_name(cg, node));
+ and2 = new_rd_Proj(dbg, irg, block, and2, mode, pn_ia32_xAndNot_res);
+
+ new_op = new_rd_ia32_xOr(dbg, irg, block, noreg, noreg, and1, and2, nomem);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_res_mode(new_op, mode);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
+ new_op = new_rd_Proj(dbg, irg, block, new_op, mode, pn_ia32_xOr_res);
+ }
+ else {
+ /* x87 FPU */
+ new_op = new_rd_ia32_vfCMov(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
+ set_ia32_pncode(new_op, pnc);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ }
+ }
+ else {
+ /* integer psi */
+ construct_binop_func *set_func = NULL;
+ cmov_func_t *cmov_func = NULL;
+
+ if (mode_is_float(get_irn_mode(cmp_a))) {
+ /* 1st case: compare operands are floats */
+ FP_USED(cg);
+
+ if (USE_SSE2(cg)) {
+ /* SSE FPU */
+ set_func = new_rd_ia32_xCmpSet;
+ cmov_func = new_rd_ia32_xCmpCMov;
+ }
+ else {
+ /* x87 FPU */
+ set_func = new_rd_ia32_vfCmpSet;
+ cmov_func = new_rd_ia32_vfCmpCMov;
+ }
+
+ pnc &= 7; /* fp compare -> int compare */
+ }
+ else {
+ /* 2nd case: compare operand are integer too */
+ set_func = new_rd_ia32_CmpSet;
+ cmov_func = new_rd_ia32_CmpCMov;
+ }
+
+ /* create the nodes */
+
+ /* check for special case first: And/Or -- Cmp with 0 -- Psi */
+ if (is_ia32_Const_0(cmp_b) && is_Proj(cmp_a) && (is_ia32_And(get_Proj_pred(cmp_a)) || is_ia32_Or(get_Proj_pred(cmp_a)))) {
+ if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
+ /* first case for SETcc: default is 0, set to 1 iff condition is true */
+ new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
+ set_ia32_pncode(new_op, pnc);
+ }
+ else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
+ /* second case for SETcc: default is 1, set to 0 iff condition is true: */
+ /* we invert condition and set default to 0 */
+ new_op = new_rd_ia32_PsiCondSet(dbg, irg, block, cmp_a, mode);
+ set_ia32_pncode(new_op, get_negated_pnc(pnc, mode));
+ }
+ else {
+ /* otherwise: use CMOVcc */
+ new_op = new_rd_ia32_PsiCondCMov(dbg, irg, block, cmp_a, psi_true, psi_default, mode);
+ set_ia32_pncode(new_op, pnc);
+ }
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
+ }
+ else {
+ env->irn = cmp;
+ if (is_ia32_Const_1(psi_true) && is_ia32_Const_0(psi_default)) {
+ /* first case for SETcc: default is 0, set to 1 iff condition is true */
+ new_op = gen_binop(env, cmp_a, cmp_b, set_func);
+ set_ia32_pncode(get_Proj_pred(new_op), pnc);
+ set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
+ }
+ else if (is_ia32_Const_0(psi_true) && is_ia32_Const_1(psi_default)) {
+ /* second case for SETcc: default is 1, set to 0 iff condition is true: */
+ /* we invert condition and set default to 0 */
+ new_op = gen_binop(env, cmp_a, cmp_b, set_func);
+ set_ia32_pncode(get_Proj_pred(new_op), get_negated_pnc(pnc, mode));
+ set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
+ }
+ else {
+ /* otherwise: use CMOVcc */
+ new_op = cmov_func(dbg, irg, block, cmp_a, cmp_b, psi_true, psi_default, mode);
+ set_ia32_pncode(new_op, pnc);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, node));
+ }
+ }
+ }
+
return new_op;
}
* @return The created ia32 Conv node
*/
static ir_node *gen_Conv(ia32_transform_env_t *env) {
- dbg_info *dbg = env->dbg;
- ir_graph *irg = env->irg;
- ir_node *op = get_Conv_op(env->irn);
- ir_mode *src_mode = get_irn_mode(op);
- ir_mode *tgt_mode = env->mode;
- int src_bits = get_mode_size_bits(src_mode);
- int tgt_bits = get_mode_size_bits(tgt_mode);
- ir_node *block = env->block;
- ir_node *new_op = NULL;
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *nomem = new_rd_NoMem(irg);
- ir_node *proj;
+ dbg_info *dbg = env->dbg;
+ ir_graph *irg = env->irg;
+ ir_node *op = get_Conv_op(env->irn);
+ ir_mode *src_mode = get_irn_mode(op);
+ ir_mode *tgt_mode = env->mode;
+ int src_bits = get_mode_size_bits(src_mode);
+ int tgt_bits = get_mode_size_bits(tgt_mode);
+ int pn = -1;
+ ir_node *block = env->block;
+ ir_node *new_op = NULL;
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ ir_node *proj;
DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
if (src_mode == tgt_mode) {
if (USE_SSE2(env->cg)) {
DB((mod, LEVEL_1, "create Conv(float, float) ..."));
new_op = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_FP2FP_res;
}
else {
DB((mod, LEVEL_1, "killed Conv(float, float) ..."));
else {
/* ... to int */
DB((mod, LEVEL_1, "create Conv(float, int) ..."));
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_Conv_FP2I(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_FP2I_res;
+ }
else
return gen_x87_fp_to_gp(env, tgt_mode);
set_ia32_tgt_mode(new_op, tgt_mode);
set_ia32_src_mode(new_op, src_mode);
- proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, 0);
+ proj = new_rd_Proj(dbg, irg, block, new_op, mode_Is, pn_ia32_Conv_FP2I_res);
if (tgt_bits == 8 || src_bits == 8) {
new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, proj, nomem);
+ pn = pn_ia32_Conv_I2I8Bit_res;
}
else {
new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, proj, nomem);
+ pn = pn_ia32_Conv_I2I_res;
}
}
}
FP_USED(env->cg);
/* ... to float */
DB((mod, LEVEL_1, "create Conv(int, float) ..."));
- if (USE_SSE2(env->cg))
+ if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_Conv_I2FP(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_I2FP_res;
+ }
else
return gen_x87_gp_to_fp(env, src_mode);
}
DB((mod, LEVEL_1, "create Conv(int, int) ...", src_mode, tgt_mode));
if (tgt_bits == 8 || src_bits == 8) {
new_op = new_rd_ia32_Conv_I2I8Bit(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_I2I8Bit_res;
}
else {
new_op = new_rd_ia32_Conv_I2I(dbg, irg, block, noreg, noreg, op, nomem);
+ pn = pn_ia32_Conv_I2I_res;
}
}
}
set_ia32_am_support(new_op, ia32_am_Source);
- new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, 0);
+ new_op = new_rd_Proj(dbg, irg, block, new_op, tgt_mode, pn);
}
return new_op;
*
********************************************/
+ /**
+ * Decides in which block the transformed StackParam should be placed.
+ * If the StackParam has more than one user, the dominator block of
+ * the users will be returned. In case of only one user, this is either
+ * the user block or, in case of a Phi, the predecessor block of the Phi.
+ */
+ static ir_node *get_block_transformed_stack_param(ir_node *irn) {
+ ir_node *dom_bl = NULL;
+
+ if (get_irn_n_edges(irn) == 1) {
+ ir_node *src = get_edge_src_irn(get_irn_out_edge_first(irn));
+
+ if (! is_Phi(src)) {
+ dom_bl = get_nodes_block(src);
+ }
+ else {
+ /* Determine on which in position of the Phi the irn is */
+ /* and get the corresponding cfg predecessor block. */
+
+ int i = get_irn_pred_pos(src, irn);
+ assert(i >= 0 && "kaputt");
+ dom_bl = get_Block_cfgpred_block(get_nodes_block(src), i);
+ }
+ }
+ else {
+ dom_bl = node_users_smallest_common_dominator(irn, 1);
+ }
+
+ assert(dom_bl && "dominator block not found");
+
+ return dom_bl;
+ }
+
static ir_node *gen_be_StackParam(ia32_transform_env_t *env) {
ir_node *new_op = NULL;
ir_node *node = env->irn;
entity *ent = be_get_frame_entity(node);
ir_mode *mode = env->mode;
-// /* If the StackParam has only one user -> */
-// /* put it in the Block where the user resides */
-// if (get_irn_n_edges(node) == 1) {
-// env->block = get_nodes_block(get_edge_src_irn(get_irn_out_edge_first(node)));
-// }
+ /* choose the block where to place the load */
+ env->block = get_block_transformed_stack_param(node);
if (mode_is_float(mode)) {
FP_USED(env->cg);
set_ia32_am_support(res, ia32_am_Full);
set_ia32_commutative(res);
}
+ set_ia32_res_mode(res, tenv.mode);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(tenv.cg, irn));
/* copy register */
arch_set_irn_register(cg->arch_env, res, out_reg);
set_ia32_op_type(res, ia32_Normal);
set_ia32_commutative(res);
+ set_ia32_res_mode(res, tenv.mode);
if (imm) {
set_ia32_cnst(res, offs);
DBG_OPT_LEA2ADD(irn, res);
- res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
+ res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, pn_ia32_Add_res);
/* add result Proj to schedule */
sched_add_before(irn, res);
#define IGN(a)
GEN(Add);
+ GEN(ia32_l_Add);
+ GEN(ia32_l_AddC);
GEN(Sub);
+ GEN(ia32_l_Sub);
+ GEN(ia32_l_SubC);
GEN(Mul);
GEN(And);
GEN(Or);
GEN(CopyB);
GEN(Mux);
+ GEN(Psi);
IGN(Call);
IGN(Alloc);
ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
ir_op *op = get_irn_op(node);
ir_node *asm_node = NULL;
+ int i;
if (is_Block(node))
return;
+ /* link arguments pointing to Unknown to the UNKNOWN Proj */
+ for (i = get_irn_arity(node) - 1; i >= 0; i--) {
+ if (is_Unknown(get_irn_n(node, i)))
+ set_irn_n(node, i, be_get_unknown_for_mode(cg, get_irn_mode(get_irn_n(node, i))));
+ }
+
DBG((cg->mod, LEVEL_1, "check %+F ... ", node));
if (op->ops.generic) {
ia32_transform_env_t tenv;
DB((cg->mod, LEVEL_1, "ignored\n"));
}
}
+
+/**
+ * Transforms a psi condition.
+ */
+static void transform_psi_cond(ir_node *cond, ir_mode *mode, ia32_code_gen_t *cg) {
+ int i;
+
+ assert(get_irn_mode(cond) == mode_b && "logical operator for condition must be mode_b");
+ set_irn_mode(cond, mode);
+
+ for (i = get_irn_arity(cond) - 1; i >= 0; i--) {
+ ir_node *in = get_irn_n(cond, i);
+
+ /* if in is a compare: transform into Set/xCmp */
+ if (is_Proj(in)) {
+ ir_node *new_op = NULL;
+ ir_node *cmp = get_Proj_pred(in);
+ ir_node *cmp_a = get_Cmp_left(cmp);
+ ir_node *cmp_b = get_Cmp_right(cmp);
+ dbg_info *dbg = get_irn_dbg_info(cmp);
+ ir_graph *irg = get_irn_irg(cmp);
+ ir_node *block = get_nodes_block(cmp);
+ ir_node *noreg = ia32_new_NoReg_gp(cg);
+ ir_node *nomem = new_rd_NoMem(irg);
+ int pnc = get_Proj_proj(in);
+
+ /* this is a compare */
+ if (mode_is_float(mode)) {
+ /* Psi is float, we need a floating point compare */
+
+ if (USE_SSE2(cg)) {
+ /* SSE FPU */
+ if (! mode_is_float(get_irn_mode(cmp_a))) {
+ cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_a, cmp_a, mode);
+ cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, cmp_b, cmp_b, mode);
+ pnc |= 8;
+ }
+
+ new_op = new_rd_ia32_xCmp(dbg, irg, block, noreg, noreg, cmp_a, cmp_b, nomem);
+ set_ia32_pncode(new_op, pnc);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(cg, cmp));
+ }
+ else {
+ /* x87 FPU */
+ assert(0);
+ }
+ }
+ else {
+ /* integer Psi */
+ ia32_transform_env_t tenv;
+ construct_binop_func *set_func = NULL;
+
+ if (mode_is_float(get_irn_mode(cmp_a))) {
+ /* 1st case: compare operands are floats */
+ FP_USED(cg);
+
+ if (USE_SSE2(cg)) {
+ /* SSE FPU */
+ set_func = new_rd_ia32_xCmpSet;
+ }
+ else {
+ /* x87 FPU */
+ set_func = new_rd_ia32_vfCmpSet;
+ }
+
+ pnc &= 7; /* fp compare -> int compare */
+ }
+ else {
+ /* 2nd case: compare operand are integer too */
+ set_func = new_rd_ia32_CmpSet;
+ }
+
+ tenv.block = block;
+ tenv.cg = cg;
+ tenv.dbg = dbg;
+ tenv.irg = irg;
+ tenv.irn = cmp;
+ tenv.mode = mode;
+ tenv.mod = cg->mod;
+
+ new_op = gen_binop(&tenv, cmp_a, cmp_b, set_func);
+ set_ia32_pncode(get_Proj_pred(new_op), pnc);
+ set_ia32_am_support(get_Proj_pred(new_op), ia32_am_Source);
+ }
+
+ /* exchange with old compare */
+ exchange(in, new_op);
+ }
+ else {
+ /* another complex condition */
+ transform_psi_cond(in, mode, cg);
+ }
+ }
+}
+
+/**
+ * The Psi selector can be a tree of compares combined with "And"s and "Or"s.
+ * We create a Set node, respectively a xCmp in case the Psi is a float, for each
+ * compare, which causes the compare result to be stores in a register. The
+ * "And"s and "Or"s are transformed later, we just have to set their mode right.
+ */
+void ia32_transform_psi_cond_tree(ir_node *node, void *env) {
+ ia32_code_gen_t *cg = (ia32_code_gen_t *)env;
+ ir_node *psi_sel, *new_cmp, *block;
+ ir_graph *irg;
+ ir_mode *mode;
+
+ /* check for Psi */
+ if (get_irn_opcode(node) != iro_Psi)
+ return;
+
+ psi_sel = get_Psi_cond(node, 0);
+
+ /* if psi_cond is a cmp: do nothing, this case is covered by gen_Psi */
+ if (is_Proj(psi_sel))
+ return;
+
+ mode = get_irn_mode(node);
+
+ transform_psi_cond(psi_sel, mode, cg);
+
+ irg = get_irn_irg(node);
+ block = get_nodes_block(node);
+
+ /* we need to compare the evaluated condition tree with 0 */
+
+ /* BEWARE: new_r_Const_long works for floating point as well */
+ new_cmp = new_r_Cmp(irg, block, psi_sel, new_r_Const_long(irg, block, mode, 0));
+ /* transform the const */
+ ia32_place_consts_set_modes(new_cmp, cg);
+ new_cmp = new_r_Proj(irg, block, new_cmp, mode_b, pn_Cmp_Ne + (mode_is_float(mode) ? pn_Cmp_Uo : 0));
+
+ set_Psi_cond(node, 0, new_cmp);
+}
projects / libfirm / blobdiff