ir_node *op, ir_node *mem, ir_mode *mode);
typedef enum {
- ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS
+ ia32_SSIGN, ia32_DSIGN, ia32_SABS, ia32_DABS, ia32_known_const_max
} ia32_known_const_t;
/****************************************************************************************************
*
****************************************************************************************************/
-struct tv_ent {
- entity *ent;
- tarval *tv;
-};
-
-/* Compares two (entity, tarval) combinations */
-static int cmp_tv_ent(const void *a, const void *b, size_t len) {
- const struct tv_ent *e1 = a;
- const struct tv_ent *e2 = b;
-
- return !(e1->tv == e2->tv);
-}
-
/* Generates an entity for a known FP const (used for FP Neg + Abs) */
-static char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
- static set *const_set = NULL;
- struct tv_ent key;
- struct tv_ent *entry;
- char *tp_name;
- char *ent_name;
- char *cnst_str;
+static const char *gen_fp_known_const(ir_mode *mode, ia32_known_const_t kct) {
+ static const struct {
+ const char *tp_name;
+ const char *ent_name;
+ const char *cnst_str;
+ } names [ia32_known_const_max] = {
+ { TP_SFP_SIGN, ENT_SFP_SIGN, SFP_SIGN }, /* ia32_SSIGN */
+ { TP_DFP_SIGN, ENT_DFP_SIGN, DFP_SIGN }, /* ia32_DSIGN */
+ { TP_SFP_ABS, ENT_SFP_ABS, SFP_ABS }, /* ia32_SABS */
+ { TP_DFP_ABS, ENT_DFP_ABS, DFP_ABS } /* ia32_DABS */
+ };
+ static struct entity *ent_cache[ia32_known_const_max];
+
+ const char *tp_name, *ent_name, *cnst_str;
ir_type *tp;
ir_node *cnst;
ir_graph *rem;
entity *ent;
+ tarval *tv;
- if (! const_set) {
- const_set = new_set(cmp_tv_ent, 10);
- }
+ ent_name = names[kct].ent_name;
+ if (! ent_cache[kct]) {
+ tp_name = names[kct].tp_name;
+ cnst_str = names[kct].cnst_str;
- switch (kct) {
- case ia32_SSIGN:
- tp_name = TP_SFP_SIGN;
- ent_name = ENT_SFP_SIGN;
- cnst_str = SFP_SIGN;
- break;
- case ia32_DSIGN:
- tp_name = TP_DFP_SIGN;
- ent_name = ENT_DFP_SIGN;
- cnst_str = DFP_SIGN;
- break;
- case ia32_SABS:
- tp_name = TP_SFP_ABS;
- ent_name = ENT_SFP_ABS;
- cnst_str = SFP_ABS;
- break;
- case ia32_DABS:
- tp_name = TP_DFP_ABS;
- ent_name = ENT_DFP_ABS;
- cnst_str = DFP_ABS;
- break;
- }
-
-
- key.tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
- key.ent = NULL;
-
- entry = set_insert(const_set, &key, sizeof(key), HASH_PTR(key.tv));
-
- if (! entry->ent) {
+ tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
tp = new_type_primitive(new_id_from_str(tp_name), mode);
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
const code irg */
rem = current_ir_graph;
current_ir_graph = get_const_code_irg();
- cnst = new_Const(mode, key.tv);
+ cnst = new_Const(mode, tv);
current_ir_graph = rem;
set_atomic_ent_value(ent, cnst);
- /* set the entry for hashmap */
- entry->ent = ent;
+ /* cache the entry */
+ ent_cache[kct] = ent;
}
-
return ent_name;
}
* Prints the old node name on cg obst and returns a pointer to it.
*/
const char *get_old_node_name(ia32_transform_env_t *env) {
- static int name_cnt = 0;
ia32_isa_t *isa = (ia32_isa_t *)env->cg->arch_env->isa;
lc_eoprintf(firm_get_arg_env(), isa->name_obst, "%+F", env->irn);
obstack_1grow(isa->name_obst, 0);
isa->name_obst_size += obstack_object_size(isa->name_obst);
- name_cnt++;
- if (name_cnt % 1024 == 0) {
- printf("name obst size reached %d bytes after %d nodes\n", isa->name_obst_size, name_cnt);
- }
return obstack_finish(isa->name_obst);
}
#endif /* NDEBUG */
ir_node *proj_EAX, *proj_EDX, *mulh;
ir_node *in[1];
- assert(mode_is_float(env->mode) && "Mulh with float not supported");
+ assert(!mode_is_float(env->mode) && "Mulh with float not supported");
proj_EAX = gen_binop(env, op1, op2, new_rd_ia32_Mulh);
mulh = get_Proj_pred(proj_EAX);
proj_EDX = new_rd_Proj(env->dbg, env->irg, env->block, mulh, env->mode, pn_EDX);
return new_rd_Proj(dbg, irg, block, new_op, mode, 0);
}
+static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
+ const ir_edge_t *edge;
+ ir_node *proj;
+ assert(get_irn_mode(irn) == mode_T && "need mode_T");
+
+ foreach_out_edge(irn, edge) {
+ proj = get_edge_src_irn(edge);
+
+ if (get_Proj_proj(proj) == pn)
+ return proj;
+ }
+ return NULL;
+}
/**
* Generates an ia32 DivMod with additional infrastructure for the
switch (dm_flav) {
case flavour_Div:
- mem = get_Div_mem(irn);
+ mem = get_Div_mem(irn);
+ mode = get_irn_mode(get_proj_for_pn(irn, pn_Div_res));
break;
case flavour_Mod:
- mem = get_Mod_mem(irn);
+ mem = get_Mod_mem(irn);
+ mode = get_irn_mode(get_proj_for_pn(irn, pn_Mod_res));
break;
case flavour_DivMod:
- mem = get_DivMod_mem(irn);
+ mem = get_DivMod_mem(irn);
+ mode = get_irn_mode(get_proj_for_pn(irn, pn_DivMod_res_div));
break;
default:
assert(0);
* @return The created ia32 Minus node
*/
static ir_node *gen_Minus(ia32_transform_env_t *env, ir_node *op) {
- char *name;
+ const char *name;
ir_node *new_op;
ir_node *noreg_gp = ia32_new_NoReg_gp(env->cg);
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *nomem = new_NoMem();
int size;
- char *name;
+ const char *name;
if (mode_is_float(mode)) {
res = new_rd_ia32_fAnd(dbg,irg, block, noreg_gp, noreg_gp, op, noreg_fp, nomem, mode_T);
ir_node *val = get_Store_value(node);
ir_node *ptr = get_Store_ptr(node);
ir_node *mem = get_Store_mem(node);
+ ir_mode *mode = get_irn_mode(val);
ir_node *sval = val;
ir_node *new_op;
- /* in case of storing a const -> make it an attribute */
- if (is_ia32_Cnst(val)) {
+ /* in case of storing a const (but not a symconst) -> make it an attribute */
+ if (is_ia32_Const(val)) {
sval = noreg;
}
- if (mode_is_float(env->mode)) {
- new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
+ if (mode_is_float(mode)) {
+ new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
+ }
+ else if (get_mode_size_bits(mode) == 8) {
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
}
else {
- new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, env->mode);
+ new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, sval, mem, mode_T);
}
/* stored const is an attribute (saves a register) */
- if (is_ia32_Cnst(val)) {
+ if (is_ia32_Const(val)) {
set_ia32_Immop_attr(new_op, val);
}
/**
- * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp or CondJmp_i
+ * Transforms a Cond -> Proj[b] -> Cmp into a CondJmp, CondJmp_i or TestJmp
*
* @param env The transformation environment
* @return The transformed node.
ir_node *res = NULL;
ir_node *pred = NULL;
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *nomem = new_NoMem();
ir_node *cmp_a, *cmp_b, *cnst, *expr;
if (is_Proj(sel) && sel_mode == mode_b) {
+ ir_node *nomem = new_NoMem();
+
pred = get_Proj_pred(sel);
/* get both compare operators */
expr = get_expr_op(cmp_a, cmp_b);
if (cnst && expr) {
+ if (mode_is_int(get_irn_mode(expr))) {
+ if (classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL) {
+ /* a Cmp A, 0 */
+ ir_node *op1 = expr;
+ ir_node *op2 = expr;
+ ir_node *and = skip_Proj(expr);
+ char *cnst = NULL;
+
+ /* check, if expr is an only once used And operation */
+ if (get_irn_n_edges(expr) == 1 && is_ia32_And(and)) {
+ op1 = get_irn_n(and, 2);
+ op2 = get_irn_n(and, 3);
+
+ cnst = get_ia32_cnst(and);
+ }
+ res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2, mode_T);
+ set_ia32_pncode(res, get_Proj_proj(sel));
+
+ if (cnst) {
+ copy_ia32_Immop_attr(res, and);
+ }
+
+ SET_IA32_ORIG_NODE(res, get_old_node_name(env));
+ return res;
+ }
+ }
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem, mode_T);
set_ia32_Immop_attr(res, cnst);
}
}
SET_IA32_ORIG_NODE(res, get_old_node_name(env));
-
return res;
}
if (mode_is_float(mode)) {
new_op = new_rd_ia32_fStore(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
}
+ else if (get_mode_size_bits(mode) == 8) {
+ new_op = new_rd_ia32_Store8Bit(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
+ }
else {
new_op = new_rd_ia32_Store(env->dbg, env->irg, env->block, ptr, noreg, val, mem, mode_T);
}
/* generate the add */
if (mode_is_float(tenv.mode)) {
res = new_rd_ia32_fAdd(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+ set_ia32_am_support(res, ia32_am_Source);
}
else {
res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, res, in1, nomem, mode_T);
+ set_ia32_am_support(res, ia32_am_Full);
}
SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
}
}
+/**
+ * Transforms a LEA into an Add if possible
+ * THIS FUNCTIONS MUST BE CALLED AFTER REGISTER ALLOCATION.
+ */
+void ia32_transform_lea_to_add(ir_node *irn, ia32_code_gen_t *cg) {
+ ia32_am_flavour_t am_flav;
+ int imm = 0;
+ ir_node *res = NULL;
+ ir_node *nomem, *noreg, *base, *index, *op1, *op2;
+ char *offs;
+ ia32_transform_env_t tenv;
+ const arch_register_t *out_reg, *base_reg, *index_reg;
+
+ /* must be a LEA */
+ if (! is_ia32_Lea(irn))
+ return;
+
+ am_flav = get_ia32_am_flavour(irn);
+
+ /* only some LEAs can be transformed to an Add */
+ if (am_flav != ia32_am_B && am_flav != ia32_am_OB && am_flav != ia32_am_OI && am_flav != ia32_am_BI)
+ return;
+
+ noreg = ia32_new_NoReg_gp(cg);
+ nomem = new_rd_NoMem(cg->irg);
+ op1 = noreg;
+ op2 = noreg;
+ base = get_irn_n(irn, 0);
+ index = get_irn_n(irn,1);
+
+ offs = get_ia32_am_offs(irn);
+
+ /* offset has a explicit sign -> we need to skip + */
+ if (offs && offs[0] == '+')
+ offs++;
+
+ out_reg = arch_get_irn_register(cg->arch_env, irn);
+ base_reg = arch_get_irn_register(cg->arch_env, base);
+ index_reg = arch_get_irn_register(cg->arch_env, index);
+
+ tenv.block = get_nodes_block(irn);
+ tenv.dbg = get_irn_dbg_info(irn);
+ tenv.irg = cg->irg;
+ tenv.irn = irn;
+ tenv.mod = cg->mod;
+ tenv.mode = get_irn_mode(irn);
+ tenv.cg = cg;
+
+ switch(get_ia32_am_flavour(irn)) {
+ case ia32_am_B:
+ /* out register must be same as base register */
+ if (! REGS_ARE_EQUAL(out_reg, base_reg))
+ return;
+
+ op1 = base;
+ break;
+ case ia32_am_OB:
+ /* out register must be same as base register */
+ if (! REGS_ARE_EQUAL(out_reg, base_reg))
+ return;
+
+ op1 = base;
+ imm = 1;
+ break;
+ case ia32_am_OI:
+ /* out register must be same as index register */
+ if (! REGS_ARE_EQUAL(out_reg, index_reg))
+ return;
+
+ op1 = index;
+ imm = 1;
+ break;
+ case ia32_am_BI:
+ /* out register must be same as one in register */
+ if (REGS_ARE_EQUAL(out_reg, base_reg)) {
+ op1 = base;
+ op2 = index;
+ }
+ else if (REGS_ARE_EQUAL(out_reg, index_reg)) {
+ op1 = index;
+ op2 = base;
+ }
+ else {
+ /* in registers a different from out -> no Add possible */
+ return;
+ }
+ default:
+ break;
+ }
+
+ res = new_rd_ia32_Add(tenv.dbg, tenv.irg, tenv.block, noreg, noreg, op1, op2, nomem, mode_T);
+ arch_set_irn_register(cg->arch_env, res, out_reg);
+ set_ia32_op_type(res, ia32_Normal);
+
+ if (imm)
+ set_ia32_cnst(res, offs);
+
+ SET_IA32_ORIG_NODE(res, get_old_node_name(&tenv));
+
+ /* add Add to schedule */
+ sched_add_before(irn, res);
+
+ res = new_rd_Proj(tenv.dbg, tenv.irg, tenv.block, res, tenv.mode, 0);
+
+ /* add result Proj to schedule */
+ sched_add_before(irn, res);
+
+ /* remove the old LEA */
+ sched_remove(irn);
+
+ /* exchange the Add and the LEA */
+ exchange(irn, res);
+}
+
/**
* Transforms the given firm node (and maybe some other related nodes)
* into one or more assembler nodes.
*/
void ia32_transform_node(ir_node *node, void *env) {
ia32_code_gen_t *cgenv = (ia32_code_gen_t *)env;
- opcode code = get_irn_opcode(node);
+ opcode code;
ir_node *asm_node = NULL;
ia32_transform_env_t tenv;
DBG((tenv.mod, LEVEL_1, "check %+F ... ", node));
+ code = get_irn_opcode(node);
switch (code) {
BINOP(Add);
BINOP(Sub);
projects / libfirm / blobdiff