#include "../benode_t.h"
#include "../besched.h"
#include "../beabi.h"
+#include "../beutil.h"
#include "bearch_ia32_t.h"
#include "ia32_nodes_attr.h"
* Returns 1 if irn is a Const representing 0, 0 otherwise
*/
static INLINE int is_ia32_Const_0(ir_node *irn) {
- return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
- classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_NULL : 0;
+ return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
+ && tarval_is_null(get_ia32_Immop_tarval(irn));
}
/**
* Returns 1 if irn is a Const representing 1, 0 otherwise
*/
static INLINE int is_ia32_Const_1(ir_node *irn) {
- return (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_Const) ?
- classify_tarval(get_ia32_Immop_tarval(irn)) == TV_CLASSIFY_ONE : 0;
-}
-
-/**
- * Gets the Proj with number pn from irn.
- */
-static ir_node *get_proj_for_pn(const ir_node *irn, long pn) {
- const ir_edge_t *edge;
- ir_node *proj;
- assert(get_irn_mode(irn) == mode_T && "need mode_T");
-
- foreach_out_edge(irn, edge) {
- proj = get_edge_src_irn(edge);
-
- if (get_Proj_proj(proj) == pn)
- return proj;
- }
-
- return NULL;
+ return is_ia32_irn(irn) && is_ia32_Const(irn) && get_ia32_immop_type(irn) == ia32_ImmConst
+ && tarval_is_one(get_ia32_Immop_tarval(irn));
}
/**
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_flavour(load, ia32_am_N);
set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
- res = new_r_Proj(irg, block, load, mode_D, pn_ia32_vfld_res);
+ res = new_r_Proj(irg, block, load, mode_E, pn_ia32_vfld_res);
}
} else {
floatent = get_entity_for_tv(env->cg, node);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_flavour(load, ia32_am_N);
set_ia32_am_sc(load, ia32_get_ent_ident(floatent));
- res = new_r_Proj(irg, block, load, mode_D, pn_ia32_xLoad_res);
+ res = new_r_Proj(irg, block, load, mode_E, pn_ia32_xLoad_res);
}
set_ia32_ls_mode(load, mode);
ir_node *conv = new_rd_ia32_Conv_FP2FP(dbg, irg, block, noreg, noreg, in, nomem);
set_ia32_am_support(conv, ia32_am_Source);
- set_ia32_ls_mode(conv, mode_D);
+ set_ia32_ls_mode(conv, mode_E);
SET_IA32_ORIG_NODE(conv, ia32_get_old_node_name(cg, old_node));
return conv;
tp_name = names[kct].tp_name;
cnst_str = names[kct].cnst_str;
- mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
+ //mode = kct == ia32_SSIGN || kct == ia32_SABS ? mode_Iu : mode_Lu;
+ mode = mode_LLu;
tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
tp = new_type_primitive(new_id_from_str(tp_name), mode);
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
/* exchange left/right */
set_irn_n(node, in1, right);
set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
- set_ia32_Immop_attr(node, left);
+ copy_ia32_Immop_attr(node, left);
} else if(is_ia32_Cnst(right)) {
set_irn_n(node, in2, ia32_get_admissible_noreg(env->cg, node, in2));
- set_ia32_Immop_attr(node, right);
+ copy_ia32_Immop_attr(node, right);
} else {
return;
}
ir_node *new_op2 = transform_node(env, op2);
new_node = func(dbg, irg, block, noreg_gp, noreg_gp, new_op1, new_op2, nomem);
- if(func == new_rd_ia32_Mul) {
+ if(func == new_rd_ia32_IMul) {
set_ia32_am_support(new_node, ia32_am_Source);
} else {
set_ia32_am_support(new_node, ia32_am_Full);
DB((mod, LEVEL_1, "Shift/Rot with immediate ..."));
new_op = func(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
- set_ia32_Immop_attr(new_op, imm_op);
+ copy_ia32_Immop_attr(new_op, imm_op);
} else {
/* This is a normal shift/rot */
DB((mod, LEVEL_1, "Shift/Rot binop ..."));
}
-/**
- * Creates an ia32 Add with immediate.
- *
- * @param env The transformation environment
- * @param expr_op The expression operator
- * @param const_op The constant
- * @return the created ia32 Add node
- */
-static ir_node *gen_imm_Add(ia32_transform_env_t *env, ir_node *node,
- ir_node *expr_op, ir_node *const_op) {
- ir_node *new_op = NULL;
- tarval *tv = get_ia32_Immop_tarval(const_op);
- ir_graph *irg = env->irg;
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = transform_node(env, get_nodes_block(node));
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *nomem = new_NoMem();
- int normal_add = 1;
- tarval_classification_t class_tv, class_negtv;
- DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
-
- /* try to optimize to inc/dec */
- if ((env->cg->opt & IA32_OPT_INCDEC) && tv && (get_ia32_op_type(const_op) == ia32_Const)) {
- /* optimize tarvals */
- class_tv = classify_tarval(tv);
- class_negtv = classify_tarval(tarval_neg(tv));
-
- if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
- DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
- new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
- normal_add = 0;
- }
- else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
- DB((mod, LEVEL_2, "Add(-1) to Dec ... "));
- new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
- normal_add = 0;
- }
- }
-
- if (normal_add) {
- new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
- set_ia32_Immop_attr(new_op, const_op);
- set_ia32_commutative(new_op);
- }
-
- return new_op;
-}
-
/**
* Creates an ia32 Add.
*
else
return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfadd);
}
- else {
- /* integer ADD */
- if (!expr_op) {
- /* No expr_op means, that we have two const - one symconst and */
- /* one tarval or another symconst - because this case is not */
- /* covered by constant folding */
- /* We need to check for: */
- /* 1) symconst + const -> becomes a LEA */
- /* 2) symconst + symconst -> becomes a const + LEA as the elf */
- /* linker doesn't support two symconsts */
-
- if (get_ia32_op_type(new_op1) == ia32_SymConst
- && get_ia32_op_type(new_op2) == ia32_SymConst) {
- /* this is the 2nd case */
- new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op2));
- set_ia32_am_flavour(new_op, ia32_am_OB);
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- } else {
- /* this is the 1st case */
- if (get_ia32_op_type(new_op1) == ia32_SymConst) {
- tarval *tv = get_ia32_cnst_tv(new_op2);
- long offs = get_tarval_long(tv);
-
- new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
-
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op1));
- add_ia32_am_offs_int(new_op, offs);
- set_ia32_am_flavour(new_op, ia32_am_O);
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else if (get_ia32_op_type(new_op2) == ia32_SymConst) {
- tarval *tv = get_ia32_cnst_tv(new_op1);
- long offs = get_tarval_long(tv);
-
- new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
-
- add_ia32_am_offs_int(new_op, offs);
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op2));
- set_ia32_am_flavour(new_op, ia32_am_O);
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else {
- tarval *tv1 = get_ia32_cnst_tv(new_op1);
- tarval *tv2 = get_ia32_cnst_tv(new_op2);
- tarval *restv = tarval_add(tv1, tv2);
+ /* integer ADD */
+ if (!expr_op) {
+ ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
+ ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
+
+ /* No expr_op means, that we have two const - one symconst and */
+ /* one tarval or another symconst - because this case is not */
+ /* covered by constant folding */
+ /* We need to check for: */
+ /* 1) symconst + const -> becomes a LEA */
+ /* 2) symconst + symconst -> becomes a const + LEA as the elf */
+ /* linker doesn't support two symconsts */
+
+ if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
+ /* this is the 2nd case */
+ new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
+ set_ia32_am_flavour(new_op, ia32_am_OB);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+
+ DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
+ } else if (tp1 == ia32_ImmSymConst) {
+ tarval *tv = get_ia32_Immop_tarval(new_op2);
+ long offs = get_tarval_long(tv);
- DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
+ new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
+ DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- new_op = new_rd_ia32_Const(dbg, irg, block);
- set_ia32_Const_tarval(new_op, restv);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- }
- }
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
+ add_ia32_am_offs_int(new_op, offs);
+ set_ia32_am_flavour(new_op, ia32_am_O);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ } else if (tp2 == ia32_ImmSymConst) {
+ tarval *tv = get_ia32_Immop_tarval(new_op1);
+ long offs = get_tarval_long(tv);
- return new_op;
- }
- else if (imm_op) {
- /* This is expr + const */
- new_op = gen_imm_Add(env, node, expr_op, imm_op);
+ new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
+ DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
+
+ add_ia32_am_offs_int(new_op, offs);
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
+ set_ia32_am_flavour(new_op, ia32_am_O);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ } else {
+ tarval *tv1 = get_ia32_Immop_tarval(new_op1);
+ tarval *tv2 = get_ia32_Immop_tarval(new_op2);
+ tarval *restv = tarval_add(tv1, tv2);
+
+ DEBUG_ONLY(ir_fprintf(stderr, "Warning: add with 2 consts not folded: %+F\n", node));
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Dest);
+ new_op = new_rd_ia32_Const(dbg, irg, block);
+ set_ia32_Const_tarval(new_op, restv);
+ DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
}
- else {
- /* This is a normal add */
- new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Full);
- set_ia32_commutative(new_op);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ return new_op;
+ } else if (imm_op) {
+ if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
+ tarval_classification_t class_tv, class_negtv;
+ tarval *tv = get_ia32_Immop_tarval(imm_op);
+
+ /* optimize tarvals */
+ class_tv = classify_tarval(tv);
+ class_negtv = classify_tarval(tarval_neg(tv));
+
+ if (class_tv == TV_CLASSIFY_ONE) { /* + 1 == INC */
+ DB((env->mod, LEVEL_2, "Add(1) to Inc ... "));
+ new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ return new_op;
+ } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) { /* + (-1) == DEC */
+ DB((env->mod, LEVEL_2, "Add(-1) to Dec ... "));
+ new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ return new_op;
+ }
}
}
+ /* This is a normal add */
+ new_op = new_rd_ia32_Add(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
+
+ /* set AM support */
+ set_ia32_am_support(new_op, ia32_am_Full);
+ set_ia32_commutative(new_op);
+
+ fold_immediate(env, new_op, 2, 3);
+
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
return new_op;
}
+#if 0
+static ir_node *create_ia32_Mul(ia32_transform_env_t *env, ir_node *node) {
+ ir_graph *irg = env->irg;
+ dbg_info *dbg = get_irn_dbg_info(node);
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *op1 = get_Mul_left(node);
+ ir_node *op2 = get_Mul_right(node);
+ ir_node *new_op1 = transform_node(env, op1);
+ ir_node *new_op2 = transform_node(env, op2);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *proj_EAX, *proj_EDX, *res;
+ ir_node *in[1];
+
+ res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
+ set_ia32_commutative(res);
+ set_ia32_am_support(res, ia32_am_Source);
+
+ /* imediates are not supported, so no fold_immediate */
+ proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
+ proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
+
+ /* keep EAX */
+ in[0] = proj_EDX;
+ be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
+
+ return proj_EAX;
+}
+#endif
/**
static ir_node *gen_Mul(ia32_transform_env_t *env, ir_node *node) {
ir_node *op1 = get_Mul_left(node);
ir_node *op2 = get_Mul_right(node);
- ir_node *new_op;
ir_mode *mode = get_irn_mode(node);
if (mode_is_float(mode)) {
FP_USED(env->cg);
if (USE_SSE2(env->cg))
- new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
+ return gen_binop_float(env, node, op1, op2, new_rd_ia32_xMul);
else
- new_op = gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
- }
- else {
- new_op = gen_binop(env, node, op1, op2, new_rd_ia32_Mul);
+ return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfmul);
}
- return new_op;
+ // for the lower 32bit of the result it doesn't matter whether we use
+ // signed or unsigned multiplication so we use IMul as it has fewer
+ // constraints
+ return gen_binop(env, node, op1, op2, new_rd_ia32_IMul);
}
-
-
/**
* Creates an ia32 Mulh.
* Note: Mul produces a 64Bit result and Mulh returns the upper 32 bit of
ir_node *new_op1 = transform_node(env, op1);
ir_node *new_op2 = transform_node(env, op2);
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *proj_EAX, *proj_EDX, *mulh;
+ ir_node *proj_EAX, *proj_EDX, *res;
ir_mode *mode = get_irn_mode(node);
ir_node *in[1];
assert(!mode_is_float(mode) && "Mulh with float not supported");
- mulh = new_rd_ia32_Mulh(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
- set_ia32_commutative(mulh);
- set_ia32_am_support(mulh, ia32_am_Source);
+ if(mode_is_signed(mode)) {
+ res = new_rd_ia32_IMul1OP(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
+ } else {
+ res = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_op1, new_op2, new_NoMem());
+ }
- /* imediates are not supported, so no fold_immediate */
- proj_EAX = new_rd_Proj(dbg, irg, block, mulh, mode_Iu, pn_EAX);
- proj_EDX = new_rd_Proj(dbg, irg, block, mulh, mode_Iu, pn_EDX);
+ set_ia32_commutative(res);
+ set_ia32_am_support(res, ia32_am_Source);
+
+ set_ia32_am_support(res, ia32_am_Source);
+
+ proj_EAX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
+ proj_EDX = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
/* keep EAX */
in[0] = proj_EAX;
ir_mode *mode = get_irn_mode(node);
assert(! mode_is_float(mode));
- return gen_binop(env, node, op1, op2, new_rd_ia32_Eor);
+ return gen_binop(env, node, op1, op2, new_rd_ia32_Xor);
}
}
-
-/**
- * Creates an ia32 Sub with immediate.
- *
- * @param env The transformation environment
- * @param expr_op The first operator
- * @param const_op The constant operator
- * @return The created ia32 Sub node
- */
-static ir_node *gen_imm_Sub(ia32_transform_env_t *env, ir_node *node,
- ir_node *expr_op, ir_node *const_op) {
- ir_node *new_op = NULL;
- tarval *tv = get_ia32_Immop_tarval(const_op);
- ir_graph *irg = env->irg;
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = transform_node(env, get_nodes_block(node));
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
- ir_node *nomem = new_NoMem();
- int normal_sub = 1;
- tarval_classification_t class_tv, class_negtv;
- DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
-
- /* try to optimize to inc/dec */
- if ((env->cg->opt & IA32_OPT_INCDEC) && tv && (get_ia32_op_type(const_op) == ia32_Const)) {
- /* optimize tarvals */
- class_tv = classify_tarval(tv);
- class_negtv = classify_tarval(tarval_neg(tv));
-
- if (class_tv == TV_CLASSIFY_ONE) { /* - 1 == DEC */
- DB((mod, LEVEL_2, "Sub(1) to Dec ... "));
- new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
- normal_sub = 0;
- }
- else if (class_negtv == TV_CLASSIFY_ONE) { /* - (-1) == Sub */
- DB((mod, LEVEL_2, "Sub(-1) to Inc ... "));
- new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
- normal_sub = 0;
- }
- }
-
- if (normal_sub) {
- new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, expr_op, noreg, nomem);
- set_ia32_Immop_attr(new_op, const_op);
- }
-
- return new_op;
-}
-
/**
* Creates an ia32 Sub.
*
return gen_binop_float(env, node, op1, op2, new_rd_ia32_xSub);
else
return gen_binop_float(env, node, op1, op2, new_rd_ia32_vfsub);
- } else {
- /* integer SUB */
- if (! expr_op) {
- /* No expr_op means, that we have two const - one symconst and */
- /* one tarval or another symconst - because this case is not */
- /* covered by constant folding */
- /* We need to check for: */
- /* 1) symconst - const -> becomes a LEA */
- /* 2) symconst - symconst -> becomes a const - LEA as the elf */
- /* linker doesn't support two symconsts */
-
- if (get_ia32_op_type(new_op1) == ia32_SymConst
- && get_ia32_op_type(new_op2) == ia32_SymConst) {
- /* this is the 2nd case */
- new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
- set_ia32_am_sc(new_op, get_ia32_id_cnst(op2));
- set_ia32_am_sc_sign(new_op);
- set_ia32_am_flavour(new_op, ia32_am_OB);
-
- DBG_OPT_LEA3(op1, op2, node, new_op);
- } else {
- /* this is the 1st case */
- new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
-
- DBG_OPT_LEA3(op1, op2, node, new_op);
-
- if (get_ia32_op_type(new_op1) == ia32_SymConst) {
- tarval *tv = get_ia32_cnst_tv(new_op2);
- long offs = get_tarval_long(tv);
-
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op1));
- add_ia32_am_offs_int(new_op, -offs);
- set_ia32_am_flavour(new_op, ia32_am_O);
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else if (get_ia32_op_type(new_op2) == ia32_SymConst) {
- tarval *tv = get_ia32_cnst_tv(new_op1);
- long offs = get_tarval_long(tv);
-
- add_ia32_am_offs_int(new_op, offs);
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_op2));
- set_ia32_am_sc_sign(new_op);
- set_ia32_am_flavour(new_op, ia32_am_O);
- set_ia32_am_support(new_op, ia32_am_Source);
- set_ia32_op_type(new_op, ia32_AddrModeS);
- } else {
- tarval *tv1 = get_ia32_cnst_tv(new_op1);
- tarval *tv2 = get_ia32_cnst_tv(new_op2);
- tarval *restv = tarval_sub(tv1, tv2);
+ }
- DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
+ /* integer SUB */
+ if (! expr_op) {
+ ia32_immop_type_t tp1 = get_ia32_immop_type(new_op1);
+ ia32_immop_type_t tp2 = get_ia32_immop_type(new_op2);
+
+ /* No expr_op means, that we have two const - one symconst and */
+ /* one tarval or another symconst - because this case is not */
+ /* covered by constant folding */
+ /* We need to check for: */
+ /* 1) symconst - const -> becomes a LEA */
+ /* 2) symconst - symconst -> becomes a const - LEA as the elf */
+ /* linker doesn't support two symconsts */
+ if (tp1 == ia32_ImmSymConst && tp2 == ia32_ImmSymConst) {
+ /* this is the 2nd case */
+ new_op = new_rd_ia32_Lea(dbg, irg, block, new_op1, noreg);
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(op2));
+ set_ia32_am_sc_sign(new_op);
+ set_ia32_am_flavour(new_op, ia32_am_OB);
+
+ DBG_OPT_LEA3(op1, op2, node, new_op);
+ } else if (tp1 == ia32_ImmSymConst) {
+ tarval *tv = get_ia32_Immop_tarval(new_op2);
+ long offs = get_tarval_long(tv);
- new_op = new_rd_ia32_Const(dbg, irg, block);
- set_ia32_Const_tarval(new_op, restv);
- DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
- }
- }
+ new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
+ DBG_OPT_LEA3(op1, op2, node, new_op);
- return new_op;
- } else if (imm_op) {
- /* This is expr - const */
- new_op = gen_imm_Sub(env, node, expr_op, imm_op);
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op1));
+ add_ia32_am_offs_int(new_op, -offs);
+ set_ia32_am_flavour(new_op, ia32_am_O);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
+ } else if (tp2 == ia32_ImmSymConst) {
+ tarval *tv = get_ia32_Immop_tarval(new_op1);
+ long offs = get_tarval_long(tv);
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Dest);
+ new_op = new_rd_ia32_Lea(dbg, irg, block, noreg, noreg);
+ DBG_OPT_LEA3(op1, op2, node, new_op);
+
+ add_ia32_am_offs_int(new_op, offs);
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_op2));
+ set_ia32_am_sc_sign(new_op);
+ set_ia32_am_flavour(new_op, ia32_am_O);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ set_ia32_op_type(new_op, ia32_AddrModeS);
} else {
- /* This is a normal sub */
- new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
+ tarval *tv1 = get_ia32_Immop_tarval(new_op1);
+ tarval *tv2 = get_ia32_Immop_tarval(new_op2);
+ tarval *restv = tarval_sub(tv1, tv2);
+
+ DEBUG_ONLY(ir_fprintf(stderr, "Warning: sub with 2 consts not folded: %+F\n", node));
- /* set AM support */
- set_ia32_am_support(new_op, ia32_am_Full);
+ new_op = new_rd_ia32_Const(dbg, irg, block);
+ set_ia32_Const_tarval(new_op, restv);
+ DBG_OPT_LEA3(new_op1, new_op2, node, new_op);
+ }
+
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ return new_op;
+ } else if (imm_op) {
+ if((env->cg->opt & IA32_OPT_INCDEC) && get_ia32_immop_type(imm_op) == ia32_ImmConst) {
+ tarval_classification_t class_tv, class_negtv;
+ tarval *tv = get_ia32_Immop_tarval(imm_op);
+
+ /* optimize tarvals */
+ class_tv = classify_tarval(tv);
+ class_negtv = classify_tarval(tarval_neg(tv));
+
+ if (class_tv == TV_CLASSIFY_ONE) {
+ DB((env->mod, LEVEL_2, "Sub(1) to Dec ... "));
+ new_op = new_rd_ia32_Dec(dbg, irg, block, noreg, noreg, expr_op, nomem);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ return new_op;
+ } else if (class_tv == TV_CLASSIFY_ALL_ONE || class_negtv == TV_CLASSIFY_ONE) {
+ DB((env->mod, LEVEL_2, "Sub(-1) to Inc ... "));
+ new_op = new_rd_ia32_Inc(dbg, irg, block, noreg, noreg, expr_op, nomem);
+ SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
+ return new_op;
+ }
}
}
+ /* This is a normal sub */
+ new_op = new_rd_ia32_Sub(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
+
+ /* set AM support */
+ set_ia32_am_support(new_op, ia32_am_Full);
+
+ fold_immediate(env, new_op, 2, 3);
+
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
return new_op;
ir_node *in_keep[1];
ir_node *mem, *new_mem;
ir_node *projs[pn_DivMod_max];
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_node *new_dividend = transform_node(env, dividend);
ir_node *new_divisor = transform_node(env, divisor);
switch (dm_flav) {
case flavour_Div:
mem = get_Div_mem(node);
- mode = get_irn_mode(get_proj_for_pn(node, pn_Div_res));
+ mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Div_res));
break;
case flavour_Mod:
mem = get_Mod_mem(node);
- mode = get_irn_mode(get_proj_for_pn(node, pn_Mod_res));
+ mode = get_irn_mode(be_get_Proj_for_pn(node, pn_Mod_res));
break;
case flavour_DivMod:
mem = get_DivMod_mem(node);
- proj_div = get_proj_for_pn(node, pn_DivMod_res_div);
- proj_mod = get_proj_for_pn(node, pn_DivMod_res_mod);
+ proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
+ proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
mode = proj_div ? get_irn_mode(proj_div) : get_irn_mode(proj_mod);
break;
default:
if (mode_is_signed(mode)) {
/* in signed mode, we need to sign extend the dividend */
- cltd = new_rd_ia32_Cdq(dbg, irg, block, new_dividend);
- new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cdq_EAX);
- edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cdq_EDX);
- }
- else {
+ cltd = new_rd_ia32_Cltd(dbg, irg, block, new_dividend);
+ new_dividend = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EAX);
+ edx_node = new_rd_Proj(dbg, irg, block, cltd, mode_Iu, pn_ia32_Cltd_EDX);
+ } else {
edx_node = new_rd_ia32_Const(dbg, irg, block);
add_irn_dep(edx_node, be_abi_get_start_barrier(env->cg->birg->abi));
- set_ia32_Const_type(edx_node, ia32_Const);
set_ia32_Immop_tarval(edx_node, get_tarval_null(mode_Iu));
}
if(mode_is_signed(mode)) {
- res = new_rd_ia32_IDiv(dbg, irg, block, new_dividend, new_divisor, edx_node, new_mem, dm_flav);
+ res = new_rd_ia32_IDiv(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
} else {
- res = new_rd_ia32_Div(dbg, irg, block, new_dividend, new_divisor, edx_node, new_mem, dm_flav);
+ res = new_rd_ia32_Div(dbg, irg, block, noreg, noreg, new_dividend, edx_node, new_divisor, new_mem, dm_flav);
}
+
+ /* Matze: code can't handle this at the moment... */
+#if 0
+ /* set AM support */
+ set_ia32_am_support(res, ia32_am_Source);
+#endif
+
set_ia32_n_res(res, 2);
/* Only one proj is used -> We must add a second proj and */
break;
case iro_DivMod:
/* check, which Proj-Keep, we need to add */
- proj_div = get_proj_for_pn(node, pn_DivMod_res_div);
- proj_mod = get_proj_for_pn(node, pn_DivMod_res_mod);
+ proj_div = be_get_Proj_for_pn(node, pn_DivMod_res_div);
+ proj_mod = be_get_Proj_for_pn(node, pn_DivMod_res_mod);
if (proj_div && proj_mod) {
/* nothing to be done */
if (is_ia32_xConst(new_op2)) {
new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, noreg, nomem);
set_ia32_am_support(new_op, ia32_am_None);
- set_ia32_Immop_attr(new_op, new_op2);
+ copy_ia32_Immop_attr(new_op, new_op2);
} else {
new_op = new_rd_ia32_xDiv(dbg, irg, block, noreg, noreg, new_op1, new_op2, nomem);
// Matze: disabled for now, spillslot coalescer fails
/**
- * Creates an ia32 Shrs.
+ * Creates an ia32 Sar.
*
* @param env The transformation environment
* @return The created ia32 Shrs node
*/
static ir_node *gen_Shrs(ia32_transform_env_t *env, ir_node *node) {
return gen_shift_binop(env, node, get_Shrs_left(node),
- get_Shrs_right(node), new_rd_ia32_Shrs);
+ get_Shrs_right(node), new_rd_ia32_Sar);
}
*/
static ir_node *gen_RotL(ia32_transform_env_t *env, ir_node *node,
ir_node *op1, ir_node *op2) {
- return gen_shift_binop(env, node, op1, op2, new_rd_ia32_RotL);
+ return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Rol);
}
*/
static ir_node *gen_RotR(ia32_transform_env_t *env, ir_node *node, ir_node *op1,
ir_node *op2) {
- return gen_shift_binop(env, node, op1, op2, new_rd_ia32_RotR);
+ return gen_shift_binop(env, node, op1, op2, new_rd_ia32_Ror);
}
operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
that means we can create a RotR instead of an Add and a RotL */
- if (is_Proj(op2)) {
- ir_node *pred = get_Proj_pred(op2);
-
- if (is_ia32_Add(pred)) {
- ir_node *pred_pred = get_irn_n(pred, 2);
- tarval *tv = get_ia32_Immop_tarval(pred);
+ if (get_irn_op(op2) == op_Add) {
+ ir_node *add = op2;
+ ir_node *left = get_Add_left(add);
+ ir_node *right = get_Add_right(add);
+ if (is_Const(right)) {
+ tarval *tv = get_Const_tarval(right);
ir_mode *mode = get_irn_mode(node);
long bits = get_mode_size_bits(mode);
- if (is_Proj(pred_pred)) {
- pred_pred = get_Proj_pred(pred_pred);
- }
-
- if (is_ia32_Minus(pred_pred) &&
- tarval_is_long(tv) &&
- get_tarval_long(tv) == bits)
+ if (get_irn_op(left) == op_Minus &&
+ tarval_is_long(tv) &&
+ get_tarval_long(tv) == bits)
{
DB((env->mod, LEVEL_1, "RotL into RotR ... "));
- rotate = gen_RotR(env, node, op1, get_irn_n(pred_pred, 2));
+ rotate = gen_RotR(env, node, op1, get_Minus_op(left));
}
-
}
}
- if (!rotate) {
+ if (rotate == NULL) {
rotate = gen_RotL(env, node, op1, op2);
}
ir_node *noreg_fp = ia32_new_NoReg_fp(env->cg);
ir_node *nomem = new_rd_NoMem(irg);
- res = new_rd_ia32_xEor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
+ res = new_rd_ia32_xXor(dbg, irg, block, noreg_gp, noreg_gp, new_op, noreg_fp, nomem);
size = get_mode_size_bits(mode);
name = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
res = new_rd_ia32_vfchs(dbg, irg, block, new_op);
}
} else {
- res = gen_unop(env, node, op, new_rd_ia32_Minus);
+ res = gen_unop(env, node, op, new_rd_ia32_Neg);
}
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
}
}
else {
- res = new_rd_ia32_Cdq(dbg, irg, block, new_op);
+ res = new_rd_ia32_Cltd(dbg, irg, block, new_op);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
p_eax = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EAX);
p_edx = new_rd_Proj(dbg, irg, block, res, mode_Iu, pn_EDX);
- res = new_rd_ia32_Eor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
+ res = new_rd_ia32_Xor(dbg, irg, block, noreg_gp, noreg_gp, p_eax, p_edx, nomem);
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
res = new_rd_ia32_Sub(dbg, irg, block, noreg_gp, noreg_gp, res, p_edx, nomem);
check for special case: the loaded value might not be used (optimized, volatile, ...)
we add a Proj + Keep for volatile loads and ignore all other cases
*/
- if (! get_proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
+ if (! be_get_Proj_for_pn(node, pn_Load_res) && get_Load_volatility(node) == volatility_is_volatile) {
/* add a result proj and a Keep to produce a pseudo use */
ir_node *proj = new_r_Proj(irg, block, node, mode_Iu, pn_ia32_Load_res);
be_new_Keep(arch_get_irn_reg_class(env->cg->arch_env, proj, -1), irg, block, 1, &proj);
/* base is a constant address */
if (is_imm) {
- if (get_ia32_op_type(new_ptr) == ia32_SymConst) {
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_ptr));
+ if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
am_flav = ia32_am_N;
} else {
- tarval *tv = get_ia32_cnst_tv(new_ptr);
+ tarval *tv = get_ia32_Immop_tarval(new_ptr);
long offs = get_tarval_long(tv);
add_ia32_am_offs_int(new_op, offs);
int is_imm = 0;
ir_node *new_op;
ia32_am_flavour_t am_flav = ia32_am_B;
- ia32_immop_type_t immop = ia32_ImmNone;
-
- if (! mode_is_float(mode)) {
- /* in case of storing a const (but not a symconst) -> make it an attribute */
- if (is_ia32_Cnst(new_val)) {
- switch (get_ia32_op_type(new_val)) {
- case ia32_Const:
- immop = ia32_ImmConst;
- break;
- case ia32_SymConst:
- immop = ia32_ImmSymConst;
- break;
- default:
- assert(0 && "unsupported Const type");
- }
- sval = noreg;
- }
+
+ if (is_ia32_Const(new_val)) {
+ assert(!mode_is_float(mode));
+ sval = noreg;
}
/* address might be a constant (symconst or absolute address) */
FP_USED(env->cg);
if (USE_SSE2(env->cg)) {
new_op = new_rd_ia32_xStore(dbg, irg, block, sptr, noreg, sval, new_mem);
- }
- else {
+ } else {
new_op = new_rd_ia32_vfst(dbg, irg, block, sptr, noreg, sval, new_mem);
}
- }
- else if (get_mode_size_bits(mode) == 8) {
+ } else if (get_mode_size_bits(mode) == 8) {
new_op = new_rd_ia32_Store8Bit(dbg, irg, block, sptr, noreg, sval, new_mem);
- }
- else {
+ } else {
new_op = new_rd_ia32_Store(dbg, irg, block, sptr, noreg, sval, new_mem);
}
/* stored const is an immediate value */
- if (! mode_is_float(mode) && is_ia32_Cnst(new_val)) {
- set_ia32_Immop_attr(new_op, new_val);
+ if (is_ia32_Const(new_val)) {
+ assert(!mode_is_float(mode));
+ copy_ia32_Immop_attr(new_op, new_val);
}
/* base is an constant address */
if (is_imm) {
- if (get_ia32_op_type(new_ptr) == ia32_SymConst) {
- set_ia32_am_sc(new_op, get_ia32_id_cnst(new_ptr));
+ if (get_ia32_immop_type(new_ptr) == ia32_ImmSymConst) {
+ set_ia32_am_sc(new_op, get_ia32_Immop_symconst(new_ptr));
am_flav = ia32_am_N;
- }
- else {
- tarval *tv = get_ia32_cnst_tv(new_ptr);
+ } else {
+ tarval *tv = get_ia32_Immop_tarval(new_ptr);
long offs = get_tarval_long(tv);
add_ia32_am_offs_int(new_op, offs);
set_ia32_op_type(new_op, ia32_AddrModeD);
set_ia32_am_flavour(new_op, am_flav);
set_ia32_ls_mode(new_op, mode);
- set_ia32_immop_type(new_op, immop);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
}
if ((pnc == pn_Cmp_Eq || pnc == pn_Cmp_Lg) && mode_is_int(get_irn_mode(expr))) {
- if (get_ia32_op_type(cnst) == ia32_Const &&
+ if (get_ia32_immop_type(cnst) == ia32_ImmConst &&
classify_tarval(get_ia32_Immop_tarval(cnst)) == TV_CLASSIFY_NULL)
{
/* a Cmp A =/!= 0 */
ir_node *op1 = expr;
ir_node *op2 = expr;
- const char *cnst = NULL;
+ int is_and = 0;
/* check, if expr is an only once used And operation */
if (is_ia32_And(expr) && get_irn_n_edges(expr)) {
op1 = get_irn_n(expr, 2);
op2 = get_irn_n(expr, 3);
- cnst = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr)) ? get_ia32_cnst(expr) : NULL;
+ is_and = (is_ia32_ImmConst(expr) || is_ia32_ImmSymConst(expr));
}
res = new_rd_ia32_TestJmp(dbg, irg, block, op1, op2);
set_ia32_pncode(res, pnc);
- if (cnst) {
+ if (is_and) {
copy_ia32_Immop_attr(res, expr);
}
else {
res = new_rd_ia32_CondJmp(dbg, irg, block, noreg, noreg, expr, noreg, nomem);
}
- set_ia32_Immop_attr(res, cnst);
+ copy_ia32_Immop_attr(res, cnst);
}
else {
ir_mode *cmp_mode = get_irn_mode(cmp_a);
res = new_rd_ia32_Const(dbg, irg, block);
add_irn_dep(res, be_abi_get_start_barrier(env->cg->birg->abi));
- set_ia32_op_type(res, ia32_Const);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
res = new_rd_ia32_CopyB(dbg, irg, block, new_dst, new_src, res, new_mem);
else {
res = new_rd_ia32_CopyB_i(dbg, irg, block, new_dst, new_src, new_mem);
set_ia32_Immop_tarval(res, new_tarval_from_long(size, mode_Is));
- set_ia32_immop_type(res, ia32_ImmConst);
/* ok: now attach Proj's because movsd will destroy esi and edi */
in[0] = new_r_Proj(irg, block, res, dst_mode, pn_ia32_CopyB_i_DST);
/* in case the compare operands are int, we move them into xmm register */
if (! mode_is_float(get_irn_mode(cmp_a))) {
- new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_D);
- new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_D);
+ new_cmp_a = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_a, node, mode_E);
+ new_cmp_b = gen_sse_conv_int2float(cg, dbg, irg, block, new_cmp_b, node, mode_E);
pnc |= 8; /* transform integer compare to fp compare */
}
pn_res = pn_ia32_vfld_res;
}
- proj_mode = mode_D;
+ proj_mode = mode_E;
} else {
new_op = new_rd_ia32_Load(dbg, irg, block, new_ptr, noreg, nomem);
proj_mode = mode_Iu;
set_ia32_use_frame(res);
set_ia32_am_flavour(res, ia32_am_OB);
- //set_ia32_immop_type(res, ia32_ImmConst);
- //set_ia32_commutative(res);
-
SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(env->cg, node));
return res;
return new_op;
}
-/**
- * In case SSE is used we need to copy the result from FPU TOS.
- */
-static ir_node *gen_be_Call(ia32_transform_env_t *env, ir_node *node) {
- ir_graph *irg = env->irg;
- dbg_info *dbg = get_irn_dbg_info(node);
- ir_node *block = transform_node(env, get_nodes_block(node));
- ir_node *call_res = get_proj_for_pn(node, pn_be_Call_first_res);
- ir_node *call_mem = get_proj_for_pn(node, pn_be_Call_M_regular);
- ir_mode *mode;
- ir_node *nomem = new_NoMem();
- ir_node *noreg = ia32_new_NoReg_gp(env->cg);
-
- if (! call_res || ! USE_SSE2(env->cg)) {
- return duplicate_node(env, node);
- }
-
- mode = get_irn_mode(call_res);
-
- /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
- if (call_mem == NULL)
- call_mem = new_rd_Proj(dbg, irg, block, node, mode_M, pn_be_Call_M_regular);
-
- if (mode_is_float(mode)) {
- /* store st(0) onto stack */
- ir_node *frame = get_irg_frame(irg);
- ir_node *fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, nomem);
- ir_entity *ent = frame_alloc_area(get_irg_frame_type(irg), get_mode_size_bytes(mode), 16, 0);
- ir_node *sse_load, *p, *bad, *keep;
- ir_node *mproj;
- ir_node **in_keep;
- int keep_arity, i;
-
- // Matze: TODO, fix this for new transform code...
- assert(0);
-
- set_ia32_ls_mode(fstp, mode);
- set_ia32_op_type(fstp, ia32_AddrModeD);
- set_ia32_use_frame(fstp);
- set_ia32_frame_ent(fstp, ent);
- set_ia32_am_flavour(fstp, ia32_am_B);
- set_ia32_am_support(fstp, ia32_am_Dest);
-
- /* load into SSE register */
- sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, ia32_new_NoReg_gp(env->cg), fstp);
- set_ia32_ls_mode(sse_load, mode);
- set_ia32_op_type(sse_load, ia32_AddrModeS);
- set_ia32_use_frame(sse_load);
- set_ia32_frame_ent(sse_load, ent);
- set_ia32_am_flavour(sse_load, ia32_am_B);
- set_ia32_am_support(sse_load, ia32_am_Source);
- mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
- sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode, pn_ia32_xLoad_res);
-
- /* reroute all users of the result proj to the sse load */
- edges_reroute(call_res, sse_load, irg);
- edges_reroute_kind(call_res, sse_load, EDGE_KIND_DEP, irg);
-
- /* reroute all users of the old call memory to the sse load memory */
- edges_reroute(call_mem, mproj, irg);
- edges_reroute_kind(call_mem, mproj, EDGE_KIND_DEP, irg);
-
- /* now, we can set the old call mem as input of GetST0 */
- set_irn_n(fstp, 1, call_mem);
-
- /* now: create new Keep whith all former ins and one additional in - the result Proj */
-
- /* get a Proj representing a caller save register */
- p = get_proj_for_pn(node, pn_be_Call_first_res + 1);
- assert(is_Proj(p) && "Proj expected.");
-
- /* user of the the proj is the Keep */
- p = get_edge_src_irn(get_irn_out_edge_first(p));
- assert(be_is_Keep(p) && "Keep expected.");
-
- /* copy in array of the old keep and set the result proj as additional in */
- keep_arity = get_irn_arity(p) + 1;
- NEW_ARR_A(ir_node *, in_keep, keep_arity);
- in_keep[keep_arity - 1] = call_res;
- for (i = 0; i < keep_arity - 1; ++i)
- in_keep[i] = get_irn_n(p, i);
-
- /* create new keep and set the in class requirements properly */
- keep = be_new_Keep(NULL, irg, block, keep_arity, in_keep);
- for(i = 0; i < keep_arity; ++i) {
- const arch_register_class_t *cls = arch_get_irn_reg_class(env->cg->arch_env, in_keep[i], -1);
- be_node_set_reg_class(keep, i, cls);
- }
-
- /* kill the old keep */
- bad = get_irg_bad(irg);
- for (i = 0; i < keep_arity - 1; i++)
- set_irn_n(p, i, bad);
- remove_End_keepalive(get_irg_end(irg), p);
- }
-
- return duplicate_node(env, node);
-}
-
/**
* In case SSE is used we need to copy the result from XMM0 to FPU TOS before return.
*/
ir_type *res_type;
ir_mode *mode;
ir_node *frame, *sse_store, *fld, *mproj, *barrier;
- ir_node *new_barrier, *new_frame, *new_ret_val, *new_ret_mem;
+ ir_node *new_barrier, *new_ret_val, *new_ret_mem;
ir_node **in;
int pn_ret_val, pn_ret_mem, arity, i;
}
assert(get_method_n_ress(tp) == 1);
- mode = mode_D;
pn_ret_val = get_Proj_proj(ret_val);
pn_ret_mem = get_Proj_proj(ret_mem);
new_ret_mem = transform_node(env, ret_mem);
frame = get_irg_frame(irg);
- new_frame = transform_node(env, frame);
dbg = get_irn_dbg_info(barrier);
block = transform_node(env, get_nodes_block(barrier));
/* store xmm0 onto stack */
- sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, new_frame, new_ret_val, new_ret_mem);
+ sse_store = new_rd_ia32_xStoreSimple(dbg, irg, block, frame, new_ret_val, new_ret_mem);
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
set_ia32_am_support(sse_store, ia32_am_Dest);
/* load into st0 */
- fld = new_rd_ia32_SetST0(dbg, irg, block, new_frame, sse_store);
+ fld = new_rd_ia32_SetST0(dbg, irg, block, frame, sse_store);
set_ia32_ls_mode(fld, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
set_ia32_am_support(fld, ia32_am_Source);
mproj = new_r_Proj(irg, block, fld, mode_M, pn_ia32_SetST0_M);
- fld = new_r_Proj(irg, block, fld, mode_D, pn_ia32_SetST0_res);
+ fld = new_r_Proj(irg, block, fld, mode_E, pn_ia32_SetST0_res);
arch_set_irn_register(env->cg->arch_env, fld, &ia32_vfp_regs[REG_VF0]);
/* create a new barrier */
ir_node *new_sz = transform_node(env, sz);
ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
ir_node *new_sp = transform_node(env, sp);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_NoMem();
- new_op = new_rd_ia32_AddSP(dbg, irg, block, new_sp, new_sz);
- fold_immediate(env, new_op, 0, 1);
+ /* ia32 stack grows in reverse direction, make a SubSP */
+ new_op = new_rd_ia32_SubSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ fold_immediate(env, new_op, 2, 3);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
ir_node *new_sz = transform_node(env, sz);
ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
ir_node *new_sp = transform_node(env, sp);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *nomem = new_NoMem();
- new_op = new_rd_ia32_SubSP(dbg, irg, block, new_sp, new_sz);
- fold_immediate(env, new_op, 0, 1);
+ /* ia32 stack grows in reverse direction, make an AddSP */
+ new_op = new_rd_ia32_AddSP(dbg, irg, block, noreg, noreg, new_sp, new_sz, nomem);
+ set_ia32_am_support(new_op, ia32_am_Source);
+ fold_immediate(env, new_op, 2, 3);
SET_IA32_ORIG_NODE(new_op, ia32_get_old_node_name(env->cg, node));
mode = mode_Iu;
} else if(mode_is_float(mode)) {
assert(mode == mode_D || mode == mode_F);
- // all float operations are on mode_D registers
- mode = mode_D;
+ // all float operations are on mode_E registers
+ mode = mode_E;
}
/* phi nodes allow loops, so we use the old arguments for now
return gen_lowered_Store(env, node, new_rd_ia32_##op, fp_unit); \
}
-GEN_LOWERED_OP(AddC)
+GEN_LOWERED_OP(Adc)
GEN_LOWERED_OP(Add)
-GEN_LOWERED_OP(SubC)
+GEN_LOWERED_OP(Sbb)
GEN_LOWERED_OP(Sub)
-GEN_LOWERED_OP(Mul)
-GEN_LOWERED_OP(Eor)
+GEN_LOWERED_OP(IMul)
+GEN_LOWERED_OP(Xor)
GEN_LOWERED_x87_OP(vfprem)
GEN_LOWERED_x87_OP(vfmul)
GEN_LOWERED_x87_OP(vfsub)
-GEN_LOWERED_UNOP(Minus)
+GEN_LOWERED_UNOP(Neg)
GEN_LOWERED_LOAD(vfild, fp_x87)
GEN_LOWERED_LOAD(Load, fp_none)
* Transforms a l_MulS into a "real" MulS node.
*
* @param env The transformation environment
- * @return the created ia32 MulS node
+ * @return the created ia32 Mul node
*/
-static ir_node *gen_ia32_l_MulS(ia32_transform_env_t *env, ir_node *node) {
+static ir_node *gen_ia32_l_Mul(ia32_transform_env_t *env, ir_node *node) {
ir_node *noreg = ia32_new_NoReg_gp(env->cg);
ir_graph *irg = env->irg;
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *block = transform_node(env, get_nodes_block(node));
ir_node *left = get_binop_left(node);
ir_node *right = get_binop_right(node);
+ ir_node *new_left = transform_node(env, left);
+ ir_node *new_right = transform_node(env, right);
ir_node *in[2];
- /* l_MulS is already a mode_T node, so we create the MulS in the normal way */
+ /* l_Mul is already a mode_T node, so we create the Mul in the normal way */
/* and then skip the result Proj, because all needed Projs are already there. */
-
- ir_node *muls = new_rd_ia32_MulS(dbg, irg, block, noreg, noreg, left, right, new_NoMem());
+ ir_node *muls = new_rd_ia32_Mul(dbg, irg, block, noreg, noreg, new_left, new_right, new_NoMem());
clear_ia32_commutative(muls);
set_ia32_am_support(muls, ia32_am_Source);
fold_immediate(env, muls, 2, 3);
GEN_LOWERED_SHIFT_OP(Shl)
GEN_LOWERED_SHIFT_OP(Shr)
-GEN_LOWERED_SHIFT_OP(Shrs)
+GEN_LOWERED_SHIFT_OP(Sar)
/**
* Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
else
new_op = new_rd_ia32_ShrD(dbg, irg, block, noreg, noreg,
new_op1, new_op2, noreg, nomem);
- set_ia32_Immop_attr(new_op, imm_op);
+ copy_ia32_Immop_attr(new_op, imm_op);
}
else {
/* This is a normal ShiftD */
set_ia32_am_support(res, ia32_am_Source);
set_ia32_am_flavour(res, ia32_B);
set_ia32_op_type(res, ia32_AddrModeS);
- res = new_rd_Proj(dbg, irg, block, res, mode_D, pn_ia32_xLoad_res);
+ res = new_rd_Proj(dbg, irg, block, res, mode_E, pn_ia32_xLoad_res);
return res;
}
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
if(proj == pn_be_AddSP_res) {
ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
if(proj == pn_be_SubSP_res) {
ir_node *res = new_rd_Proj(dbg, irg, block, new_pred, mode_Iu, pn_ia32_AddSP_stack);
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
/* renumber the proj */
if(is_ia32_Load(new_pred)) {
}
} else if(is_ia32_xLoad(new_pred)) {
if(proj == pn_Load_res) {
- return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_xLoad_res);
+ return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_xLoad_res);
} else if(proj == pn_Load_M) {
return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_xLoad_M);
}
} else if(is_ia32_vfld(new_pred)) {
if(proj == pn_Load_res) {
- return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfld_res);
+ return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfld_res);
} else if(proj == pn_Load_M) {
return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfld_M);
}
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
switch(proj) {
case pn_CopyB_M_regular:
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
switch(proj) {
case pn_ia32_l_vfdiv_M:
return new_rd_Proj(dbg, irg, block, new_pred, mode_M, pn_ia32_vfdiv_M);
case pn_ia32_l_vfdiv_res:
- return new_rd_Proj(dbg, irg, block, new_pred, mode_D, pn_ia32_vfdiv_res);
+ return new_rd_Proj(dbg, irg, block, new_pred, mode_E, pn_ia32_vfdiv_res);
default:
assert(0);
}
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = transform_node(env, pred);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
switch(proj) {
case pn_Quot_M:
break;
case pn_Quot_res:
if(is_ia32_xDiv(new_pred)) {
- return new_rd_Proj(dbg, irg, block, new_pred, mode,
+ return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
pn_ia32_xDiv_res);
} else if(is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbg, irg, block, new_pred, mode,
+ return new_rd_Proj(dbg, irg, block, new_pred, mode_E,
pn_ia32_vfdiv_res);
}
break;
return new_rd_Unknown(irg, mode);
}
+static ir_node *gen_Proj_tls(ia32_transform_env_t *env, ir_node *node) {
+ ir_graph *irg = env->irg;
+ //dbg_info *dbg = get_irn_dbg_info(node);
+ dbg_info *dbg = NULL;
+ ir_node *block = transform_node(env, get_nodes_block(node));
+
+ ir_node *res = new_rd_ia32_LdTls(dbg, irg, block, mode_Iu);
+
+ return res;
+}
+
+static ir_node *gen_Proj_be_Call(ia32_transform_env_t *env, ir_node *node) {
+ ir_graph *irg = env->irg;
+ dbg_info *dbg = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *block = transform_node(env, get_nodes_block(node));
+ ir_node *sse_load;
+ ir_node *call = get_Proj_pred(node);
+ ir_node *new_call = transform_node(env, call);
+
+ /* The following is kinda tricky: If we're using SSE, then we have to
+ * move the result value of the call in floating point registers to an
+ * xmm register, we therefore construct a GetST0 -> xLoad sequence
+ * after the call, we have to make sure to correctly make the
+ * MemProj and the result Proj use these 2 nodes
+ */
+ if(proj == pn_be_Call_M_regular) {
+ // get new node for result, are we doing the sse load/store hack?
+ ir_node *call_res = be_get_Proj_for_pn(call, pn_be_Call_first_res);
+ ir_node *call_res_new;
+ ir_node *call_res_pred = NULL;
+
+ if(call_res != NULL) {
+ call_res_new = transform_node(env, call_res);
+ call_res_pred = get_Proj_pred(call_res_new);
+ }
+
+ if(call_res_pred == NULL || be_is_Call(call_res_pred)) {
+ return new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
+ } else {
+ assert(is_ia32_xLoad(call_res_pred));
+ return new_rd_Proj(dbg, irg, block, call_res_pred, mode_M, pn_ia32_xLoad_M);
+ }
+ }
+ if(proj == pn_be_Call_first_res && mode_is_float(mode)
+ && USE_SSE2(env->cg)) {
+ ir_node *fstp;
+ ir_node *frame = get_irg_frame(irg);
+ ir_node *noreg = ia32_new_NoReg_gp(env->cg);
+ ir_node *p;
+ ir_node *call_mem = be_get_Proj_for_pn(call, pn_be_Call_M_regular);
+ ir_node *keepin[1];
+ const arch_register_class_t *cls;
+
+ /* in case there is no memory output: create one to serialize the copy FPU -> SSE */
+ call_mem = new_rd_Proj(dbg, irg, block, new_call, mode_M, pn_be_Call_M_regular);
+
+ /* store st(0) onto stack */
+ fstp = new_rd_ia32_GetST0(dbg, irg, block, frame, noreg, call_mem);
+
+ set_ia32_ls_mode(fstp, mode);
+ set_ia32_op_type(fstp, ia32_AddrModeD);
+ set_ia32_use_frame(fstp);
+ set_ia32_am_flavour(fstp, ia32_am_B);
+ set_ia32_am_support(fstp, ia32_am_Dest);
+
+ /* load into SSE register */
+ sse_load = new_rd_ia32_xLoad(dbg, irg, block, frame, noreg, fstp);
+ set_ia32_ls_mode(sse_load, mode);
+ set_ia32_op_type(sse_load, ia32_AddrModeS);
+ set_ia32_use_frame(sse_load);
+ set_ia32_am_flavour(sse_load, ia32_am_B);
+ set_ia32_am_support(sse_load, ia32_am_Source);
+
+ //mproj = new_rd_Proj(dbg, irg, block, sse_load, mode_M, pn_ia32_xLoad_M);
+ sse_load = new_rd_Proj(dbg, irg, block, sse_load, mode_E, pn_ia32_xLoad_res);
+
+ /* now: create new Keep whith all former ins and one additional in - the result Proj */
+
+ /* get a Proj representing a caller save register */
+ p = be_get_Proj_for_pn(call, pn_be_Call_first_res + 1);
+ assert(is_Proj(p) && "Proj expected.");
+
+ /* user of the the proj is the Keep */
+ p = get_edge_src_irn(get_irn_out_edge_first(p));
+ assert(be_is_Keep(p) && "Keep expected.");
+
+ /* keep the result */
+ cls = arch_get_irn_reg_class(env->cg->arch_env, sse_load, -1);
+ keepin[0] = sse_load;
+ be_new_Keep(cls, irg, block, 1, keepin);
+
+ return sse_load;
+ }
+
+ /* transform call modes to the mode_Iu or mode_E */
+ if(mode_is_float(mode)) {
+ mode = mode_E;
+ } else if(mode != mode_M) {
+ mode = mode_Iu;
+ }
+
+ return new_rd_Proj(dbg, irg, block, new_call, mode, proj);
+}
+
static ir_node *gen_Proj(ia32_transform_env_t *env, ir_node *node) {
ir_graph *irg = env->irg;
dbg_info *dbg = get_irn_dbg_info(node);
ir_node *pred = get_Proj_pred(node);
- int proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
if(is_Store(pred) || be_is_FrameStore(pred)) {
if(proj == pn_Store_M) {
return gen_Proj_be_SubSP(env, node);
} else if(be_is_AddSP(pred)) {
return gen_Proj_be_AddSP(env, node);
- } else if(get_irn_op(pred) == op_Start && proj == pn_Start_X_initial_exec) {
- ir_node *block = get_nodes_block(pred);
- ir_node *jump;
-
- block = transform_node(env, block);
- // we exchange the ProjX with a jump
- jump = new_rd_Jmp(dbg, irg, block);
- ir_fprintf(stderr, "created jump: %+F\n", jump);
- return jump;
+ } else if(be_is_Call(pred)) {
+ return gen_Proj_be_Call(env, node);
+ } else if(get_irn_op(pred) == op_Start) {
+ if(proj == pn_Start_X_initial_exec) {
+ ir_node *block = get_nodes_block(pred);
+ ir_node *jump;
+
+ block = transform_node(env, block);
+ // we exchange the ProjX with a jump
+ jump = new_rd_Jmp(dbg, irg, block);
+ ir_fprintf(stderr, "created jump: %+F\n", jump);
+ return jump;
+ }
+ if(node == env->old_anchors[anchor_tls]) {
+ return gen_Proj_tls(env, node);
+ }
}
return duplicate_node(env, node);
/* transform ops from intrinsic lowering */
GEN(ia32_l_Add);
- GEN(ia32_l_AddC);
+ GEN(ia32_l_Adc);
GEN(ia32_l_Sub);
- GEN(ia32_l_SubC);
- GEN(ia32_l_Minus);
+ GEN(ia32_l_Sbb);
+ GEN(ia32_l_Neg);
GEN(ia32_l_Mul);
- GEN(ia32_l_Eor);
- GEN(ia32_l_MulS);
+ GEN(ia32_l_Xor);
+ GEN(ia32_l_IMul);
GEN(ia32_l_Shl);
GEN(ia32_l_Shr);
- GEN(ia32_l_Shrs);
+ GEN(ia32_l_Sar);
GEN(ia32_l_ShlD);
GEN(ia32_l_ShrD);
GEN(ia32_l_vfdiv);
/* handle generic backend nodes */
GEN(be_FrameAddr);
- GEN(be_Call);
+ //GEN(be_Call);
GEN(be_Return);
GEN(be_FrameLoad);
GEN(be_FrameStore);
ir_node *block;
ir_node *new_node;
int i, arity;
- ir_node **ins;
block = transform_node(env, get_nodes_block(node));
arity = get_irn_arity(node);
- ins = alloca(arity * sizeof(ins[0]));
- for(i = 0; i < arity; ++i) {
- ir_node *in = get_irn_n(node, i);
- ins[i] = transform_node(env, in);
+ if(op->opar == oparity_dynamic) {
+ new_node = new_ir_node(dbg, irg, block, op, mode, -1, NULL);
+ for(i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ in = transform_node(env, in);
+ add_irn_n(new_node, in);
+ }
+ } else {
+ ir_node **ins = alloca(arity * sizeof(ins[0]));
+ for(i = 0; i < arity; ++i) {
+ ir_node *in = get_irn_n(node, i);
+ ins[i] = transform_node(env, in);
+ }
+
+ new_node = new_ir_node(dbg, irg, block, op, mode, arity, ins);
}
- new_node = new_ir_node(dbg, irg, block,
- op, mode, arity, ins);
copy_node_attr(node, new_node);
duplicate_deps(env, node, new_node);
projects / libfirm / blobdiff