/*
- * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
- *
* This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
*/
/**
#include "besched.h"
#include "beabi.h"
#include "beutil.h"
-#include "beirg.h"
#include "betranshlp.h"
#include "be_t.h"
/* define this to construct SSE constants instead of load them */
#undef CONSTRUCT_SSE_CONST
-#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
+#define mode_fp (ia32_reg_classes[CLASS_ia32_fp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
-static ir_node *create_immediate_or_transform(ir_node *node,
- char immediate_constraint_type);
+static ir_node *create_immediate_or_transform(ir_node *node);
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
dbg_info *dbgi, ir_node *block,
{
ir_graph *irg = current_ir_graph;
- if (be_get_irg_options(irg)->pic) {
+ if (be_options.pic) {
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
return arch_env->impl->get_pic_base(irg);
}
ir_mode *mode = get_irn_mode(node);
ir_tarval *tv = get_Const_tarval(node);
- assert(is_Const(node));
-
if (mode_is_float(mode)) {
ir_graph *irg = get_irn_irg(node);
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
#ifdef CONSTRUCT_SSE_CONST
} else if (tarval_is_one(tv)) {
int cnst = mode == mode_F ? 26 : 55;
- ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
- ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
+ ir_node *imm1 = ia32_create_Immediate(irg, NULL, 0, cnst);
+ ir_node *imm2 = ia32_create_Immediate(irg, NULL, 0, 2);
ir_node *pslld, *psrld;
load = new_bd_ia32_xAllOnes(dbgi, block);
(get_tarval_sub_bits(tv, 2) << 16) |
(get_tarval_sub_bits(tv, 3) << 24);
if (val == 0) {
- ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
+ ir_node *imm32 = ia32_create_Immediate(irg, NULL, 0, 32);
ir_node *cnst, *psllq;
/* fine, lower 32bit are zero, produce 32bit value */
}
} else {
if (tarval_is_null(tv)) {
- load = new_bd_ia32_vfldz(dbgi, block);
+ load = new_bd_ia32_fldz(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else if (tarval_is_one(tv)) {
- load = new_bd_ia32_vfld1(dbgi, block);
+ load = new_bd_ia32_fld1(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else {
smaller entities */
ls_mode = get_type_mode(get_entity_type(floatent));
base = get_symconst_base();
- load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
- ls_mode);
+ load = new_bd_ia32_fld(dbgi, block, base, noreg_GP, nomem,
+ ls_mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
arch_add_irn_flags(load, arch_irn_flags_rematerializable);
- res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
+ res = new_r_Proj(load, mode_fp, pn_ia32_fld_res);
}
}
#ifdef CONSTRUCT_SSE_CONST
if (ia32_cg_config.use_sse2)
cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D);
else
- cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
+ cnst = new_bd_ia32_fld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
set_ia32_am_sc(cnst, get_SymConst_entity(node));
set_ia32_use_frame(cnst);
} else {
case 0: mode = mode_Iu; break;
case 1: mode = mode_Lu; break;
case 2: mode = mode_F; break;
- default: panic("internal compiler error (ia32_gen_fp_known_const)");
+ default: panic("internal compiler error");
}
tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
}
/**
- * Check, if a given node is a Down-Conv, ie. a integer Conv
+ * Check, if a given node is a Down-Conv, i.e. a integer Conv
* from a mode with a mode with more bits to a mode with lesser bits.
* Moreover, we return only true if the node has not more than 1 user.
*
if (!is_Conv(node))
return 0;
- /* we only want to skip the conv when we're the only user
- * (because this test is used in the context of address-mode selection
- * and we don't want to use address mode for multiple users) */
- if (get_irn_n_edges(node) > 1)
- return 0;
-
src_mode = get_irn_mode(get_Conv_op(node));
dest_mode = get_irn_mode(node);
return
/** Skip all Down-Conv's on a given node and return the resulting node. */
ir_node *ia32_skip_downconv(ir_node *node)
{
- while (is_downconv(node))
+ while (is_downconv(node)) {
+ /* we only want to skip the conv when we're the only user
+ * (because this test is used in the context of address-mode selection
+ * and we don't want to use address mode for multiple users) */
+ if (get_irn_n_edges(node) > 1)
+ break;
+
node = get_Conv_op(node);
+ }
+
+ return node;
+}
+
+static bool is_float_downconv(const ir_node *node)
+{
+ if (!is_Conv(node))
+ return false;
+ ir_node *pred = get_Conv_op(node);
+ ir_mode *pred_mode = get_irn_mode(pred);
+ ir_mode *mode = get_irn_mode(node);
+ return mode_is_float(pred_mode)
+ && get_mode_size_bits(mode) <= get_mode_size_bits(pred_mode);
+}
+static ir_node *ia32_skip_float_downconv(ir_node *node)
+{
+ while (is_float_downconv(node)) {
+ node = get_Conv_op(node);
+ }
return node;
}
/** Skip all signedness convs */
static ir_node *ia32_skip_sameconv(ir_node *node)
{
- while (is_sameconv(node))
+ while (is_sameconv(node)) {
node = get_Conv_op(node);
+ }
return node;
}
-static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
+static ir_node *transform_sext(ir_node *node, ir_node *orig_node)
{
- ir_mode *mode = get_irn_mode(node);
- ir_node *block;
- ir_mode *tgt_mode;
- dbg_info *dbgi;
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ return create_I2I_Conv(mode, mode_Is, dbgi, block, node, orig_node);
+}
+
+static ir_node *transform_zext(ir_node *node, ir_node *orig_node)
+{
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ /* normalize to an unsigned mode */
+ switch (get_mode_size_bits(mode)) {
+ case 8: mode = mode_Bu; break;
+ case 16: mode = mode_Hu; break;
+ default:
+ panic("ia32: invalid mode in zest: %+F", node);
+ }
+ return create_I2I_Conv(mode, mode_Iu, dbgi, block, node, orig_node);
+}
+static ir_node *transform_upconv(ir_node *node, ir_node *orig_node)
+{
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_signed(mode)) {
- tgt_mode = mode_Is;
+ return transform_sext(node, orig_node);
} else {
- tgt_mode = mode_Iu;
+ return transform_zext(node, orig_node);
}
- block = get_nodes_block(node);
- dbgi = get_irn_dbg_info(node);
+}
- return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
+static ir_node *get_noreg(ir_mode *const mode)
+{
+ if (!mode_is_float(mode)) {
+ return noreg_GP;
+ } else if (ia32_cg_config.use_sse2) {
+ return ia32_new_NoReg_xmm(current_ir_graph);
+ } else {
+ return ia32_new_NoReg_fp(current_ir_graph);
+ }
}
/**
* op2 input */
new_op2 = NULL;
if (!(flags & match_try_am) && use_immediate) {
- new_op2 = ia32_try_create_Immediate(op2, 0);
+ new_op2 = ia32_try_create_Immediate(op2, 'i');
}
if (new_op2 == NULL &&
use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
build_address(am, op2, ia32_create_am_normal);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
- if (mode_is_float(mode)) {
- new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
- } else {
- new_op2 = noreg_GP;
- }
+ new_op2 = get_noreg(mode);
am->op_type = ia32_AddrModeS;
} else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
use_am &&
ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
- ir_node *noreg;
build_address(am, op1, ia32_create_am_normal);
- if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_vfp(current_ir_graph);
- } else {
- noreg = noreg_GP;
- }
-
+ ir_node *const noreg = get_noreg(mode);
if (new_op2 != NULL) {
new_op1 = noreg;
} else {
}
mode = get_irn_mode(op2);
- if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
- new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
- if (new_op2 == NULL)
- new_op2 = create_upconv(op2, NULL);
- am->ls_mode = mode_Iu;
+ if (get_mode_size_bits(mode) != 32
+ && (flags & (match_mode_neutral | match_upconv | match_zero_ext))) {
+ if (flags & match_upconv) {
+ new_op1 = (op1 == NULL ? NULL : transform_upconv(op1, op1));
+ if (new_op2 == NULL)
+ new_op2 = transform_upconv(op2, op2);
+ } else if (flags & match_zero_ext) {
+ new_op1 = (op1 == NULL ? NULL : transform_zext(op1, op1));
+ if (new_op2 == NULL)
+ new_op2 = transform_zext(op2, op2);
+ } else {
+ new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
+ if (new_op2 == NULL)
+ new_op2 = be_transform_node(op2);
+ assert(flags & match_mode_neutral);
+ }
+ mode = mode_Iu;
} else {
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (new_op2 == NULL)
new_op2 = be_transform_node(op2);
- am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
}
+ am->ls_mode = mode;
}
if (addr->base == NULL)
addr->base = noreg_GP;
return node;
}
+static void check_x87_floatmode(ir_mode *mode)
+{
+ if (mode != ia32_mode_E) {
+ panic("ia32: x87 only supports x86 extended float mode");
+ }
+}
+
/**
* Construct a standard binary operation, set AM and immediate if required.
*
/* All operations are considered commutative, because there are reverse
* variants */
match_flags_t flags = match_commutative | match_am;
+ ir_mode *mode
+ = is_Div(node) ? get_Div_resmode(node) : get_irn_mode(node);
+ check_x87_floatmode(mode);
op1 = skip_float_upconv(op1);
op2 = skip_float_upconv(op2);
construct_shift_func *func,
match_flags_t flags)
{
- dbg_info *dbgi;
- ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
- ir_mode *mode = get_irn_mode(node);
+ ir_mode *mode = get_irn_mode(node);
assert(! mode_is_float(mode));
assert(flags & match_immediate);
- assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
+ assert((flags & ~(match_mode_neutral | match_zero_ext | match_upconv | match_immediate)) == 0);
- if (get_mode_modulo_shift(mode) != 32)
+ if (get_mode_modulo_shift(mode) != 32) {
+ /* TODO: implement special cases for non-modulo shifts */
panic("modulo shift!=32 not supported by ia32 backend");
+ }
+ ir_node *new_op1;
+ ir_node *new_op2;
if (flags & match_mode_neutral) {
op1 = ia32_skip_downconv(op1);
new_op1 = be_transform_node(op1);
- } else if (get_mode_size_bits(mode) != 32) {
- new_op1 = create_upconv(op1, node);
} else {
- new_op1 = be_transform_node(op1);
+ op1 = ia32_skip_sameconv(op1);
+ if (get_mode_size_bits(mode) != 32) {
+ if (flags & match_upconv) {
+ new_op1 = transform_upconv(op1, node);
+ } else if (flags & match_zero_ext) {
+ new_op1 = transform_zext(op1, node);
+ } else {
+ /* match_mode_neutral not handled here because it makes no
+ * sense for shift operations */
+ panic("ia32 code selection failed for %+F", node);
+ }
+ } else {
+ new_op1 = be_transform_node(op1);
+ }
}
/* the shift amount can be any mode that is bigger than 5 bits, since all
op2 = op;
assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
}
- new_op2 = create_immediate_or_transform(op2, 0);
+ new_op2 = create_immediate_or_transform(op2);
- dbgi = get_irn_dbg_info(node);
- block = get_nodes_block(node);
- new_block = be_transform_node(block);
- new_node = func(dbgi, new_block, new_op1, new_op2);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_node = func(dbgi, new_block, new_op1, new_op2);
SET_IA32_ORIG_NODE(new_node, node);
/* lowered shift instruction may have a dependency operand, handle it here */
assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
count = get_Conv_op(count);
}
- new_count = create_immediate_or_transform(count, 0);
+ new_count = create_immediate_or_transform(count);
new_node = func(dbgi, new_block, new_high, new_low, new_count);
return new_node;
}
/**
- * test wether 2 values result in 'x' and '32-x' when interpreted as a shift
+ * Tests whether 2 values result in 'x' and '32-x' when interpreted as a shift
* value.
*/
static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fadd);
}
ia32_mark_non_am(node);
- op2 = ia32_skip_downconv(op2);
- op1 = ia32_skip_downconv(op1);
-
/**
* Rules for an Add:
* 0. Immediate Trees (example Add(Symconst, Const) -> Const)
return gen_binop(node, op1, op2, new_bd_ia32_xMul,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fmul);
}
return gen_binop(node, op1, op2, new_bd_ia32_IMul,
match_commutative | match_am | match_mode_neutral |
if (ia32_cg_config.use_sse2)
return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fsub);
}
if (is_Const(op2)) {
ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
res = new_bd_ia32_Cltd(dbgi, block, val, pval);
} else {
- ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
+ ir_graph *const irg = get_Block_irg(block);
+ ir_node *const imm31 = ia32_create_Immediate(irg, NULL, 0, 31);
res = new_bd_ia32_Sar(dbgi, block, val, imm31);
}
SET_IA32_ORIG_NODE(res, orig);
panic("invalid divmod node %+F", node);
}
- match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
+ match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv);
/* Beware: We don't need a Sync, if the memory predecessor of the Div node
is the memory of the consumed address. We can have only the second op as address
if (ia32_cg_config.use_sse2) {
return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
} else {
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fdiv);
}
}
ir_node *left = get_Shr_left(node);
ir_node *right = get_Shr_right(node);
- return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
+ return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
+ match_immediate | match_zero_ext);
}
-
-
/**
* Creates an ia32 Sar.
*
}
}
- return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
+ return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
+ match_immediate | match_upconv);
}
set_ia32_op_type(new_node, ia32_AddrModeS);
set_ia32_ls_mode(new_node, mode);
} else {
- new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
+ new_node = new_bd_ia32_fchs(dbgi, block, new_op);
}
} else {
new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
ir_node *op = get_Not_op(node);
assert(get_irn_mode(node) != mode_b); /* should be lowered already */
- assert (! mode_is_float(get_irn_mode(node)));
+ assert(!mode_is_float(get_irn_mode(node)));
return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
}
/* TODO, implement -Abs case */
assert(!negate);
} else {
- new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
+ check_x87_floatmode(mode);
+ new_node = new_bd_ia32_fabs(dbgi, new_block, new_op);
SET_IA32_ORIG_NODE(new_node, node);
if (negate) {
- new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
+ new_node = new_bd_ia32_fchs(dbgi, new_block, new_node);
SET_IA32_ORIG_NODE(new_node, node);
}
}
new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
mode);
} else {
- new_node = new_bd_ia32_vfld(dbgi, block, base, idx, new_mem,
+ new_node = new_bd_ia32_fld(dbgi, block, base, idx, new_mem,
mode);
}
} else {
set_address(new_node, &addr);
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_add_irn_flags(new_node, arch_irn_flags_rematerializable);
}
if (use_dest_am(src_block, op1, mem, ptr, op2)) {
build_address(&am, op1, ia32_create_am_double_use);
- new_op = create_immediate_or_transform(op2, 0);
+ new_op = create_immediate_or_transform(op2);
} else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
build_address(&am, op2, ia32_create_am_double_use);
- new_op = create_immediate_or_transform(op1, 0);
+ new_op = create_immediate_or_transform(op1);
} else {
return NULL;
}
}
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
+ new_bd_ia32_AddMem, new_bd_ia32_AddMem_8bit,
match_commutative | match_immediate);
break;
case iro_Sub:
ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
+ new_bd_ia32_SubMem, new_bd_ia32_SubMem_8bit,
match_immediate);
break;
case iro_And:
op1 = get_And_left(val);
op2 = get_And_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
+ new_bd_ia32_AndMem, new_bd_ia32_AndMem_8bit,
match_commutative | match_immediate);
break;
case iro_Or:
op1 = get_Or_left(val);
op2 = get_Or_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
+ new_bd_ia32_OrMem, new_bd_ia32_OrMem_8bit,
match_commutative | match_immediate);
break;
case iro_Eor:
op1 = get_Eor_left(val);
op2 = get_Eor_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
+ new_bd_ia32_XorMem, new_bd_ia32_XorMem_8bit,
match_commutative | match_immediate);
break;
case iro_Shl:
} else {
panic("invalid size of Store float to mem (%+F)", node);
}
- ir_node *imm = ia32_create_Immediate(NULL, 0, val);
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const imm = ia32_create_Immediate(irg, NULL, 0, val);
ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, imm);
if (ia32_cg_config.use_fisttp) {
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
- ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
- ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_vfisttp_res);
+ ir_node *vfisttp = new_bd_ia32_fisttp(dbgi, block, base, index, mem, val);
+ ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_fisttp_res);
be_new_Keep(block, 1, &value);
return vfisttp;
ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
/* do a fist */
- ir_node *vfist = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
+ ir_node *vfist = new_bd_ia32_fist(dbgi, block, base, index, mem, val, trunc_mode);
return vfist;
}
}
addr.mem = be_transform_node(mem);
if (mode_is_float(mode)) {
- /* Convs (and strict-Convs) before stores are unnecessary if the mode
- is the same. */
- while (is_Conv(val) && mode == get_irn_mode(val)) {
- ir_node *op = get_Conv_op(val);
- if (!mode_is_float(get_irn_mode(op)))
- break;
- val = op;
- }
- new_val = be_transform_node(val);
if (ia32_cg_config.use_sse2) {
+ new_val = be_transform_node(val);
new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val);
} else {
- new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
+ val = ia32_skip_float_downconv(val);
+ new_val = be_transform_node(val);
+ new_node = new_bd_ia32_fst(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
} else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
- val = get_Conv_op(val);
-
- /* TODO: is this optimisation still necessary at all (middleend)? */
- /* We can skip ALL float->float up-Convs (and strict-up-Convs) before
- * stores. */
- while (is_Conv(val)) {
- ir_node *op = get_Conv_op(val);
- if (!mode_is_float(get_irn_mode(op)))
- break;
- if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
- break;
- val = op;
- }
+ val = get_Conv_op(val);
new_val = be_transform_node(val);
new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
} else {
- new_val = create_immediate_or_transform(val, 0);
+ unsigned dest_bits = get_mode_size_bits(mode);
+ while (is_downconv(val)
+ && get_mode_size_bits(get_irn_mode(val)) >= dest_bits) {
+ val = get_Conv_op(val);
+ }
+ new_val = create_immediate_or_transform(val);
assert(mode != mode_b);
- if (get_mode_size_bits(mode) == 8) {
- new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- } else {
- new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- }
+ new_node = dest_bits == 8
+ ? new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, new_val)
+ : new_bd_ia32_Store (dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
}
ir_set_throws_exception(new_node, throws_exception);
const ir_switch_table *table = get_Switch_table(node);
unsigned n_outs = get_Switch_n_outs(node);
ir_node *new_node;
- ir_entity *entity;
- assert(get_mode_size_bits(get_irn_mode(sel)) <= 32);
- if (get_mode_size_bits(sel_mode) != 32)
- new_sel = create_upconv(new_sel, sel);
+ assert(get_mode_size_bits(sel_mode) <= 32);
+ assert(!mode_is_float(sel_mode));
+ sel = ia32_skip_sameconv(sel);
+ if (get_mode_size_bits(sel_mode) < 32)
+ new_sel = transform_upconv(sel, node);
- entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
+ ir_type *const utype = get_unknown_type();
+ ir_entity *const entity = new_entity(utype, id_unique("TBL%u"), utype);
set_entity_visibility(entity, ir_visibility_private);
add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
ir_node *left = get_Cmp_left(node);
ir_node *new_left = be_transform_node(left);
ir_node *right = get_Cmp_right(node);
+ ir_mode *cmp_mode = get_irn_mode(left);
ir_node *new_right;
ir_node *new_node;
+ check_x87_floatmode(cmp_mode);
if (ia32_cg_config.use_fucomi) {
new_right = be_transform_node(right);
- new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
+ new_node = new_bd_ia32_Fucomi(dbgi, new_block, new_left,
new_right, 0);
set_ia32_commutative(new_node);
SET_IA32_ORIG_NODE(new_node, node);
} else {
- if (ia32_cg_config.use_ftst && is_Const_0(right)) {
- new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
+ if (is_Const_0(right)) {
+ new_node = new_bd_ia32_FtstFnstsw(dbgi, new_block, new_left, 0);
} else {
new_right = be_transform_node(right);
- new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
+ new_node = new_bd_ia32_FucomFnstsw(dbgi, new_block, new_left, new_right, 0);
set_ia32_commutative(new_node);
}
return new_node;
}
-/**
- * returns true if it is assured, that the upper bits of a node are "clean"
- * which means for a 16 or 8 bit value, that the upper bits in the register
- * are 0 for unsigned and a copy of the last significant bit for signed
- * numbers.
- */
-static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
+static bool ia32_mux_upper_bits_clean(const ir_node *node, ir_mode *mode)
{
- assert(ia32_mode_needs_gp_reg(mode));
- if (get_mode_size_bits(mode) >= 32)
- return true;
-
- if (is_Proj(transformed_node))
- return upper_bits_clean(get_Proj_pred(transformed_node), mode);
-
- switch (get_ia32_irn_opcode(transformed_node)) {
- case iro_ia32_Conv_I2I:
- case iro_ia32_Conv_I2I8Bit: {
- ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
- if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
- return false;
- if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
- return false;
-
- return true;
- }
-
- case iro_ia32_Shr:
- if (mode_is_signed(mode)) {
- return false; /* TODO handle signed modes */
- } else {
- ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
- if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
- const ia32_immediate_attr_t *attr
- = get_ia32_immediate_attr_const(right);
- if (attr->symconst == 0 &&
- (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
- return true;
- }
- }
- return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
- }
-
- case iro_ia32_Sar:
- /* TODO too conservative if shift amount is constant */
- return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
-
- case iro_ia32_And:
- if (!mode_is_signed(mode)) {
- return
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
- }
- /* TODO if one is known to be zero extended, then || is sufficient */
- /* FALLTHROUGH */
- case iro_ia32_Or:
- case iro_ia32_Xor:
- return
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
-
- case iro_ia32_Const:
- case iro_ia32_Immediate: {
- const ia32_immediate_attr_t *attr =
- get_ia32_immediate_attr_const(transformed_node);
- if (mode_is_signed(mode)) {
- long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
- return shifted == 0 || shifted == -1;
- } else {
- unsigned long shifted = (unsigned long)attr->offset;
- shifted >>= get_mode_size_bits(mode)-1;
- shifted >>= 1;
- return shifted == 0;
- }
- }
-
- default:
- return false;
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
+ ir_mode *mux_mode = get_irn_mode(node);
+ /* mux nodes which get transformed to the set instruction are not clean */
+ if (is_Const(mux_true) && is_Const(mux_false)
+ && get_mode_size_bits(mux_mode) == 8) {
+ return false;
}
+ return be_upper_bits_clean(mux_true, mode)
+ && be_upper_bits_clean(mux_false, mode);
}
/**
match_am_and_immediates | match_immediate);
/* use 32bit compare mode if possible since the opcode is smaller */
- if (upper_bits_clean(am.new_op1, cmp_mode) &&
- upper_bits_clean(am.new_op2, cmp_mode)) {
+ if (am.op_type == ia32_Normal &&
+ be_upper_bits_clean(and_left, cmp_mode) &&
+ be_upper_bits_clean(and_right, cmp_mode)) {
cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
}
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem,
- am.new_op1, am.new_op2,
- am.ins_permuted);
- } else {
- new_node = new_bd_ia32_Test(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted);
- }
+ new_node = get_mode_size_bits(cmp_mode) == 8
+ ? new_bd_ia32_Test_8bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted)
+ : new_bd_ia32_Test (dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
} else {
/* Cmp(left, right) */
match_arguments(&am, block, left, right, NULL,
- match_commutative | match_am | match_8bit_am |
- match_16bit_am | match_am_and_immediates |
- match_immediate);
+ match_commutative |
+ match_am | match_8bit_am | match_16bit_am |
+ match_am_and_immediates | match_immediate);
/* use 32bit compare mode if possible since the opcode is smaller */
- if (upper_bits_clean(am.new_op1, cmp_mode) &&
- upper_bits_clean(am.new_op2, cmp_mode)) {
+ if (am.op_type == ia32_Normal &&
+ be_upper_bits_clean(left, cmp_mode) &&
+ be_upper_bits_clean(right, cmp_mode)) {
cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
}
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted);
- } else {
- new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2,
- am.ins_permuted);
- }
+ new_node = get_mode_size_bits(cmp_mode) == 8
+ ? new_bd_ia32_Cmp_8bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted)
+ : new_bd_ia32_Cmp (dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
}
set_am_attributes(new_node, &am);
set_ia32_ls_mode(new_node, cmp_mode);
/* we might need to conv the result up */
if (get_mode_size_bits(mode) > 8) {
- new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_node, mode_Bu);
+ new_node = new_bd_ia32_Conv_I2I_8bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, orig_node);
}
SETCC_TR_NOT,
SETCC_TR_AND,
SETCC_TR_SET,
- SETCC_TR_SBB,
};
typedef struct setcc_transform {
if (ia32_cg_config.use_sse2)
load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
else
- load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
+ load = new_bd_ia32_fld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
set_am_attributes(load, &am);
- return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
+ return new_rd_Proj(NULL, load, mode_fp, pn_ia32_res);
}
panic("cannot transform floating point Mux");
case SETCC_TR_SET:
new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
break;
- case SETCC_TR_SBB:
- new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
- break;
default:
panic("unknown setcc transform");
}
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
+ arch_add_irn_flags(fist, arch_irn_flags_spill);
- assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
- mem = new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
+ assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
+ mem = new_r_Proj(fist, mode_M, pn_ia32_fist_M);
assert(get_mode_size_bits(mode) <= 32);
/* exception we can only store signed 32 bit integers, so for unsigned
}
/**
- * Creates a x87 strict Conv by placing a Store and a Load
+ * Creates a x87 Conv by placing a Store and a Load
*/
-static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
+static ir_node *gen_x87_conv(ir_mode *tgt_mode, ir_node *node)
{
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_Block_irg(block);
ir_node *store, *load;
ir_node *new_node;
- store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
+ store = new_bd_ia32_fst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
+ arch_add_irn_flags(store, arch_irn_flags_spill);
SET_IA32_ORIG_NODE(store, node);
- store_mem = new_r_Proj(store, mode_M, pn_ia32_vfst_M);
+ store_mem = new_r_Proj(store, mode_M, pn_ia32_fst_M);
- load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
+ load = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
SET_IA32_ORIG_NODE(load, node);
- new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_vfld_res);
+ new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_fld_res);
return new_node;
}
ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
func = get_mode_size_bits(mode) == 8 ?
- new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
+ new_bd_ia32_Conv_I2I_8bit : new_bd_ia32_Conv_I2I;
return func(dbgi, block, base, index, mem, val, mode);
}
if (possible_int_mode_for_fp(src_mode)) {
ia32_address_mode_t am;
- match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
+ match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am | match_upconv);
if (am.op_type == ia32_AddrModeS) {
ia32_address_t *addr = &am.addr;
- fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
- new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ fild = new_bd_ia32_fild(dbgi, block, addr->base, addr->index, addr->mem);
+ new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
set_am_attributes(fild, &am);
SET_IA32_ORIG_NODE(fild, node);
/* first convert to 32 bit signed if necessary */
if (get_mode_size_bits(src_mode) < 32) {
- if (!upper_bits_clean(new_op, src_mode)) {
+ if (!be_upper_bits_clean(op, src_mode)) {
new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, node);
}
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Iu);
+ arch_add_irn_flags(store, arch_irn_flags_spill);
store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
if (!mode_is_signed(mode)) {
ir_node *in[2];
/* store a zero */
- ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
+ ir_node *zero_const = ia32_create_Immediate(irg, NULL, 0, 0);
ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
noreg_GP, nomem, zero_const);
set_ia32_op_type(zero_store, ia32_AddrModeD);
add_ia32_am_offs_int(zero_store, 4);
set_ia32_ls_mode(zero_store, mode_Iu);
+ arch_add_irn_flags(zero_store, arch_irn_flags_spill);
in[0] = zero_store_mem;
in[1] = store_mem;
}
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
+ fild = new_bd_ia32_fild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_ls_mode(fild, store_mode);
- new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
return new_node;
}
{
ir_node *new_block = be_transform_node(block);
ir_node *new_node;
- ir_mode *smaller_mode;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
(void) node;
- if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
- smaller_mode = src_mode;
- } else {
- smaller_mode = tgt_mode;
- }
+ assert(get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode));
#ifdef DEBUG_libfirm
if (is_Const(op)) {
}
#endif
+ if (be_upper_bits_clean(op, src_mode)) {
+ return be_transform_node(op);
+ }
+
match_arguments(&am, block, NULL, op, NULL,
match_am | match_8bit_am | match_16bit_am);
- if (upper_bits_clean(am.new_op2, smaller_mode)) {
- /* unnecessary conv. in theory it shouldn't have been AM */
- assert(is_ia32_NoReg_GP(addr->base));
- assert(is_ia32_NoReg_GP(addr->index));
- assert(is_NoMem(addr->mem));
- assert(am.addr.offset == 0);
- assert(am.addr.symconst_ent == NULL);
- return am.new_op2;
- }
-
new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op2, smaller_mode);
+ addr->mem, am.new_op2, src_mode);
set_am_attributes(new_node, &am);
/* match_arguments assume that out-mode = in-mode, this isn't true here
* so fix it */
- set_ia32_ls_mode(new_node, smaller_mode);
+ set_ia32_ls_mode(new_node, src_mode);
SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
return new_node;
}
if (src_mode == tgt_mode) {
- if (get_Conv_strict(node)) {
- if (ia32_cg_config.use_sse2) {
- /* when we are in SSE mode, we can kill all strict no-op conversion */
- return be_transform_node(op);
- }
- } else {
- /* this should be optimized already, but who knows... */
- DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);)
+ /* this should be optimized already, but who knows... */
+ DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);)
DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
- return be_transform_node(op);
- }
+ return be_transform_node(op);
}
if (mode_is_float(src_mode)) {
nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
- if (get_Conv_strict(node)) {
- /* if fp_no_float_fold is not set then we assume that we
- * don't have any float operations in a non
- * mode_float_arithmetic mode and can skip strict upconvs */
- if (src_bits < tgt_bits) {
- DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
- return new_op;
- } else {
- res = gen_x87_strict_conv(tgt_mode, new_op);
- SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
- return res;
- }
+ if (src_bits < tgt_bits) {
+ DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
+ return new_op;
+ } else {
+ res = gen_x87_conv(tgt_mode, new_op);
+ SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
+ return res;
}
- DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
- return new_op;
}
} else {
/* ... to int */
unsigned float_mantissa = get_mode_mantissa_size(tgt_mode);
res = gen_x87_gp_to_fp(node, src_mode);
- /* we need a strict-Conv, if the int mode has more bits than the
+ /* we need a float-conv, if the int mode has more bits than the
* float mantissa */
if (float_mantissa < int_mantissa) {
- res = gen_x87_strict_conv(tgt_mode, res);
+ res = gen_x87_conv(tgt_mode, res);
SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
}
return res;
return be_transform_node(op);
} else {
/* to int */
- if (src_bits == tgt_bits) {
+ if (src_bits >= tgt_bits) {
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
return be_transform_node(op);
return res;
}
-static ir_node *create_immediate_or_transform(ir_node *node,
- char immediate_constraint_type)
+static ir_node *create_immediate_or_transform(ir_node *const node)
{
- ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
+ ir_node *new_node = ia32_try_create_Immediate(node, 'i');
if (new_node == NULL) {
new_node = be_transform_node(node);
}
*/
static ir_node *gen_be_Return(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
ir_node *ret_val = get_irn_n(node, n_be_Return_val);
ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
ir_node *new_ret_val = be_transform_node(ret_val);
ir_node *new_ret_mem = be_transform_node(ret_mem);
- ir_entity *ent = get_irg_entity(irg);
- ir_type *tp = get_entity_type(ent);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_graph *irg = get_Block_irg(block);
+ ir_entity *ent = get_irg_entity(irg);
+ ir_type *tp = get_entity_type(ent);
ir_type *res_type;
ir_mode *mode;
ir_node *frame;
int arity;
unsigned pop;
ir_node **in;
- ir_node *new_node;
assert(ret_val != NULL);
if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
+ arch_add_irn_flags(sse_store, arch_irn_flags_spill);
store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
/* load into x87 register */
- fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store_mem, mode);
+ fld = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
- mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
- fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
+ mproj = new_r_Proj(fld, mode_M, pn_ia32_fld_M);
+ fld = new_r_Proj(fld, mode_fp, pn_ia32_fld_res);
/* create a new return */
arity = get_irn_arity(node);
in[i] = be_transform_node(op);
}
}
- new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
+ ir_node *const new_node = be_new_Return(dbgi, block, arity, pop, arity, in);
copy_node_attr(irg, node, new_node);
return new_node;
return new_node;
}
-/**
- * Change some phi modes
- */
static ir_node *gen_Phi(ir_node *node)
{
+ ir_mode *mode = get_irn_mode(node);
const arch_register_req_t *req;
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *phi;
-
if (ia32_mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
mode = mode_xmm;
req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
} else {
- mode = mode_vfp;
- req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
+ mode = mode_fp;
+ req = ia32_reg_classes[CLASS_ia32_fp].class_req;
}
} else {
req = arch_no_register_req;
}
- /* phi nodes allow loops, so we use the old arguments for now
- * and fix this later */
- phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
- get_irn_in(node) + 1);
- copy_node_attr(irg, node, phi);
- be_duplicate_deps(node, phi);
-
- arch_set_irn_register_req_out(phi, 0, req);
-
- be_enqueue_preds(node);
-
- return phi;
+ return be_transform_phi(node, req);
}
static ir_node *gen_Jmp(ir_node *node)
assert(get_irn_mode(op) == mode_P);
- match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
+ match_arguments(&am, block, NULL, op, NULL,
+ match_am | match_immediate | match_upconv);
new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op2);
+ addr->mem, am.new_op2);
set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, node);
{
ir_node *src_block = get_nodes_block(node);
ir_node *block = be_transform_node(src_block);
- ir_graph *irg = current_ir_graph;
+ ir_graph *irg = get_Block_irg(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *frame = get_irg_frame(irg);
ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
ir_node *mem_high;
if (ia32_cg_config.use_sse2) {
- panic("ia32_l_LLtoFloat not implemented for SSE2");
+ panic("not implemented for SSE2");
}
/* do a store */
set_ia32_op_type(store_high, ia32_AddrModeD);
set_ia32_ls_mode(store_low, mode_Iu);
set_ia32_ls_mode(store_high, mode_Is);
+ arch_add_irn_flags(store_low, arch_irn_flags_spill);
+ arch_add_irn_flags(store_high, arch_irn_flags_spill);
add_ia32_am_offs_int(store_high, 4);
in[0] = mem_low;
sync = new_rd_Sync(dbgi, block, 2, in);
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
+ fild = new_bd_ia32_fild(dbgi, block, frame, noreg_GP, sync);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
SET_IA32_ORIG_NODE(fild, node);
- res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ res = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
if (! mode_is_signed(get_irn_mode(val_high))) {
ia32_address_mode_t am;
- ir_node *count = ia32_create_Immediate(NULL, 0, 31);
+ ir_node *count = ia32_create_Immediate(irg, NULL, 0, 31);
ir_node *fadd;
am.addr.base = get_symconst_base();
am.mem_proj = nomem;
am.op_type = ia32_AddrModeS;
am.new_op1 = res;
- am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
+ am.new_op2 = ia32_new_NoReg_fp(irg);
am.pinned = op_pin_state_floats;
am.commutative = 1;
am.ins_permuted = false;
- fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
+ fadd = new_bd_ia32_fadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
am.new_op1, am.new_op2, get_fpcw());
set_am_attributes(fadd, &am);
set_irn_mode(fadd, mode_T);
- res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
+ res = new_rd_Proj(NULL, fadd, mode_fp, pn_ia32_res);
}
return res;
}
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
+ arch_add_irn_flags(fist, arch_irn_flags_spill);
- assert((long)pn_ia32_vfist_M == (long) pn_ia32_vfisttp_M);
- return new_r_Proj(fist, mode_M, pn_ia32_vfist_M);
+ assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
+ return new_r_Proj(fist, mode_M, pn_ia32_fist_M);
}
static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
}
- } else if (is_ia32_Conv_I2I(new_pred) ||
- is_ia32_Conv_I2I8Bit(new_pred)) {
+ } else if (is_ia32_Conv_I2I(new_pred)) {
set_irn_mode(new_pred, mode_T);
switch ((pn_Load)proj) {
case pn_Load_res:
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
}
- } else if (is_ia32_vfld(new_pred)) {
+ } else if (is_ia32_fld(new_pred)) {
switch ((pn_Load)proj) {
case pn_Load_res:
- return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
+ return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fld_res);
case pn_Load_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fld_M);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_except);
case pn_Load_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_regular);
}
} else {
/* can happen for ProJMs when source address mode happened for the
dbg_info *dbgi = get_irn_dbg_info(node);
long pn = get_Proj_proj(node);
- if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
+ if (is_ia32_Store(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
case pn_Store_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
}
- } else if (is_ia32_vfist(new_pred)) {
+ } else if (is_ia32_fist(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfist_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fist_M);
case pn_Store_X_except:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_except);
case pn_Store_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfist_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_regular);
}
- } else if (is_ia32_vfisttp(new_pred)) {
+ } else if (is_ia32_fisttp(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfisttp_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fisttp_M);
case pn_Store_X_except:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_except);
case pn_Store_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfisttp_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_regular);
}
- } else if (is_ia32_vfst(new_pred)) {
+ } else if (is_ia32_fst(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfst_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fst_M);
case pn_Store_X_except:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_except);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_except);
case pn_Store_X_regular:
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfst_X_regular);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_regular);
}
} else if (is_ia32_xStore(new_pred)) {
switch ((pn_Store)pn) {
if (pn == pn_Store_M) {
return new_pred;
}
- panic("exception control flow for gen_float_const_Store not implemented yet");
+ panic("exception control flow not implemented yet");
} else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) {
/* destination address mode */
if (pn == pn_Store_M) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
} else if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
- } else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
+ } else if (is_ia32_fdiv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fdiv_M);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
} else if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
- } else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ } else if (is_ia32_fdiv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fdiv_res);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
ir_mode *const res_mode = get_type_mode(res_type);
if (res_mode != NULL && mode_is_float(res_mode)) {
- ir_graph *irg = current_ir_graph;
- ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
- irg_data->do_x87_sim = 1;
+ ir_graph *const irg = get_Block_irg(block);
+ ia32_request_x87_sim(irg);
}
}
/* special case for PIC trampoline calls */
old_no_pic_adjust = ia32_no_pic_adjust;
- ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic;
+ ia32_no_pic_adjust = be_options.pic;
match_arguments(&am, src_block, NULL, src_ptr, src_mem,
- match_am | match_immediate);
+ match_am | match_immediate | match_upconv);
ia32_no_pic_adjust = old_no_pic_adjust;
set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_add_irn_flags(load, arch_irn_flags_rematerializable);
}
}
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_add_irn_flags(load, arch_irn_flags_rematerializable);
}
SET_IA32_ORIG_NODE(set, node);
/* conv to 32bit */
- conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
+ conv = new_bd_ia32_Conv_I2I_8bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
SET_IA32_ORIG_NODE(conv, node);
/* neg */
ir_node *real = skip_Proj(bsr);
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
- ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
+ ir_graph *irg = get_Block_irg(block);
+ ir_node *imm = ia32_create_Immediate(irg, NULL, 0, 31);
return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
}
* chance for CSE, constant folding and other goodies for some of these
* operations)
*/
- ir_node *count = ia32_create_Immediate(NULL, 0, 16);
- ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
- ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
- shr, new_param);
- ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor);
- ir_node *flags;
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const count = ia32_create_Immediate(irg, NULL, 0, 16);
+ ir_node *const shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
+ ir_node *const xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, shr, new_param);
+ ir_node *const xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn);
+ ir_node *flags;
- set_ia32_ls_mode(xor, mode_Iu);
- set_ia32_commutative(xor);
+ set_ia32_ls_mode(xorn, mode_Iu);
+ set_ia32_commutative(xorn);
set_irn_mode(xor2, mode_T);
flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
SET_IA32_ORIG_NODE(new_node, node);
/* conv to 32bit */
- new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_node, mode_Bu);
+ new_node = new_bd_ia32_Conv_I2I_8bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
ia32_address_t *addr = &am.addr;
ir_node *cnt;
- match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am);
+ match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am | match_upconv);
cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
set_am_attributes(cnt, &am);
* But I'm too lazy to fix this now, as the code should get lowered before
* the backend anyway.
*/
+ ir_graph *const irg = get_Block_irg(new_block);
/* m1 = x & 0x55555555 */
- imm = ia32_create_Immediate(NULL, 0, 0x55555555);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x55555555);
m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
/* s1 = x >> 1 */
- simm = ia32_create_Immediate(NULL, 0, 1);
+ simm = ia32_create_Immediate(irg, NULL, 0, 1);
s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
/* m2 = s1 & 0x55555555 */
m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
/* m4 = m3 & 0x33333333 */
- imm = ia32_create_Immediate(NULL, 0, 0x33333333);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x33333333);
m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
/* s2 = m3 >> 2 */
- simm = ia32_create_Immediate(NULL, 0, 2);
+ simm = ia32_create_Immediate(irg, NULL, 0, 2);
s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
/* m5 = s2 & 0x33333333 */
m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
/* m7 = m6 & 0x0F0F0F0F */
- imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x0F0F0F0F);
m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
/* s3 = m6 >> 4 */
- simm = ia32_create_Immediate(NULL, 0, 4);
+ simm = ia32_create_Immediate(irg, NULL, 0, 4);
s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
/* m8 = s3 & 0x0F0F0F0F */
m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
/* m10 = m9 & 0x00FF00FF */
- imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x00FF00FF);
m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
/* s4 = m9 >> 8 */
- simm = ia32_create_Immediate(NULL, 0, 8);
+ simm = ia32_create_Immediate(irg, NULL, 0, 8);
s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
/* m11 = s4 & 0x00FF00FF */
m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
/* m13 = m12 & 0x0000FFFF */
- imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x0000FFFF);
m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
/* s5 = m12 >> 16 */
- simm = ia32_create_Immediate(NULL, 0, 16);
+ simm = ia32_create_Immediate(irg, NULL, 0, 16);
s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
/* res = m13 + s5 */
/* swap available */
return new_bd_ia32_Bswap(dbgi, new_block, param);
} else {
- ir_node *i8 = ia32_create_Immediate(NULL, 0, 8);
- ir_node *rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
- ir_node *i16 = ia32_create_Immediate(NULL, 0, 16);
- ir_node *rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
- ir_node *rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const i8 = ia32_create_Immediate(irg, NULL, 0, 8);
+ ir_node *const rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
+ ir_node *const i16 = ia32_create_Immediate(irg, NULL, 0, 16);
+ ir_node *const rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
+ ir_node *const rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
set_ia32_ls_mode(rol1, mode_Hu);
set_ia32_ls_mode(rol2, mode_Iu);
set_ia32_ls_mode(rol3, mode_Hu);
*/
static ir_node *gen_outport(ir_node *node)
{
- ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
+ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
ir_node *oldv = get_Builtin_param(node, 1);
ir_mode *mode = get_irn_mode(oldv);
ir_node *value = be_transform_node(oldv);
ir_type *tp = get_Builtin_type(node);
ir_type *rstp = get_method_res_type(tp, 0);
ir_mode *mode = get_type_mode(rstp);
- ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
+ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *mem = be_transform_node(get_Builtin_mem(node));
dbg_info *dbgi = get_irn_dbg_info(node);
}
addr.mem = be_transform_node(mem);
+ ir_graph *const irg = get_Block_irg(new_block);
/* mov ecx, <env> */
- val = ia32_create_Immediate(NULL, 0, 0xB9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ val = ia32_create_Immediate(irg, NULL, 0, 0xB9);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
addr.offset += 4;
/* jmp rel <callee> */
- val = ia32_create_Immediate(NULL, 0, 0xE9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ val = ia32_create_Immediate(irg, NULL, 0, 0xE9);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
case ir_bk_inner_trampoline:
return gen_inner_trampoline(node);
}
- panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
+ panic("Builtin %s not implemented", get_builtin_kind_name(kind));
}
/**
return get_Tuple_pred(new_node, 0);
}
}
- panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
+ panic("Builtin %s not implemented", get_builtin_kind_name(kind));
}
static ir_node *gen_be_IncSP(ir_node *node)
proj = pn_ia32_Call_X_regular;
} else {
arch_register_req_t const *const req = arch_get_irn_register_req(node);
- int const n_outs = arch_get_irn_n_outs(new_call);
- int i;
-
- assert(proj >= pn_be_Call_first_res);
- assert(req->type & arch_register_req_type_limited);
- for (i = 0; i < n_outs; ++i) {
- arch_register_req_t const *const new_req
- = arch_get_irn_register_req_out(new_call, i);
+ assert(proj >= pn_be_Call_first_res);
+ assert(arch_register_req_is(req, limited));
- if (!(new_req->type & arch_register_req_type_limited) ||
- new_req->cls != req->cls ||
+ be_foreach_out(new_call, i) {
+ arch_register_req_t const *const new_req = arch_get_irn_register_req_out(new_call, i);
+ if (!arch_register_req_is(new_req, limited) ||
+ new_req->cls != req->cls ||
*new_req->limited != *req->limited)
continue;
proj = i;
- break;
+ goto found;
}
- assert(i < n_outs);
+ panic("no matching out requirement found");
+found:;
}
res = new_rd_Proj(dbgi, new_call, mode, proj);
return res;
}
-/**
- * Transform the Projs from a Cmp.
- */
-static ir_node *gen_Proj_Cmp(ir_node *node)
-{
- /* this probably means not all mode_b nodes were lowered... */
- panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
- node);
-}
-
static ir_node *gen_Proj_ASM(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
return gen_Proj_be_AddSP(node);
case beo_Call:
return gen_Proj_be_Call(node);
- case iro_Cmp:
- return gen_Proj_Cmp(node);
case iro_Start:
proj = get_Proj_proj(node);
switch (proj) {
be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
- be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
+ be_set_transform_function(op_ia32_NoReg_FP, be_duplicate_node);
be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
be_set_transform_function(op_ia32_Push, be_duplicate_node);
be_set_transform_function(op_Switch, gen_Switch);
be_set_transform_function(op_SymConst, gen_SymConst);
be_set_transform_function(op_Unknown, ia32_gen_Unknown);
+
+ be_set_upper_bits_clean_function(op_Mux, ia32_mux_upper_bits_clean);
}
/**
static void ia32_pretransform_node(void)
{
ir_graph *irg = current_ir_graph;
- ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
- irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
+ irg_data->noreg_fp = be_pre_transform_node(irg_data->noreg_fp);
irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
ir_type *res_tp = get_method_res_type(mtp, j);
ir_node *res, *new_res;
- const ir_edge_t *edge, *next;
ir_mode *res_mode;
if (! is_atomic_type(res_tp)) {
continue;
}
- res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
+ res = be_get_Proj_for_pn(call, pn_ia32_Call_st0 + j);
new_res = NULL;
/* now patch the users */
- foreach_out_edge_safe(res, edge, next) {
+ foreach_out_edge_safe(res, edge) {
ir_node *succ = get_edge_src_irn(edge);
/* ignore Keeps */
ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
ir_mode *mode = get_ia32_ls_mode(succ);
- ir_node *st = new_bd_ia32_vfst(db, block, base, idx, mem, value, mode);
- //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_vfst_M);
+ ir_node *st = new_bd_ia32_fst(db, block, base, idx, mem, value, mode);
+ //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_fst_M);
set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
if (is_ia32_use_frame(succ))
set_ia32_use_frame(st);
set_irn_pinned(st, get_irn_pinned(succ));
set_ia32_op_type(st, ia32_AddrModeD);
- assert((long)pn_ia32_xStore_M == (long)pn_ia32_vfst_M);
- assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_vfst_X_regular);
- assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_vfst_X_except);
+ assert((long)pn_ia32_xStore_M == (long)pn_ia32_fst_M);
+ assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_fst_X_regular);
+ assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_fst_X_except);
exchange(succ, st);
ir_node *vfst_mem;
/* store st(0) on stack */
- vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem,
+ vfst = new_bd_ia32_fst(db, block, frame, noreg_GP, call_mem,
res, res_mode);
set_ia32_op_type(vfst, ia32_AddrModeD);
set_ia32_use_frame(vfst);
+ arch_add_irn_flags(vfst, arch_irn_flags_spill);
- vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_vfst_M);
+ vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_fst_M);
/* load into SSE register */
xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
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