/*
- * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
- *
* This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
*/
/**
* @brief This file implements the IR transformation from firm into
* ia32-Firm.
* @author Christian Wuerdig, Matthias Braun
- * @version $Id$
*/
#include "config.h"
#include "irprintf.h"
#include "debug.h"
#include "irdom.h"
+#include "iropt.h"
#include "error.h"
#include "array_t.h"
#include "heights.h"
-#include "../benode.h"
-#include "../besched.h"
-#include "../beabi.h"
-#include "../beutil.h"
-#include "../beirg.h"
-#include "../betranshlp.h"
-#include "../be_t.h"
+#include "benode.h"
+#include "besched.h"
+#include "beabi.h"
+#include "beutil.h"
+#include "betranshlp.h"
+#include "be_t.h"
#include "bearch_ia32_t.h"
#include "ia32_common_transform.h"
#include "ia32_new_nodes.h"
#include "ia32_dbg_stat.h"
#include "ia32_optimize.h"
-#include "ia32_util.h"
#include "ia32_address_mode.h"
#include "ia32_architecture.h"
/* define this to construct SSE constants instead of load them */
#undef CONSTRUCT_SSE_CONST
-
-#define SFP_SIGN "0x80000000"
-#define DFP_SIGN "0x8000000000000000"
-#define SFP_ABS "0x7FFFFFFF"
-#define DFP_ABS "0x7FFFFFFFFFFFFFFF"
-#define DFP_INTMAX "9223372036854775807"
-#define ULL_BIAS "18446744073709551616"
-
-#define ENT_SFP_SIGN "C_ia32_sfp_sign"
-#define ENT_DFP_SIGN "C_ia32_dfp_sign"
-#define ENT_SFP_ABS "C_ia32_sfp_abs"
-#define ENT_DFP_ABS "C_ia32_dfp_abs"
-#define ENT_ULL_BIAS "C_ia32_ull_bias"
-
-#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
+#define mode_fp (ia32_reg_classes[CLASS_ia32_fp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
+static ir_node *old_initial_fpcw = NULL;
static ir_node *initial_fpcw = NULL;
int ia32_no_pic_adjust;
typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
-static ir_node *create_immediate_or_transform(ir_node *node,
- char immediate_constraint_type);
+static ir_node *create_immediate_or_transform(ir_node *node);
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
dbg_info *dbgi, ir_node *block,
{
ir_graph *irg = current_ir_graph;
- if (be_get_irg_options(irg)->pic) {
+ if (be_options.pic) {
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
return arch_env->impl->get_pic_base(irg);
}
*/
static ir_node *gen_Const(ir_node *node)
{
- ir_node *old_block = get_nodes_block(node);
- ir_node *block = be_transform_node(old_block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
-
- assert(is_Const(node));
+ ir_node *old_block = get_nodes_block(node);
+ ir_node *block = be_transform_node(old_block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_tarval *tv = get_Const_tarval(node);
if (mode_is_float(mode)) {
- ir_node *res = NULL;
- ir_node *load;
- ir_node *base;
- ir_entity *floatent;
+ ir_graph *irg = get_irn_irg(node);
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ ia32_isa_t *isa = (ia32_isa_t*) arch_env;
+ ir_node *res = NULL;
+ ir_node *load;
+ ir_entity *floatent;
if (ia32_cg_config.use_sse2) {
- ir_tarval *tv = get_Const_tarval(node);
if (tarval_is_null(tv)) {
load = new_bd_ia32_xZero(dbgi, block);
set_ia32_ls_mode(load, mode);
#ifdef CONSTRUCT_SSE_CONST
} else if (tarval_is_one(tv)) {
int cnst = mode == mode_F ? 26 : 55;
- ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
- ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
+ ir_node *imm1 = ia32_create_Immediate(irg, NULL, 0, cnst);
+ ir_node *imm2 = ia32_create_Immediate(irg, NULL, 0, 2);
ir_node *pslld, *psrld;
load = new_bd_ia32_xAllOnes(dbgi, block);
set_ia32_ls_mode(load, mode);
res = load;
} else {
+ ir_node *base;
#ifdef CONSTRUCT_SSE_CONST
if (mode == mode_D) {
unsigned val = get_tarval_sub_bits(tv, 0) |
(get_tarval_sub_bits(tv, 2) << 16) |
(get_tarval_sub_bits(tv, 3) << 24);
if (val == 0) {
- ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
+ ir_node *imm32 = ia32_create_Immediate(irg, NULL, 0, 32);
ir_node *cnst, *psllq;
/* fine, lower 32bit are zero, produce 32bit value */
}
}
#endif /* CONSTRUCT_SSE_CONST */
- floatent = ia32_create_float_const_entity(node);
+ floatent = ia32_create_float_const_entity(isa, tv, NULL);
base = get_symconst_base();
load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
- arch_irn_add_flags(load, arch_irn_flags_rematerializable);
+ arch_add_irn_flags(load, arch_irn_flags_rematerializable);
res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
}
} else {
- if (is_Const_null(node)) {
- load = new_bd_ia32_vfldz(dbgi, block);
+ if (tarval_is_null(tv)) {
+ load = new_bd_ia32_fldz(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
- } else if (is_Const_one(node)) {
- load = new_bd_ia32_vfld1(dbgi, block);
+ } else if (tarval_is_one(tv)) {
+ load = new_bd_ia32_fld1(dbgi, block);
res = load;
set_ia32_ls_mode(load, mode);
} else {
ir_mode *ls_mode;
ir_node *base;
- floatent = ia32_create_float_const_entity(node);
+ floatent = ia32_create_float_const_entity(isa, tv, NULL);
/* create_float_const_ent is smart and sometimes creates
smaller entities */
ls_mode = get_type_mode(get_entity_type(floatent));
base = get_symconst_base();
- load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
- ls_mode);
+ load = new_bd_ia32_fld(dbgi, block, base, noreg_GP, nomem,
+ ls_mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
- arch_irn_add_flags(load, arch_irn_flags_rematerializable);
- res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
+ arch_add_irn_flags(load, arch_irn_flags_rematerializable);
+ res = new_r_Proj(load, mode_fp, pn_ia32_fld_res);
}
}
#ifdef CONSTRUCT_SSE_CONST
SET_IA32_ORIG_NODE(load, node);
return res;
} else { /* non-float mode */
- ir_node *cnst;
- ir_tarval *tv = get_Const_tarval(node);
- long val;
+ ir_node *cnst;
+ long val;
tv = tarval_convert_to(tv, mode_Iu);
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
- cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
+ cnst = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode_D);
else
- cnst = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem, mode_E);
+ cnst = new_bd_ia32_fld(dbgi, block, noreg_GP, noreg_GP, nomem, ia32_mode_E);
set_ia32_am_sc(cnst, get_SymConst_entity(node));
set_ia32_use_frame(cnst);
} else {
panic("backend only support symconst_addr_ent (at %+F)", node);
}
entity = get_SymConst_entity(node);
- cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
+ if (get_entity_owner(entity) == get_tls_type()) {
+ ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
+ ir_node *lea = new_bd_ia32_Lea(dbgi, block, tls_base, noreg_GP);
+ set_ia32_am_sc(lea, entity);
+ cnst = lea;
+ } else {
+ cnst = new_bd_ia32_Const(dbgi, block, entity, 0, 0, 0);
+ }
}
SET_IA32_ORIG_NODE(cnst, node);
return cnst;
}
-/**
- * Create a float type for the given mode and cache it.
- *
- * @param mode the mode for the float type (might be integer mode for SSE2 types)
- * @param align alignment
- */
-static ir_type *ia32_create_float_type(ir_mode *mode, unsigned align)
+static ir_type *make_array_type(ir_type *tp)
{
- ir_type *tp;
-
- assert(align <= 16);
-
- if (mode == mode_Iu) {
- static ir_type *int_Iu[16] = {NULL, };
-
- if (int_Iu[align] == NULL) {
- int_Iu[align] = tp = new_type_primitive(mode);
- /* set the specified alignment */
- set_type_alignment_bytes(tp, align);
- }
- return int_Iu[align];
- } else if (mode == mode_Lu) {
- static ir_type *int_Lu[16] = {NULL, };
-
- if (int_Lu[align] == NULL) {
- int_Lu[align] = tp = new_type_primitive(mode);
- /* set the specified alignment */
- set_type_alignment_bytes(tp, align);
- }
- return int_Lu[align];
- } else if (mode == mode_F) {
- static ir_type *float_F[16] = {NULL, };
-
- if (float_F[align] == NULL) {
- float_F[align] = tp = new_type_primitive(mode);
- /* set the specified alignment */
- set_type_alignment_bytes(tp, align);
- }
- return float_F[align];
- } else if (mode == mode_D) {
- static ir_type *float_D[16] = {NULL, };
-
- if (float_D[align] == NULL) {
- float_D[align] = tp = new_type_primitive(mode);
- /* set the specified alignment */
- set_type_alignment_bytes(tp, align);
- }
- return float_D[align];
- } else {
- static ir_type *float_E[16] = {NULL, };
-
- if (float_E[align] == NULL) {
- float_E[align] = tp = new_type_primitive(mode);
- /* set the specified alignment */
- set_type_alignment_bytes(tp, align);
- }
- return float_E[align];
- }
+ unsigned alignment = get_type_alignment_bytes(tp);
+ unsigned size = get_type_size_bytes(tp);
+ ir_type *res = new_type_array(1, tp);
+ set_type_alignment_bytes(res, alignment);
+ set_array_bounds_int(res, 0, 0, 2);
+ if (alignment > size)
+ size = alignment;
+ set_type_size_bytes(res, 2 * size);
+ set_type_state(res, layout_fixed);
+ return res;
}
/**
static ir_type *ia32_create_float_array(ir_type *tp)
{
ir_mode *mode = get_type_mode(tp);
- unsigned align = get_type_alignment_bytes(tp);
ir_type *arr;
- assert(align <= 16);
-
if (mode == mode_F) {
- static ir_type *float_F[16] = {NULL, };
+ static ir_type *float_F;
- if (float_F[align] != NULL)
- return float_F[align];
- arr = float_F[align] = new_type_array(1, tp);
+ arr = float_F;
+ if (arr == NULL)
+ arr = float_F = make_array_type(tp);
} else if (mode == mode_D) {
- static ir_type *float_D[16] = {NULL, };
+ static ir_type *float_D;
- if (float_D[align] != NULL)
- return float_D[align];
- arr = float_D[align] = new_type_array(1, tp);
+ arr = float_D;
+ if (arr == NULL)
+ arr = float_D = make_array_type(tp);
} else {
- static ir_type *float_E[16] = {NULL, };
+ static ir_type *float_E;
- if (float_E[align] != NULL)
- return float_E[align];
- arr = float_E[align] = new_type_array(1, tp);
+ arr = float_E;
+ if (arr == NULL)
+ arr = float_E = make_array_type(tp);
}
- set_type_alignment_bytes(arr, align);
- set_type_size_bytes(arr, 2 * get_type_size_bytes(tp));
- set_type_state(arr, layout_fixed);
return arr;
}
ir_entity *ia32_gen_fp_known_const(ia32_known_const_t kct)
{
static const struct {
- const char *ent_name;
+ const char *name;
const char *cnst_str;
- char mode;
- unsigned char align;
+ char mode;
} names [ia32_known_const_max] = {
- { ENT_SFP_SIGN, SFP_SIGN, 0, 16 }, /* ia32_SSIGN */
- { ENT_DFP_SIGN, DFP_SIGN, 1, 16 }, /* ia32_DSIGN */
- { ENT_SFP_ABS, SFP_ABS, 0, 16 }, /* ia32_SABS */
- { ENT_DFP_ABS, DFP_ABS, 1, 16 }, /* ia32_DABS */
- { ENT_ULL_BIAS, ULL_BIAS, 2, 4 } /* ia32_ULLBIAS */
+ { "C_sfp_sign", "0x80000000", 0 },
+ { "C_dfp_sign", "0x8000000000000000", 1 },
+ { "C_sfp_abs", "0x7FFFFFFF", 0 },
+ { "C_dfp_abs", "0x7FFFFFFFFFFFFFFF", 1 },
+ { "C_ull_bias", "0x10000000000000000", 2 }
};
static ir_entity *ent_cache[ia32_known_const_max];
- const char *ent_name, *cnst_str;
- ir_type *tp;
- ir_entity *ent;
- ir_tarval *tv;
- ir_mode *mode;
-
- ent_name = names[kct].ent_name;
- if (! ent_cache[kct]) {
- cnst_str = names[kct].cnst_str;
+ ir_entity *ent = ent_cache[kct];
+ if (ent == NULL) {
+ ir_graph *irg = current_ir_graph;
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ ia32_isa_t *isa = (ia32_isa_t*) arch_env;
+ const char *cnst_str = names[kct].cnst_str;
+ ident *name = new_id_from_str(names[kct].name);
+ ir_mode *mode;
+ ir_tarval *tv;
switch (names[kct].mode) {
case 0: mode = mode_Iu; break;
case 1: mode = mode_Lu; break;
- default: mode = mode_F; break;
+ case 2: mode = mode_F; break;
+ default: panic("internal compiler error");
}
- tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
- tp = ia32_create_float_type(mode, names[kct].align);
+ tv = new_tarval_from_str(cnst_str, strlen(cnst_str), mode);
- if (kct == ia32_ULLBIAS)
- tp = ia32_create_float_array(tp);
- ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
+ if (kct == ia32_ULLBIAS) {
+ ir_type *type = ia32_get_prim_type(mode_F);
+ ir_type *atype = ia32_create_float_array(type);
+ ir_initializer_t *initializer;
- set_entity_ld_ident(ent, get_entity_ident(ent));
- add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
- set_entity_visibility(ent, ir_visibility_private);
+ ent = new_entity(get_glob_type(), name, atype);
- if (kct == ia32_ULLBIAS) {
- ir_initializer_t *initializer = create_initializer_compound(2);
+ set_entity_ld_ident(ent, name);
+ set_entity_visibility(ent, ir_visibility_private);
+ add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
+ initializer = create_initializer_compound(2);
set_initializer_compound_value(initializer, 0,
create_initializer_tarval(get_mode_null(mode)));
set_initializer_compound_value(initializer, 1,
create_initializer_tarval(tv));
-
set_entity_initializer(ent, initializer);
} else {
- set_entity_initializer(ent, create_initializer_tarval(tv));
+ ent = ia32_create_float_const_entity(isa, tv, name);
}
-
/* cache the entry */
ent_cache[kct] = ent;
}
* input here, for unary operations use NULL).
*/
static int ia32_use_source_address_mode(ir_node *block, ir_node *node,
- ir_node *other, ir_node *other2, match_flags_t flags)
+ ir_node *other, ir_node *other2,
+ match_flags_t flags)
{
ir_node *load;
+ ir_mode *mode;
long pn;
/* float constants are always available */
if (is_Const(node)) {
- ir_mode *mode = get_irn_mode(node);
+ mode = get_irn_mode(node);
if (mode_is_float(mode)) {
+ ir_tarval *tv = get_Const_tarval(node);
+ if (!tarval_ieee754_can_conv_lossless(tv, mode_D))
+ return 0;
if (ia32_cg_config.use_sse2) {
if (is_simple_sse_Const(node))
return 0;
return 0;
return 1;
}
+ return 0;
}
if (!is_Proj(node))
return 0;
if (get_nodes_block(load) != block)
return 0;
+ mode = get_irn_mode(node);
+ /* we can't fold mode_E AM */
+ if (mode == ia32_mode_E)
+ return 0;
/* we only use address mode if we're the only user of the load */
if (get_irn_n_edges(node) != (flags & match_two_users ? 2 : 1))
return 0;
/* floating point immediates */
if (is_Const(node)) {
- ir_entity *entity = ia32_create_float_const_entity(node);
+ ir_graph *irg = get_irn_irg(node);
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ ia32_isa_t *isa = (ia32_isa_t*) arch_env;
+ ir_tarval *tv = get_Const_tarval(node);
+ ir_entity *entity = ia32_create_float_const_entity(isa, tv, NULL);
addr->base = get_symconst_base();
addr->index = noreg_GP;
addr->mem = nomem;
addr->symconst_ent = entity;
+ addr->tls_segment = false;
addr->use_frame = 1;
am->ls_mode = get_type_mode(get_entity_type(entity));
am->pinned = op_pin_state_floats;
set_ia32_am_scale(node, addr->scale);
set_ia32_am_sc(node, addr->symconst_ent);
set_ia32_am_offs_int(node, addr->offset);
+ set_ia32_am_tls_segment(node, addr->tls_segment);
if (addr->symconst_sign)
set_ia32_am_sc_sign(node);
if (addr->use_frame)
}
/**
- * Check, if a given node is a Down-Conv, ie. a integer Conv
+ * Check, if a given node is a Down-Conv, i.e. a integer Conv
* from a mode with a mode with more bits to a mode with lesser bits.
* Moreover, we return only true if the node has not more than 1 user.
*
if (!is_Conv(node))
return 0;
- /* we only want to skip the conv when we're the only user
- * (because this test is used in the context of address-mode selection
- * and we don't want to use address mode for multiple users) */
- if (get_irn_n_edges(node) > 1)
- return 0;
-
src_mode = get_irn_mode(get_Conv_op(node));
dest_mode = get_irn_mode(node);
return
/** Skip all Down-Conv's on a given node and return the resulting node. */
ir_node *ia32_skip_downconv(ir_node *node)
{
- while (is_downconv(node))
+ while (is_downconv(node)) {
+ /* we only want to skip the conv when we're the only user
+ * (because this test is used in the context of address-mode selection
+ * and we don't want to use address mode for multiple users) */
+ if (get_irn_n_edges(node) > 1)
+ break;
+
node = get_Conv_op(node);
+ }
+
+ return node;
+}
+
+static bool is_float_downconv(const ir_node *node)
+{
+ if (!is_Conv(node))
+ return false;
+ ir_node *pred = get_Conv_op(node);
+ ir_mode *pred_mode = get_irn_mode(pred);
+ ir_mode *mode = get_irn_mode(node);
+ return mode_is_float(pred_mode)
+ && get_mode_size_bits(mode) <= get_mode_size_bits(pred_mode);
+}
+static ir_node *ia32_skip_float_downconv(ir_node *node)
+{
+ while (is_float_downconv(node)) {
+ node = get_Conv_op(node);
+ }
return node;
}
/** Skip all signedness convs */
static ir_node *ia32_skip_sameconv(ir_node *node)
{
- while (is_sameconv(node))
+ while (is_sameconv(node)) {
node = get_Conv_op(node);
+ }
return node;
}
-static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
+static ir_node *transform_sext(ir_node *node, ir_node *orig_node)
{
- ir_mode *mode = get_irn_mode(node);
- ir_node *block;
- ir_mode *tgt_mode;
- dbg_info *dbgi;
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ return create_I2I_Conv(mode, mode_Is, dbgi, block, node, orig_node);
+}
+
+static ir_node *transform_zext(ir_node *node, ir_node *orig_node)
+{
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *block = get_nodes_block(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ /* normalize to an unsigned mode */
+ switch (get_mode_size_bits(mode)) {
+ case 8: mode = mode_Bu; break;
+ case 16: mode = mode_Hu; break;
+ default:
+ panic("ia32: invalid mode in zest: %+F", node);
+ }
+ return create_I2I_Conv(mode, mode_Iu, dbgi, block, node, orig_node);
+}
+static ir_node *transform_upconv(ir_node *node, ir_node *orig_node)
+{
+ ir_mode *mode = get_irn_mode(node);
if (mode_is_signed(mode)) {
- tgt_mode = mode_Is;
+ return transform_sext(node, orig_node);
} else {
- tgt_mode = mode_Iu;
+ return transform_zext(node, orig_node);
}
- block = get_nodes_block(node);
- dbgi = get_irn_dbg_info(node);
+}
- return create_I2I_Conv(mode, tgt_mode, dbgi, block, node, orig_node);
+static ir_node *get_noreg(ir_mode *const mode)
+{
+ if (!mode_is_float(mode)) {
+ return noreg_GP;
+ } else if (ia32_cg_config.use_sse2) {
+ return ia32_new_NoReg_xmm(current_ir_graph);
+ } else {
+ return ia32_new_NoReg_fp(current_ir_graph);
+ }
}
/**
* op2 input */
new_op2 = NULL;
if (!(flags & match_try_am) && use_immediate) {
- new_op2 = ia32_try_create_Immediate(op2, 0);
+ new_op2 = ia32_try_create_Immediate(op2, 'i');
}
if (new_op2 == NULL &&
use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
build_address(am, op2, ia32_create_am_normal);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
- if (mode_is_float(mode)) {
- new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
- } else {
- new_op2 = noreg_GP;
- }
+ new_op2 = get_noreg(mode);
am->op_type = ia32_AddrModeS;
} else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
use_am &&
ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
- ir_node *noreg;
build_address(am, op1, ia32_create_am_normal);
- if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_vfp(current_ir_graph);
- } else {
- noreg = noreg_GP;
- }
-
+ ir_node *const noreg = get_noreg(mode);
if (new_op2 != NULL) {
new_op1 = noreg;
} else {
}
am->op_type = ia32_AddrModeS;
} else {
- ir_mode *mode;
am->op_type = ia32_Normal;
if (flags & match_try_am) {
}
mode = get_irn_mode(op2);
- if (flags & match_upconv_32 && get_mode_size_bits(mode) != 32) {
- new_op1 = (op1 == NULL ? NULL : create_upconv(op1, NULL));
- if (new_op2 == NULL)
- new_op2 = create_upconv(op2, NULL);
- am->ls_mode = mode_Iu;
+ if (get_mode_size_bits(mode) != 32
+ && (flags & (match_mode_neutral | match_upconv | match_zero_ext))) {
+ if (flags & match_upconv) {
+ new_op1 = (op1 == NULL ? NULL : transform_upconv(op1, op1));
+ if (new_op2 == NULL)
+ new_op2 = transform_upconv(op2, op2);
+ } else if (flags & match_zero_ext) {
+ new_op1 = (op1 == NULL ? NULL : transform_zext(op1, op1));
+ if (new_op2 == NULL)
+ new_op2 = transform_zext(op2, op2);
+ } else {
+ new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
+ if (new_op2 == NULL)
+ new_op2 = be_transform_node(op2);
+ assert(flags & match_mode_neutral);
+ }
+ mode = mode_Iu;
} else {
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (new_op2 == NULL)
new_op2 = be_transform_node(op2);
- am->ls_mode = (flags & match_mode_neutral) ? mode_Iu : mode;
}
+ am->ls_mode = mode;
}
if (addr->base == NULL)
addr->base = noreg_GP;
static ir_node *get_fpcw(void)
{
- ir_node *fpcw;
if (initial_fpcw != NULL)
return initial_fpcw;
- fpcw = be_abi_get_ignore_irn(be_get_irg_abi(current_ir_graph),
- &ia32_registers[REG_FPCW]);
- initial_fpcw = be_transform_node(fpcw);
-
+ initial_fpcw = be_transform_node(old_initial_fpcw);
return initial_fpcw;
}
+static ir_node *skip_float_upconv(ir_node *node)
+{
+ ir_mode *mode = get_irn_mode(node);
+ assert(mode_is_float(mode));
+
+ while (is_Conv(node)) {
+ ir_node *pred = get_Conv_op(node);
+ ir_mode *pred_mode = get_irn_mode(pred);
+
+ /**
+ * suboptimal, but without this check the address mode matcher
+ * can incorrectly think that something has only 1 user
+ */
+ if (get_irn_n_edges(node) > 1)
+ break;
+
+ if (!mode_is_float(pred_mode)
+ || get_mode_size_bits(pred_mode) > get_mode_size_bits(mode))
+ break;
+ node = pred;
+ mode = pred_mode;
+ }
+ return node;
+}
+
+static void check_x87_floatmode(ir_mode *mode)
+{
+ if (mode != ia32_mode_E) {
+ panic("ia32: x87 only supports x86 extended float mode");
+ }
+}
+
/**
* Construct a standard binary operation, set AM and immediate if required.
*
static ir_node *gen_binop_x87_float(ir_node *node, ir_node *op1, ir_node *op2,
construct_binop_float_func *func)
{
- ir_mode *mode = get_irn_mode(node);
dbg_info *dbgi;
- ir_node *block, *new_block, *new_node;
+ ir_node *block;
+ ir_node *new_block;
+ ir_node *new_node;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
ia32_x87_attr_t *attr;
/* All operations are considered commutative, because there are reverse
* variants */
- match_flags_t flags = match_commutative;
+ match_flags_t flags = match_commutative | match_am;
+ ir_mode *mode
+ = is_Div(node) ? get_Div_resmode(node) : get_irn_mode(node);
+ check_x87_floatmode(mode);
- /* happens for div nodes... */
- if (mode == mode_T) {
- if (is_Div(node))
- mode = get_Div_resmode(node);
- else
- panic("can't determine mode");
- }
-
- /* cannot use address mode with long double on x87 */
- if (get_mode_size_bits(mode) <= 64)
- flags |= match_am;
+ op1 = skip_float_upconv(op1);
+ op2 = skip_float_upconv(op2);
block = get_nodes_block(node);
match_arguments(&am, block, op1, op2, NULL, flags);
construct_shift_func *func,
match_flags_t flags)
{
- dbg_info *dbgi;
- ir_node *block, *new_block, *new_op1, *new_op2, *new_node;
+ ir_mode *mode = get_irn_mode(node);
- assert(! mode_is_float(get_irn_mode(node)));
+ assert(! mode_is_float(mode));
assert(flags & match_immediate);
- assert((flags & ~(match_mode_neutral | match_immediate)) == 0);
+ assert((flags & ~(match_mode_neutral | match_zero_ext | match_upconv | match_immediate)) == 0);
+
+ if (get_mode_modulo_shift(mode) != 32) {
+ /* TODO: implement special cases for non-modulo shifts */
+ panic("modulo shift!=32 not supported by ia32 backend");
+ }
+ ir_node *new_op1;
+ ir_node *new_op2;
if (flags & match_mode_neutral) {
op1 = ia32_skip_downconv(op1);
new_op1 = be_transform_node(op1);
- } else if (get_mode_size_bits(get_irn_mode(node)) != 32) {
- new_op1 = create_upconv(op1, node);
} else {
- new_op1 = be_transform_node(op1);
+ op1 = ia32_skip_sameconv(op1);
+ if (get_mode_size_bits(mode) != 32) {
+ if (flags & match_upconv) {
+ new_op1 = transform_upconv(op1, node);
+ } else if (flags & match_zero_ext) {
+ new_op1 = transform_zext(op1, node);
+ } else {
+ /* match_mode_neutral not handled here because it makes no
+ * sense for shift operations */
+ panic("ia32 code selection failed for %+F", node);
+ }
+ } else {
+ new_op1 = be_transform_node(op1);
+ }
}
/* the shift amount can be any mode that is bigger than 5 bits, since all
op2 = op;
assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
}
- new_op2 = create_immediate_or_transform(op2, 0);
+ new_op2 = create_immediate_or_transform(op2);
- dbgi = get_irn_dbg_info(node);
- block = get_nodes_block(node);
- new_block = be_transform_node(block);
- new_node = func(dbgi, new_block, new_op1, new_op2);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_node = func(dbgi, new_block, new_op1, new_op2);
SET_IA32_ORIG_NODE(new_node, node);
/* lowered shift instruction may have a dependency operand, handle it here */
static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
ia32_address_t *addr)
{
- ir_node *base, *index, *res;
+ ir_node *base;
+ ir_node *idx;
+ ir_node *res;
base = addr->base;
if (base == NULL) {
base = be_transform_node(base);
}
- index = addr->index;
- if (index == NULL) {
- index = noreg_GP;
+ idx = addr->index;
+ if (idx == NULL) {
+ idx = noreg_GP;
} else {
- index = be_transform_node(index);
+ idx = be_transform_node(idx);
}
- res = new_bd_ia32_Lea(dbgi, block, base, index);
+ /* segment overrides are ineffective for Leas :-( so we have to patch
+ * around... */
+ if (addr->tls_segment) {
+ ir_node *tls_base = new_bd_ia32_LdTls(NULL, block);
+ assert(addr->symconst_ent != NULL);
+ if (base == noreg_GP)
+ base = tls_base;
+ else
+ base = new_bd_ia32_Lea(dbgi, block, tls_base, base);
+ addr->tls_segment = false;
+ }
+
+ res = new_bd_ia32_Lea(dbgi, block, base, idx);
set_address(res, addr);
return res;
|| addr->frame_entity || addr->use_frame;
}
+typedef ir_node* (*new_shiftd_func)(dbg_info *dbgi, ir_node *block,
+ ir_node *high, ir_node *low,
+ ir_node *count);
+
+/**
+ * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
+ * op1 - target to be shifted
+ * op2 - contains bits to be shifted into target
+ * op3 - shift count
+ * Only op3 can be an immediate.
+ */
+static ir_node *gen_64bit_shifts(dbg_info *dbgi, ir_node *block,
+ ir_node *high, ir_node *low, ir_node *count,
+ new_shiftd_func func)
+{
+ ir_node *new_block = be_transform_node(block);
+ ir_node *new_high = be_transform_node(high);
+ ir_node *new_low = be_transform_node(low);
+ ir_node *new_count;
+ ir_node *new_node;
+
+ /* the shift amount can be any mode that is bigger than 5 bits, since all
+ * other bits are ignored anyway */
+ while (is_Conv(count) &&
+ get_irn_n_edges(count) == 1 &&
+ mode_is_int(get_irn_mode(count))) {
+ assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
+ count = get_Conv_op(count);
+ }
+ new_count = create_immediate_or_transform(count);
+
+ new_node = func(dbgi, new_block, new_high, new_low, new_count);
+ return new_node;
+}
+
+/**
+ * Tests whether 2 values result in 'x' and '32-x' when interpreted as a shift
+ * value.
+ */
+static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
+{
+ if (is_Const(value1) && is_Const(value2)) {
+ ir_tarval *tv1 = get_Const_tarval(value1);
+ ir_tarval *tv2 = get_Const_tarval(value2);
+ if (tarval_is_long(tv1) && tarval_is_long(tv2)) {
+ long v1 = get_tarval_long(tv1);
+ long v2 = get_tarval_long(tv2);
+ return v1 <= v2 && v2 == 32-v1;
+ }
+ }
+ return false;
+}
+
+static ir_node *match_64bit_shift(ir_node *node)
+{
+ ir_node *op1 = get_binop_left(node);
+ ir_node *op2 = get_binop_right(node);
+ assert(is_Or(node) || is_Add(node));
+
+ if (is_Shr(op1)) {
+ ir_node *tmp = op1;
+ op1 = op2;
+ op2 = tmp;
+ }
+
+ /* match ShlD operation */
+ if (is_Shl(op1) && is_Shr(op2)) {
+ ir_node *shl_right = get_Shl_right(op1);
+ ir_node *shl_left = get_Shl_left(op1);
+ ir_node *shr_right = get_Shr_right(op2);
+ ir_node *shr_left = get_Shr_left(op2);
+ /* constant ShlD operation */
+ if (is_complementary_shifts(shl_right, shr_right)) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ return gen_64bit_shifts(dbgi, block, shl_left, shr_left, shl_right,
+ new_bd_ia32_ShlD);
+ }
+ /* constant ShrD operation */
+ if (is_complementary_shifts(shr_right, shl_right)) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ return gen_64bit_shifts(dbgi, block, shr_left, shl_left, shr_right,
+ new_bd_ia32_ShrD);
+ }
+ /* lower_dw produces the following for ShlD:
+ * Or(Shr(Shr(high,1),Not(c)),Shl(low,c)) */
+ if (is_Shr(shr_left) && is_Not(shr_right)
+ && is_Const_1(get_Shr_right(shr_left))
+ && get_Not_op(shr_right) == shl_right) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *val_h = get_Shr_left(shr_left);
+ return gen_64bit_shifts(dbgi, block, shl_left, val_h, shl_right,
+ new_bd_ia32_ShlD);
+ }
+ /* lower_dw produces the following for ShrD:
+ * Or(Shl(Shl(high,1),Not(c)), Shr(low,c)) */
+ if (is_Shl(shl_left) && is_Not(shl_right)
+ && is_Const_1(get_Shl_right(shl_left))
+ && get_Not_op(shl_right) == shr_right) {
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *val_h = get_Shl_left(shl_left);
+ return gen_64bit_shifts(dbgi, block, shr_left, val_h, shr_right,
+ new_bd_ia32_ShrD);
+ }
+ }
+
+ return NULL;
+}
+
/**
* Creates an ia32 Add.
*
ia32_address_t addr;
ia32_address_mode_t am;
+ new_node = match_64bit_shift(node);
+ if (new_node != NULL)
+ return new_node;
+
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2)
return gen_binop(node, op1, op2, new_bd_ia32_xAdd,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfadd);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fadd);
}
ia32_mark_non_am(node);
- op2 = ia32_skip_downconv(op2);
- op1 = ia32_skip_downconv(op1);
-
/**
* Rules for an Add:
* 0. Immediate Trees (example Add(Symconst, Const) -> Const)
return gen_binop(node, op1, op2, new_bd_ia32_xMul,
match_commutative | match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfmul);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fmul);
}
return gen_binop(node, op1, op2, new_bd_ia32_IMul,
match_commutative | match_am | match_mode_neutral |
match_commutative | match_mode_neutral | match_am | match_immediate);
}
-
-
/**
* Creates an ia32 Or.
*
{
ir_node *op1 = get_Or_left(node);
ir_node *op2 = get_Or_right(node);
+ ir_node *res;
+
+ res = match_64bit_shift(node);
+ if (res != NULL)
+ return res;
assert (! mode_is_float(get_irn_mode(node)));
return gen_binop(node, op1, op2, new_bd_ia32_Or, match_commutative
if (ia32_cg_config.use_sse2)
return gen_binop(node, op1, op2, new_bd_ia32_xSub, match_am);
else
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfsub);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fsub);
}
if (is_Const(op2)) {
ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
res = new_bd_ia32_Cltd(dbgi, block, val, pval);
} else {
- ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
+ ir_graph *const irg = get_Block_irg(block);
+ ir_node *const imm31 = ia32_create_Immediate(irg, NULL, 0, 31);
res = new_bd_ia32_Sar(dbgi, block, val, imm31);
}
SET_IA32_ORIG_NODE(res, orig);
*/
static ir_node *create_Div(ir_node *node)
{
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ int throws_exception = ir_throws_exception(node);
ir_node *mem;
ir_node *new_mem;
ir_node *op1;
panic("invalid divmod node %+F", node);
}
- match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv_32);
+ match_arguments(&am, block, op1, op2, NULL, match_am | match_upconv);
/* Beware: We don't need a Sync, if the memory predecessor of the Div node
is the memory of the consumed address. We can have only the second op as address
addr->index, new_mem, am.new_op2,
am.new_op1, sign_extension);
}
+ ir_set_throws_exception(new_node, throws_exception);
set_irn_pinned(new_node, get_irn_pinned(node));
if (ia32_cg_config.use_sse2) {
return gen_binop(node, op1, op2, new_bd_ia32_xDiv, match_am);
} else {
- return gen_binop_x87_float(node, op1, op2, new_bd_ia32_vfdiv);
+ return gen_binop_x87_float(node, op1, op2, new_bd_ia32_fdiv);
}
}
ir_node *left = get_Shr_left(node);
ir_node *right = get_Shr_right(node);
- return gen_shift_binop(node, left, right, new_bd_ia32_Shr, match_immediate);
+ return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
+ match_immediate | match_zero_ext);
}
-
-
/**
* Creates an ia32 Sar.
*
}
}
- return gen_shift_binop(node, left, right, new_bd_ia32_Sar, match_immediate);
+ return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
+ match_immediate | match_upconv);
}
set_ia32_op_type(new_node, ia32_AddrModeS);
set_ia32_ls_mode(new_node, mode);
} else {
- new_node = new_bd_ia32_vfchs(dbgi, block, new_op);
+ new_node = new_bd_ia32_fchs(dbgi, block, new_op);
}
} else {
new_node = gen_unop(node, op, new_bd_ia32_Neg, match_mode_neutral);
ir_node *op = get_Not_op(node);
assert(get_irn_mode(node) != mode_b); /* should be lowered already */
- assert (! mode_is_float(get_irn_mode(node)));
+ assert(!mode_is_float(get_irn_mode(node)));
return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
}
-static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
- bool negate, ir_node *node)
+static ir_node *create_float_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
+ bool negate, ir_node *node)
{
ir_node *new_block = be_transform_node(block);
ir_mode *mode = get_irn_mode(op);
- ir_node *new_op;
+ ir_node *new_op = be_transform_node(op);
ir_node *new_node;
int size;
ir_entity *ent;
- if (mode_is_float(mode)) {
- new_op = be_transform_node(op);
+ assert(mode_is_float(mode));
- if (ia32_cg_config.use_sse2) {
- ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
- new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
- noreg_GP, nomem, new_op, noreg_fp);
+ if (ia32_cg_config.use_sse2) {
+ ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
+ new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
+ noreg_GP, nomem, new_op, noreg_fp);
- size = get_mode_size_bits(mode);
- ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
+ size = get_mode_size_bits(mode);
+ ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
- set_ia32_am_sc(new_node, ent);
+ set_ia32_am_sc(new_node, ent);
- SET_IA32_ORIG_NODE(new_node, node);
+ SET_IA32_ORIG_NODE(new_node, node);
- set_ia32_op_type(new_node, ia32_AddrModeS);
- set_ia32_ls_mode(new_node, mode);
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode);
- /* TODO, implement -Abs case */
- assert(!negate);
- } else {
- new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
- SET_IA32_ORIG_NODE(new_node, node);
- if (negate) {
- new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
- SET_IA32_ORIG_NODE(new_node, node);
- }
- }
+ /* TODO, implement -Abs case */
+ assert(!negate);
} else {
- ir_node *xorn;
- ir_node *sign_extension;
-
- if (get_mode_size_bits(mode) == 32) {
- new_op = be_transform_node(op);
- } else {
- new_op = create_I2I_Conv(mode, mode_Is, dbgi, block, op, node);
- }
-
- sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
-
- xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_op, sign_extension);
- SET_IA32_ORIG_NODE(xorn, node);
-
+ check_x87_floatmode(mode);
+ new_node = new_bd_ia32_fabs(dbgi, new_block, new_op);
+ SET_IA32_ORIG_NODE(new_node, node);
if (negate) {
- new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, sign_extension, xorn);
- } else {
- new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, xorn, sign_extension);
+ new_node = new_bd_ia32_fchs(dbgi, new_block, new_node);
+ SET_IA32_ORIG_NODE(new_node, node);
}
- SET_IA32_ORIG_NODE(new_node, node);
}
return new_node;
}
static ia32_condition_code_t relation_to_condition_code(ir_relation relation,
- ir_mode *mode)
+ ir_mode *mode,
+ bool overflow_possible)
{
if (mode_is_float(mode)) {
switch (relation) {
case ir_relation_unordered_equal:
case ir_relation_equal: return ia32_cc_equal;
case ir_relation_unordered_less:
- case ir_relation_less: return ia32_cc_less;
+ case ir_relation_less:
+ return overflow_possible ? ia32_cc_less : ia32_cc_sign;
case ir_relation_unordered_less_equal:
case ir_relation_less_equal: return ia32_cc_less_equal;
case ir_relation_unordered_greater:
case ir_relation_greater: return ia32_cc_greater;
case ir_relation_unordered_greater_equal:
- case ir_relation_greater_equal: return ia32_cc_greater_equal;
+ case ir_relation_greater_equal:
+ return overflow_possible ? ia32_cc_greater_equal : ia32_cc_not_sign;
case ir_relation_unordered_less_greater:
case ir_relation_less_greater: return ia32_cc_not_equal;
case ir_relation_less_equal_greater:
}
}
-static ir_node *get_flags_mode_b(ir_node *node, ia32_condition_code_t *cc_out)
-{
- /* a mode_b value, we have to compare it against 0 */
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_block = be_transform_node(get_nodes_block(node));
- ir_node *new_op = be_transform_node(node);
- ir_node *flags = new_bd_ia32_Test(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_op, new_op, false);
- *cc_out = ia32_cc_not_equal;
- return flags;
-}
-
-static ir_node *get_flags_node_cmp(ir_node *cmp, ia32_condition_code_t *cc_out)
+static ir_node *get_flags_node(ir_node *cmp, ia32_condition_code_t *cc_out)
{
/* must have a Cmp as input */
ir_relation relation = get_Cmp_relation(cmp);
- ir_relation possible;
ir_node *l = get_Cmp_left(cmp);
ir_node *r = get_Cmp_right(cmp);
ir_mode *mode = get_irn_mode(l);
+ bool overflow_possible;
ir_node *flags;
/* check for bit-test */
- if (ia32_cg_config.use_bt && (relation == ir_relation_equal
- || (mode_is_signed(mode) && relation == ir_relation_less_greater)
- || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))
- && is_And(l)) {
+ if (ia32_cg_config.use_bt
+ && (relation == ir_relation_equal
+ || (mode_is_signed(mode) && relation == ir_relation_less_greater)
+ || (!mode_is_signed(mode) && ((relation & ir_relation_greater_equal) == ir_relation_greater)))
+ && is_And(l)) {
ir_node *la = get_And_left(l);
ir_node *ra = get_And_right(l);
if (is_Shl(ra)) {
if (is_Const_1(c) && is_Const_0(r)) {
/* (1 << n) & ra) */
ir_node *n = get_Shl_right(la);
- flags = gen_bt(cmp, ra, n);
+ flags = gen_bt(cmp, ra, n);
/* the bit is copied into the CF flag */
if (relation & ir_relation_equal)
*cc_out = ia32_cc_above_equal; /* test for CF=0 */
}
}
- /* the middle-end tries to eliminate impossible relations, so a ptr != 0
+ /* the middle-end tries to eliminate impossible relations, so a ptr <> 0
* test becomes ptr > 0. But for x86 an equal comparison is preferable to
* a >0 (we can sometimes eliminate the cmp in favor of flags produced by
- * a predecessor node). So add the < bit */
- possible = ir_get_possible_cmp_relations(l, r);
- if (((relation & ir_relation_less) && !(possible & ir_relation_greater))
- || ((relation & ir_relation_greater) && !(possible & ir_relation_less)))
- relation |= ir_relation_less_greater;
+ * a predecessor node). So add the < bit.
+ * (Note that we do not want to produce <=> (which can happen for
+ * unoptimized code), because no x86 flag can represent that */
+ if (!(relation & ir_relation_equal) && relation & ir_relation_less_greater)
+ relation |= get_negated_relation(ir_get_possible_cmp_relations(l, r)) & ir_relation_less_greater;
+
+ overflow_possible = true;
+ if (is_Const(r) && is_Const_null(r))
+ overflow_possible = false;
/* just do a normal transformation of the Cmp */
- *cc_out = relation_to_condition_code(relation, mode);
+ *cc_out = relation_to_condition_code(relation, mode, overflow_possible);
flags = be_transform_node(cmp);
return flags;
}
-/**
- * Transform a node returning a "flag" result.
- *
- * @param node the node to transform
- * @param cc_out the compare mode to use
- */
-static ir_node *get_flags_node(ir_node *node, ia32_condition_code_t *cc_out)
-{
- if (is_Cmp(node))
- return get_flags_node_cmp(node, cc_out);
- assert(get_irn_mode(node) == mode_b);
- return get_flags_mode_b(node, cc_out);
-}
-
/**
* Transforms a Load.
*
ir_node *new_mem = be_transform_node(mem);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_Load_mode(node);
+ int throws_exception = ir_throws_exception(node);
ir_node *base;
- ir_node *index;
+ ir_node *idx;
ir_node *new_node;
ia32_address_t addr;
/* construct load address */
memset(&addr, 0, sizeof(addr));
ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
- base = addr.base;
- index = addr.index;
+ base = addr.base;
+ idx = addr.index;
if (base == NULL) {
base = noreg_GP;
base = be_transform_node(base);
}
- if (index == NULL) {
- index = noreg_GP;
+ if (idx == NULL) {
+ idx = noreg_GP;
} else {
- index = be_transform_node(index);
+ idx = be_transform_node(idx);
}
if (mode_is_float(mode)) {
if (ia32_cg_config.use_sse2) {
- new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
+ new_node = new_bd_ia32_xLoad(dbgi, block, base, idx, new_mem,
mode);
} else {
- new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
+ new_node = new_bd_ia32_fld(dbgi, block, base, idx, new_mem,
mode);
}
} else {
/* create a conv node with address mode for smaller modes */
if (get_mode_size_bits(mode) < 32) {
- new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, index,
+ new_node = new_bd_ia32_Conv_I2I(dbgi, block, base, idx,
new_mem, noreg_GP, mode);
} else {
- new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
+ new_node = new_bd_ia32_Load(dbgi, block, base, idx, new_mem);
}
}
+ ir_set_throws_exception(new_node, throws_exception);
set_irn_pinned(new_node, get_irn_pinned(node));
set_ia32_op_type(new_node, ia32_AddrModeS);
set_address(new_node, &addr);
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
- arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
+ arch_add_irn_flags(new_node, arch_irn_flags_rematerializable);
}
SET_IA32_ORIG_NODE(new_node, node);
if (use_dest_am(src_block, op1, mem, ptr, op2)) {
build_address(&am, op1, ia32_create_am_double_use);
- new_op = create_immediate_or_transform(op2, 0);
+ new_op = create_immediate_or_transform(op2);
} else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
build_address(&am, op2, ia32_create_am_double_use);
- new_op = create_immediate_or_transform(op1, 0);
+ new_op = create_immediate_or_transform(op1);
} else {
return NULL;
}
be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
mem_proj = be_transform_node(am.mem_proj);
- be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
+ be_set_transformed_node(am.mem_proj, new_node);
+ be_set_transformed_node(mem_proj, new_node);
return new_node;
}
be_set_transformed_node(get_Proj_pred(am.mem_proj), new_node);
mem_proj = be_transform_node(am.mem_proj);
- be_set_transformed_node(mem_proj ? mem_proj : am.mem_proj, new_node);
+ be_set_transformed_node(am.mem_proj, new_node);
+ be_set_transformed_node(mem_proj, new_node);
return new_node;
}
}
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
+ new_bd_ia32_AddMem, new_bd_ia32_AddMem_8bit,
match_commutative | match_immediate);
break;
case iro_Sub:
ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
+ new_bd_ia32_SubMem, new_bd_ia32_SubMem_8bit,
match_immediate);
break;
case iro_And:
op1 = get_And_left(val);
op2 = get_And_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
+ new_bd_ia32_AndMem, new_bd_ia32_AndMem_8bit,
match_commutative | match_immediate);
break;
case iro_Or:
op1 = get_Or_left(val);
op2 = get_Or_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
+ new_bd_ia32_OrMem, new_bd_ia32_OrMem_8bit,
match_commutative | match_immediate);
break;
case iro_Eor:
op1 = get_Eor_left(val);
op2 = get_Eor_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
+ new_bd_ia32_XorMem, new_bd_ia32_XorMem_8bit,
match_commutative | match_immediate);
break;
case iro_Shl:
dbg_info *dbgi = get_irn_dbg_info(node);
int ofs = 0;
int i = 0;
+ int throws_exception = ir_throws_exception(node);
ir_node *ins[4];
ia32_address_t addr;
- assert(size % 4 == 0);
- assert(size <= 16);
-
build_address_ptr(&addr, ptr, mem);
do {
- unsigned val =
- get_tarval_sub_bits(tv, ofs) |
- (get_tarval_sub_bits(tv, ofs + 1) << 8) |
- (get_tarval_sub_bits(tv, ofs + 2) << 16) |
- (get_tarval_sub_bits(tv, ofs + 3) << 24);
- ir_node *imm = ia32_create_Immediate(NULL, 0, val);
+ unsigned val;
+ unsigned delta;
+ ir_mode *mode;
+ if (size >= 4) {
+ val= get_tarval_sub_bits(tv, ofs) |
+ (get_tarval_sub_bits(tv, ofs + 1) << 8) |
+ (get_tarval_sub_bits(tv, ofs + 2) << 16) |
+ (get_tarval_sub_bits(tv, ofs + 3) << 24);
+ delta = 4;
+ mode = mode_Iu;
+ } else if (size >= 2) {
+ val= get_tarval_sub_bits(tv, ofs) |
+ (get_tarval_sub_bits(tv, ofs + 1) << 8);
+ delta = 2;
+ mode = mode_Hu;
+ } else {
+ panic("invalid size of Store float to mem (%+F)", node);
+ }
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const imm = ia32_create_Immediate(irg, NULL, 0, val);
ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, imm);
+ ir_node *new_mem = new_r_Proj(new_node, mode_M, pn_ia32_Store_M);
+ ir_set_throws_exception(new_node, throws_exception);
set_irn_pinned(new_node, get_irn_pinned(node));
set_ia32_op_type(new_node, ia32_AddrModeD);
- set_ia32_ls_mode(new_node, mode_Iu);
+ set_ia32_ls_mode(new_node, mode);
set_address(new_node, &addr);
SET_IA32_ORIG_NODE(new_node, node);
assert(i < 4);
- ins[i++] = new_node;
+ ins[i++] = new_mem;
- size -= 4;
- ofs += 4;
- addr.offset += 4;
+ size -= delta;
+ ofs += delta;
+ addr.offset += delta;
} while (size != 0);
if (i > 1) {
return new_rd_Sync(dbgi, new_block, i, ins);
} else {
- return ins[0];
+ return get_Proj_pred(ins[0]);
}
}
/**
* Generate a vfist or vfisttp instruction.
*/
-static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base, ir_node *index,
- ir_node *mem, ir_node *val, ir_node **fist)
+static ir_node *gen_vfist(dbg_info *dbgi, ir_node *block, ir_node *base,
+ ir_node *index, ir_node *mem, ir_node *val)
{
- ir_node *new_node;
-
if (ia32_cg_config.use_fisttp) {
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
- ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
- ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res);
+ ir_node *vfisttp = new_bd_ia32_fisttp(dbgi, block, base, index, mem, val);
+ ir_node *value = new_r_Proj(vfisttp, ia32_mode_E, pn_ia32_fisttp_res);
be_new_Keep(block, 1, &value);
- new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M);
- *fist = vfisttp;
+ return vfisttp;
} else {
ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
/* do a fist */
- new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
- *fist = new_node;
+ ir_node *vfist = new_bd_ia32_fist(dbgi, block, base, index, mem, val, trunc_mode);
+ return vfist;
}
- return new_node;
}
+
/**
* Transforms a general (no special case) Store.
*
ir_node *ptr = get_Store_ptr(node);
ir_node *mem = get_Store_mem(node);
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_val, *new_node, *store;
+ int throws_exception = ir_throws_exception(node);
+ ir_node *new_val;
+ ir_node *new_node;
ia32_address_t addr;
/* check for destination address mode */
addr.mem = be_transform_node(mem);
if (mode_is_float(mode)) {
- /* Convs (and strict-Convs) before stores are unnecessary if the mode
- is the same. */
- while (is_Conv(val) && mode == get_irn_mode(val)) {
- ir_node *op = get_Conv_op(val);
- if (!mode_is_float(get_irn_mode(op)))
- break;
- val = op;
- }
- new_val = be_transform_node(val);
if (ia32_cg_config.use_sse2) {
+ new_val = be_transform_node(val);
new_node = new_bd_ia32_xStore(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val);
} else {
- new_node = new_bd_ia32_vfst(dbgi, new_block, addr.base,
+ val = ia32_skip_float_downconv(val);
+ new_val = be_transform_node(val);
+ new_node = new_bd_ia32_fst(dbgi, new_block, addr.base,
addr.index, addr.mem, new_val, mode);
}
- store = new_node;
} else if (!ia32_cg_config.use_sse2 && is_float_to_int_conv(val)) {
- val = get_Conv_op(val);
-
- /* TODO: is this optimisation still necessary at all (middleend)? */
- /* We can skip ALL float->float up-Convs (and strict-up-Convs) before stores. */
- while (is_Conv(val)) {
- ir_node *op = get_Conv_op(val);
- if (!mode_is_float(get_irn_mode(op)))
- break;
- if (get_mode_size_bits(get_irn_mode(op)) > get_mode_size_bits(get_irn_mode(val)))
- break;
- val = op;
- }
+ val = get_Conv_op(val);
new_val = be_transform_node(val);
- new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val, &store);
+ new_node = gen_vfist(dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
} else {
- new_val = create_immediate_or_transform(val, 0);
+ unsigned dest_bits = get_mode_size_bits(mode);
+ while (is_downconv(val)
+ && get_mode_size_bits(get_irn_mode(val)) >= dest_bits) {
+ val = get_Conv_op(val);
+ }
+ new_val = create_immediate_or_transform(val);
assert(mode != mode_b);
- if (get_mode_size_bits(mode) == 8) {
- new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- } else {
- new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- }
- store = new_node;
+ new_node = dest_bits == 8
+ ? new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, new_val)
+ : new_bd_ia32_Store (dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
}
+ ir_set_throws_exception(new_node, throws_exception);
- set_irn_pinned(store, get_irn_pinned(node));
- set_ia32_op_type(store, ia32_AddrModeD);
- set_ia32_ls_mode(store, mode);
+ set_irn_pinned(new_node, get_irn_pinned(node));
+ set_ia32_op_type(new_node, ia32_AddrModeD);
+ set_ia32_ls_mode(new_node, mode);
- set_address(store, &addr);
- SET_IA32_ORIG_NODE(store, node);
+ set_address(new_node, &addr);
+ SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
*/
static ir_node *gen_Store(ir_node *node)
{
- ir_node *val = get_Store_value(node);
- ir_mode *mode = get_irn_mode(val);
+ ir_node *val = get_Store_value(node);
+ ir_mode *mode = get_irn_mode(val);
if (mode_is_float(mode) && is_Const(val)) {
/* We can transform every floating const store
*
* @return the created ia32 SwitchJmp node
*/
-static ir_node *create_Switch(ir_node *node)
-{
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *sel = get_Cond_selector(node);
- ir_node *new_sel = be_transform_node(sel);
- long switch_min = LONG_MAX;
- long switch_max = LONG_MIN;
- long default_pn = get_Cond_default_proj(node);
- ir_node *new_node;
- const ir_edge_t *edge;
-
- assert(get_mode_size_bits(get_irn_mode(sel)) == 32);
-
- /* determine the smallest switch case value */
- foreach_out_edge(node, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- long pn = get_Proj_proj(proj);
- if (pn == default_pn)
- continue;
-
- if (pn < switch_min)
- switch_min = pn;
- if (pn > switch_max)
- switch_max = pn;
- }
-
- if ((unsigned long) (switch_max - switch_min) > 128000) {
- panic("Size of switch %+F bigger than 128000", node);
- }
-
- if (switch_min != 0) {
- /* if smallest switch case is not 0 we need an additional sub */
- new_sel = new_bd_ia32_Lea(dbgi, block, new_sel, noreg_GP);
- add_ia32_am_offs_int(new_sel, -switch_min);
- set_ia32_op_type(new_sel, ia32_AddrModeS);
-
- SET_IA32_ORIG_NODE(new_sel, node);
- }
-
- new_node = new_bd_ia32_SwitchJmp(dbgi, block, new_sel, default_pn);
+static ir_node *gen_Switch(ir_node *node)
+{
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_graph *irg = get_irn_irg(node);
+ ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_node *sel = get_Switch_selector(node);
+ ir_node *new_sel = be_transform_node(sel);
+ ir_mode *sel_mode = get_irn_mode(sel);
+ const ir_switch_table *table = get_Switch_table(node);
+ unsigned n_outs = get_Switch_n_outs(node);
+ ir_node *new_node;
+
+ assert(get_mode_size_bits(sel_mode) <= 32);
+ assert(!mode_is_float(sel_mode));
+ sel = ia32_skip_sameconv(sel);
+ if (get_mode_size_bits(sel_mode) < 32)
+ new_sel = transform_upconv(sel, node);
+
+ ir_type *const utype = get_unknown_type();
+ ir_entity *const entity = new_entity(utype, id_unique("TBL%u"), utype);
+ set_entity_visibility(entity, ir_visibility_private);
+ add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
+
+ table = ir_switch_table_duplicate(irg, table);
+
+ new_node = new_bd_ia32_SwitchJmp(dbgi, block, noreg_GP, new_sel, n_outs, table);
+ set_ia32_am_scale(new_node, 2);
+ set_ia32_am_sc(new_node, entity);
+ set_ia32_op_type(new_node, ia32_AddrModeS);
+ set_ia32_ls_mode(new_node, mode_Iu);
SET_IA32_ORIG_NODE(new_node, node);
+ // FIXME This seems wrong. GCC uses PIC for switch on OS X.
+ get_ia32_attr(new_node)->data.am_sc_no_pic_adjust = true;
return new_node;
}
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *sel = get_Cond_selector(node);
- ir_mode *sel_mode = get_irn_mode(sel);
ir_node *flags = NULL;
ir_node *new_node;
ia32_condition_code_t cc;
- if (sel_mode != mode_b) {
- return create_Switch(node);
- }
-
/* we get flags from a Cmp */
flags = get_flags_node(sel, &cc);
ir_node *left = get_Cmp_left(node);
ir_node *new_left = be_transform_node(left);
ir_node *right = get_Cmp_right(node);
+ ir_mode *cmp_mode = get_irn_mode(left);
ir_node *new_right;
ir_node *new_node;
+ check_x87_floatmode(cmp_mode);
if (ia32_cg_config.use_fucomi) {
new_right = be_transform_node(right);
- new_node = new_bd_ia32_vFucomi(dbgi, new_block, new_left,
+ new_node = new_bd_ia32_Fucomi(dbgi, new_block, new_left,
new_right, 0);
set_ia32_commutative(new_node);
SET_IA32_ORIG_NODE(new_node, node);
} else {
- if (ia32_cg_config.use_ftst && is_Const_0(right)) {
- new_node = new_bd_ia32_vFtstFnstsw(dbgi, new_block, new_left, 0);
+ if (is_Const_0(right)) {
+ new_node = new_bd_ia32_FtstFnstsw(dbgi, new_block, new_left, 0);
} else {
new_right = be_transform_node(right);
- new_node = new_bd_ia32_vFucomFnstsw(dbgi, new_block, new_left, new_right, 0);
+ new_node = new_bd_ia32_FucomFnstsw(dbgi, new_block, new_left, new_right, 0);
+ set_ia32_commutative(new_node);
}
- set_ia32_commutative(new_node);
-
SET_IA32_ORIG_NODE(new_node, node);
new_node = new_bd_ia32_Sahf(dbgi, new_block, new_node);
return new_node;
}
-/**
- * returns true if it is assured, that the upper bits of a node are "clean"
- * which means for a 16 or 8 bit value, that the upper bits in the register
- * are 0 for unsigned and a copy of the last significant bit for signed
- * numbers.
- */
-static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
+static bool ia32_mux_upper_bits_clean(const ir_node *node, ir_mode *mode)
{
- assert(ia32_mode_needs_gp_reg(mode));
- if (get_mode_size_bits(mode) >= 32)
- return true;
-
- if (is_Proj(transformed_node))
- return upper_bits_clean(get_Proj_pred(transformed_node), mode);
-
- switch (get_ia32_irn_opcode(transformed_node)) {
- case iro_ia32_Conv_I2I:
- case iro_ia32_Conv_I2I8Bit: {
- ir_mode *smaller_mode = get_ia32_ls_mode(transformed_node);
- if (mode_is_signed(smaller_mode) != mode_is_signed(mode))
- return false;
- if (get_mode_size_bits(smaller_mode) > get_mode_size_bits(mode))
- return false;
-
- return true;
- }
-
- case iro_ia32_Shr:
- if (mode_is_signed(mode)) {
- return false; /* TODO handle signed modes */
- } else {
- ir_node *right = get_irn_n(transformed_node, n_ia32_Shr_count);
- if (is_ia32_Immediate(right) || is_ia32_Const(right)) {
- const ia32_immediate_attr_t *attr
- = get_ia32_immediate_attr_const(right);
- if (attr->symconst == 0 &&
- (unsigned)attr->offset >= 32 - get_mode_size_bits(mode)) {
- return true;
- }
- }
- return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Shr_val), mode);
- }
-
- case iro_ia32_Sar:
- /* TODO too conservative if shift amount is constant */
- return upper_bits_clean(get_irn_n(transformed_node, n_ia32_Sar_val), mode);
-
- case iro_ia32_And:
- if (!mode_is_signed(mode)) {
- return
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_right), mode) ||
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_And_left), mode);
- }
- /* TODO if one is known to be zero extended, then || is sufficient */
- /* FALLTHROUGH */
- case iro_ia32_Or:
- case iro_ia32_Xor:
- return
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_right), mode) &&
- upper_bits_clean(get_irn_n(transformed_node, n_ia32_binary_left), mode);
-
- case iro_ia32_Const:
- case iro_ia32_Immediate: {
- const ia32_immediate_attr_t *attr =
- get_ia32_immediate_attr_const(transformed_node);
- if (mode_is_signed(mode)) {
- long shifted = attr->offset >> (get_mode_size_bits(mode) - 1);
- return shifted == 0 || shifted == -1;
- } else {
- unsigned long shifted = (unsigned long)attr->offset;
- shifted >>= get_mode_size_bits(mode);
- return shifted == 0;
- }
- }
-
- default:
- return false;
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
+ ir_mode *mux_mode = get_irn_mode(node);
+ /* mux nodes which get transformed to the set instruction are not clean */
+ if (is_Const(mux_true) && is_Const(mux_false)
+ && get_mode_size_bits(mux_mode) == 8) {
+ return false;
}
+ return be_upper_bits_clean(mux_true, mode)
+ && be_upper_bits_clean(mux_false, mode);
}
/**
assert(get_irn_mode(and_left) == cmp_mode);
match_arguments(&am, block, and_left, and_right, NULL,
- match_commutative |
- match_am | match_8bit_am | match_16bit_am |
- match_am_and_immediates | match_immediate);
+ match_commutative |
+ match_am | match_8bit_am | match_16bit_am |
+ match_am_and_immediates | match_immediate);
/* use 32bit compare mode if possible since the opcode is smaller */
- if (upper_bits_clean(am.new_op1, cmp_mode) &&
- upper_bits_clean(am.new_op2, cmp_mode)) {
+ if (am.op_type == ia32_Normal &&
+ be_upper_bits_clean(and_left, cmp_mode) &&
+ be_upper_bits_clean(and_right, cmp_mode)) {
cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
}
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
- } else {
- new_node = new_bd_ia32_Test(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
- }
+ new_node = get_mode_size_bits(cmp_mode) == 8
+ ? new_bd_ia32_Test_8bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted)
+ : new_bd_ia32_Test (dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
} else {
/* Cmp(left, right) */
match_arguments(&am, block, left, right, NULL,
- match_commutative | match_am | match_8bit_am |
- match_16bit_am | match_am_and_immediates |
- match_immediate);
+ match_commutative |
+ match_am | match_8bit_am | match_16bit_am |
+ match_am_and_immediates | match_immediate);
/* use 32bit compare mode if possible since the opcode is smaller */
- if (upper_bits_clean(am.new_op1, cmp_mode) &&
- upper_bits_clean(am.new_op2, cmp_mode)) {
+ if (am.op_type == ia32_Normal &&
+ be_upper_bits_clean(left, cmp_mode) &&
+ be_upper_bits_clean(right, cmp_mode)) {
cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
}
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted);
- } else {
- new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
- }
+ new_node = get_mode_size_bits(cmp_mode) == 8
+ ? new_bd_ia32_Cmp_8bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted)
+ : new_bd_ia32_Cmp (dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
}
set_am_attributes(new_node, &am);
set_ia32_ls_mode(new_node, cmp_mode);
/* we might need to conv the result up */
if (get_mode_size_bits(mode) > 8) {
- new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_node, mode_Bu);
+ new_node = new_bd_ia32_Conv_I2I_8bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, orig_node);
}
dbgi = get_irn_dbg_info(psi);
sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
+ set_ia32_ls_mode(sbb, mode_Iu);
notn = new_bd_ia32_Not(dbgi, block, sbb);
new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
+ set_ia32_ls_mode(new_node, mode_Iu);
set_ia32_commutative(new_node);
return new_node;
}
}
- tp = ia32_create_float_type(mode, 4);
+ tp = ia32_get_prim_type(mode);
tp = ia32_create_float_array(tp);
ent = new_entity(get_glob_type(), id_unique("C%u"), tp);
SETCC_TR_NOT,
SETCC_TR_AND,
SETCC_TR_SET,
- SETCC_TR_SBB,
};
typedef struct setcc_transform {
++step;
res->steps[step].transform = SETCC_TR_NEG;
} else {
- int v = get_tarval_lowest_bit(t);
- assert(v >= 0);
+ int val = get_tarval_lowest_bit(t);
+ assert(val >= 0);
res->steps[step].transform = SETCC_TR_SHL;
- res->steps[step].scale = v;
+ res->steps[step].scale = val;
}
}
++step;
assert(get_irn_mode(sel) == mode_b);
- is_abs = be_mux_is_abs(sel, mux_true, mux_false);
+ is_abs = ir_mux_is_abs(sel, mux_false, mux_true);
if (is_abs != 0) {
- return create_abs(dbgi, block, be_get_abs_op(sel), is_abs < 0, node);
+ if (ia32_mode_needs_gp_reg(mode)) {
+ ir_fprintf(stderr, "Optimisation warning: Integer abs %+F not transformed\n",
+ node);
+ } else {
+ ir_node *op = ir_get_abs_op(sel, mux_false, mux_true);
+ return create_float_abs(dbgi, block, op, is_abs < 0, node);
+ }
}
/* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
am.addr.symconst_ent = ia32_create_const_array(mux_false, mux_true, &new_mode);
- switch (get_mode_size_bytes(new_mode)) {
- case 4:
+ if (new_mode == mode_F) {
scale = 2;
- break;
- case 8:
+ } else if (new_mode == mode_D) {
scale = 3;
- break;
- case 10:
- /* use 2 * 5 */
- scale = 1;
- new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
- set_ia32_am_scale(new_node, 2);
- break;
- case 12:
- /* use 4 * 3 */
- scale = 2;
- new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
- set_ia32_am_scale(new_node, 1);
- break;
- case 16:
+ } else if (new_mode == ia32_mode_E) {
/* arg, shift 16 NOT supported */
scale = 3;
new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
- break;
- default:
+ } else {
panic("Unsupported constant size");
}
am.addr.offset = 0;
am.addr.scale = scale;
am.addr.use_frame = 0;
+ am.addr.tls_segment = false;
am.addr.frame_entity = NULL;
am.addr.symconst_sign = 0;
am.mem_proj = am.addr.mem;
if (ia32_cg_config.use_sse2)
load = new_bd_ia32_xLoad(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
else
- load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
+ load = new_bd_ia32_fld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
set_am_attributes(load, &am);
- return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
+ return new_rd_Proj(NULL, load, mode_fp, pn_ia32_res);
}
panic("cannot transform floating point Mux");
case SETCC_TR_SET:
new_node = create_set_32bit(dbgi, new_block, flags, res.cc, node);
break;
- case SETCC_TR_SBB:
- new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
- break;
default:
panic("unknown setcc transform");
}
}
}
-
/**
* Create a conversion from x87 state register to general purpose.
*/
ir_graph *irg = current_ir_graph;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_irn_mode(node);
+ ir_node *frame = get_irg_frame(irg);
ir_node *fist, *load, *mem;
- mem = gen_vfist(dbgi, block, get_irg_frame(irg), noreg_GP, nomem, new_op, &fist);
+ fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_op);
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
+ arch_add_irn_flags(fist, arch_irn_flags_spill);
+
+ assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
+ mem = new_r_Proj(fist, mode_M, pn_ia32_fist_M);
assert(get_mode_size_bits(mode) <= 32);
/* exception we can only store signed 32 bit integers, so for unsigned
}
/**
- * Creates a x87 strict Conv by placing a Store and a Load
+ * Creates a x87 Conv by placing a Store and a Load
*/
-static ir_node *gen_x87_strict_conv(ir_mode *tgt_mode, ir_node *node)
+static ir_node *gen_x87_conv(ir_mode *tgt_mode, ir_node *node)
{
ir_node *block = get_nodes_block(node);
ir_graph *irg = get_Block_irg(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *frame = get_irg_frame(irg);
+ ir_node *store_mem;
ir_node *store, *load;
ir_node *new_node;
- store = new_bd_ia32_vfst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
+ store = new_bd_ia32_fst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
+ arch_add_irn_flags(store, arch_irn_flags_spill);
SET_IA32_ORIG_NODE(store, node);
- load = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, store, tgt_mode);
+ store_mem = new_r_Proj(store, mode_M, pn_ia32_fst_M);
+
+ load = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, tgt_mode);
set_ia32_use_frame(load);
set_ia32_op_type(load, ia32_AddrModeS);
SET_IA32_ORIG_NODE(load, node);
- new_node = new_r_Proj(load, mode_E, pn_ia32_vfld_res);
+ new_node = new_r_Proj(load, ia32_mode_E, pn_ia32_fld_res);
return new_node;
}
ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
func = get_mode_size_bits(mode) == 8 ?
- new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
+ new_bd_ia32_Conv_I2I_8bit : new_bd_ia32_Conv_I2I;
return func(dbgi, block, base, index, mem, val, mode);
}
ir_mode *store_mode;
ir_node *fild;
ir_node *store;
+ ir_node *store_mem;
ir_node *new_node;
/* fild can use source AM if the operand is a signed 16bit or 32bit integer */
if (possible_int_mode_for_fp(src_mode)) {
ia32_address_mode_t am;
- match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am);
+ match_arguments(&am, src_block, NULL, op, NULL, match_am | match_try_am | match_16bit_am | match_upconv);
if (am.op_type == ia32_AddrModeS) {
ia32_address_t *addr = &am.addr;
- fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
- new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ fild = new_bd_ia32_fild(dbgi, block, addr->base, addr->index, addr->mem);
+ new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
set_am_attributes(fild, &am);
SET_IA32_ORIG_NODE(fild, node);
/* first convert to 32 bit signed if necessary */
if (get_mode_size_bits(src_mode) < 32) {
- if (!upper_bits_clean(new_op, src_mode)) {
+ if (!be_upper_bits_clean(op, src_mode)) {
new_op = create_Conv_I2I(dbgi, block, noreg_GP, noreg_GP, nomem, new_op, src_mode);
SET_IA32_ORIG_NODE(new_op, node);
}
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Iu);
+ arch_add_irn_flags(store, arch_irn_flags_spill);
+
+ store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
/* exception for 32bit unsigned, do a 64bit spill+load */
if (!mode_is_signed(mode)) {
ir_node *in[2];
/* store a zero */
- ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
+ ir_node *zero_const = ia32_create_Immediate(irg, NULL, 0, 0);
ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
noreg_GP, nomem, zero_const);
+ ir_node *zero_store_mem = new_r_Proj(zero_store, mode_M, pn_ia32_Store_M);
set_ia32_use_frame(zero_store);
set_ia32_op_type(zero_store, ia32_AddrModeD);
add_ia32_am_offs_int(zero_store, 4);
set_ia32_ls_mode(zero_store, mode_Iu);
+ arch_add_irn_flags(zero_store, arch_irn_flags_spill);
- in[0] = zero_store;
- in[1] = store;
+ in[0] = zero_store_mem;
+ in[1] = store_mem;
- store = new_rd_Sync(dbgi, block, 2, in);
+ store_mem = new_rd_Sync(dbgi, block, 2, in);
store_mode = mode_Ls;
} else {
store_mode = mode_Is;
}
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, get_irg_frame(irg), noreg_GP, store);
+ fild = new_bd_ia32_fild(dbgi, block, get_irg_frame(irg), noreg_GP, store_mem);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_ls_mode(fild, store_mode);
- new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ new_node = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
return new_node;
}
{
ir_node *new_block = be_transform_node(block);
ir_node *new_node;
- ir_mode *smaller_mode;
ia32_address_mode_t am;
ia32_address_t *addr = &am.addr;
(void) node;
- if (get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode)) {
- smaller_mode = src_mode;
- } else {
- smaller_mode = tgt_mode;
- }
+ assert(get_mode_size_bits(src_mode) < get_mode_size_bits(tgt_mode));
#ifdef DEBUG_libfirm
if (is_Const(op)) {
}
#endif
+ if (be_upper_bits_clean(op, src_mode)) {
+ return be_transform_node(op);
+ }
+
match_arguments(&am, block, NULL, op, NULL,
match_am | match_8bit_am | match_16bit_am);
- if (upper_bits_clean(am.new_op2, smaller_mode)) {
- /* unnecessary conv. in theory it shouldn't have been AM */
- assert(is_ia32_NoReg_GP(addr->base));
- assert(is_ia32_NoReg_GP(addr->index));
- assert(is_NoMem(addr->mem));
- assert(am.addr.offset == 0);
- assert(am.addr.symconst_ent == NULL);
- return am.new_op2;
- }
-
new_node = create_Conv_I2I(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op2, smaller_mode);
+ addr->mem, am.new_op2, src_mode);
set_am_attributes(new_node, &am);
/* match_arguments assume that out-mode = in-mode, this isn't true here
* so fix it */
- set_ia32_ls_mode(new_node, smaller_mode);
+ set_ia32_ls_mode(new_node, src_mode);
SET_IA32_ORIG_NODE(new_node, node);
new_node = fix_mem_proj(new_node, &am);
return new_node;
}
if (src_mode == tgt_mode) {
- if (get_Conv_strict(node)) {
- if (ia32_cg_config.use_sse2) {
- /* when we are in SSE mode, we can kill all strict no-op conversion */
- return be_transform_node(op);
- }
- } else {
- /* this should be optimized already, but who knows... */
- DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node));
+ /* this should be optimized already, but who knows... */
+ DEBUG_ONLY(ir_fprintf(stderr, "Debug warning: conv %+F is pointless\n", node);)
DB((dbg, LEVEL_1, "killed Conv(mode, mode) ..."));
- return be_transform_node(op);
- }
+ return be_transform_node(op);
}
if (mode_is_float(src_mode)) {
nomem, new_op);
set_ia32_ls_mode(res, tgt_mode);
} else {
- if (get_Conv_strict(node)) {
- /* if fp_no_float_fold is not set then we assume that we
- * don't have any float operations in a non
- * mode_float_arithmetic mode and can skip strict upconvs */
- if (src_bits < tgt_bits) {
- DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
- return new_op;
- } else {
- res = gen_x87_strict_conv(tgt_mode, new_op);
- SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
- return res;
- }
+ if (src_bits < tgt_bits) {
+ DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
+ return new_op;
+ } else {
+ res = gen_x87_conv(tgt_mode, new_op);
+ SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
+ return res;
}
- DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
- return new_op;
}
} else {
/* ... to int */
set_ia32_ls_mode(res, tgt_mode);
} else {
unsigned int_mantissa = get_mode_size_bits(src_mode) - (mode_is_signed(src_mode) ? 1 : 0);
- unsigned float_mantissa = tarval_ieee754_get_mantissa_size(tgt_mode);
+ unsigned float_mantissa = get_mode_mantissa_size(tgt_mode);
res = gen_x87_gp_to_fp(node, src_mode);
- /* we need a strict-Conv, if the int mode has more bits than the
+ /* we need a float-conv, if the int mode has more bits than the
* float mantissa */
if (float_mantissa < int_mantissa) {
- res = gen_x87_strict_conv(tgt_mode, res);
+ res = gen_x87_conv(tgt_mode, res);
SET_IA32_ORIG_NODE(get_Proj_pred(res), node);
}
return res;
return be_transform_node(op);
} else {
/* to int */
- if (src_bits == tgt_bits) {
+ if (src_bits >= tgt_bits) {
DB((dbg, LEVEL_1, "omitting unnecessary Conv(%+F, %+F) ...",
src_mode, tgt_mode));
return be_transform_node(op);
return res;
}
-static ir_node *create_immediate_or_transform(ir_node *node,
- char immediate_constraint_type)
+static ir_node *create_immediate_or_transform(ir_node *const node)
{
- ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
+ ir_node *new_node = ia32_try_create_Immediate(node, 'i');
if (new_node == NULL) {
new_node = be_transform_node(node);
}
*/
static ir_node *gen_be_Return(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
- ir_node *ret_val = get_irn_n(node, be_pos_Return_val);
- ir_node *ret_mem = get_irn_n(node, be_pos_Return_mem);
+ ir_node *ret_val = get_irn_n(node, n_be_Return_val);
+ ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
ir_node *new_ret_val = be_transform_node(ret_val);
ir_node *new_ret_mem = be_transform_node(ret_mem);
- ir_entity *ent = get_irg_entity(irg);
- ir_type *tp = get_entity_type(ent);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_graph *irg = get_Block_irg(block);
+ ir_entity *ent = get_irg_entity(irg);
+ ir_type *tp = get_entity_type(ent);
ir_type *res_type;
ir_mode *mode;
- ir_node *frame, *sse_store, *fld, *mproj;
+ ir_node *frame;
+ ir_node *sse_store;
+ ir_node *store_mem;
+ ir_node *fld;
+ ir_node *mproj;
int i;
int arity;
unsigned pop;
ir_node **in;
- ir_node *new_node;
assert(ret_val != NULL);
if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
+ arch_add_irn_flags(sse_store, arch_irn_flags_spill);
+ store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
/* load into x87 register */
- fld = new_bd_ia32_vfld(dbgi, block, frame, noreg_GP, sse_store, mode);
+ fld = new_bd_ia32_fld(dbgi, block, frame, noreg_GP, store_mem, mode);
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
- mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
- fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
+ mproj = new_r_Proj(fld, mode_M, pn_ia32_fld_M);
+ fld = new_r_Proj(fld, mode_fp, pn_ia32_fld_res);
/* create a new return */
arity = get_irn_arity(node);
in[i] = be_transform_node(op);
}
}
- new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
+ ir_node *const new_node = be_new_Return(dbgi, block, arity, pop, arity, in);
copy_node_attr(irg, node, new_node);
return new_node;
*/
static ir_node *gen_be_AddSP(ir_node *node)
{
- ir_node *sz = get_irn_n(node, be_pos_AddSP_size);
- ir_node *sp = get_irn_n(node, be_pos_AddSP_old_sp);
+ ir_node *sz = get_irn_n(node, n_be_AddSP_size);
+ ir_node *sp = get_irn_n(node, n_be_AddSP_old_sp);
ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_SubSP,
match_am | match_immediate);
assert(is_ia32_SubSP(new_node));
- arch_irn_set_register(new_node, pn_ia32_SubSP_stack,
- &ia32_registers[REG_ESP]);
+ arch_set_irn_register_out(new_node, pn_ia32_SubSP_stack,
+ &ia32_registers[REG_ESP]);
return new_node;
}
*/
static ir_node *gen_be_SubSP(ir_node *node)
{
- ir_node *sz = get_irn_n(node, be_pos_SubSP_size);
- ir_node *sp = get_irn_n(node, be_pos_SubSP_old_sp);
+ ir_node *sz = get_irn_n(node, n_be_SubSP_size);
+ ir_node *sp = get_irn_n(node, n_be_SubSP_old_sp);
ir_node *new_node = gen_binop(node, sp, sz, new_bd_ia32_AddSP,
match_am | match_immediate);
assert(is_ia32_AddSP(new_node));
- arch_irn_set_register(new_node, pn_ia32_AddSP_stack,
- &ia32_registers[REG_ESP]);
+ arch_set_irn_register_out(new_node, pn_ia32_AddSP_stack,
+ &ia32_registers[REG_ESP]);
return new_node;
}
-/**
- * Change some phi modes
- */
static ir_node *gen_Phi(ir_node *node)
{
+ ir_mode *mode = get_irn_mode(node);
const arch_register_req_t *req;
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_graph *irg = current_ir_graph;
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *phi;
-
if (ia32_mode_needs_gp_reg(mode)) {
/* we shouldn't have any 64bit stuff around anymore */
assert(get_mode_size_bits(mode) <= 32);
mode = mode_xmm;
req = ia32_reg_classes[CLASS_ia32_xmm].class_req;
} else {
- mode = mode_vfp;
- req = ia32_reg_classes[CLASS_ia32_vfp].class_req;
+ mode = mode_fp;
+ req = ia32_reg_classes[CLASS_ia32_fp].class_req;
}
} else {
req = arch_no_register_req;
}
- /* phi nodes allow loops, so we use the old arguments for now
- * and fix this later */
- phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
- get_irn_in(node) + 1);
- copy_node_attr(irg, node, phi);
- be_duplicate_deps(node, phi);
-
- arch_set_out_register_req(phi, 0, req);
-
- be_enqueue_preds(node);
-
- return phi;
+ return be_transform_phi(node, req);
}
static ir_node *gen_Jmp(ir_node *node)
assert(get_irn_mode(op) == mode_P);
- match_arguments(&am, block, NULL, op, NULL, match_am | match_immediate);
+ match_arguments(&am, block, NULL, op, NULL,
+ match_am | match_immediate | match_upconv);
new_node = new_bd_ia32_IJmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op2);
+ addr->mem, am.new_op2);
set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
-static ir_node *gen_ia32_l_ShlDep(ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_l_ShlDep_val);
- ir_node *right = get_irn_n(node, n_ia32_l_ShlDep_count);
-
- return gen_shift_binop(node, left, right, new_bd_ia32_Shl,
- match_immediate | match_mode_neutral);
-}
-
-static ir_node *gen_ia32_l_ShrDep(ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_l_ShrDep_val);
- ir_node *right = get_irn_n(node, n_ia32_l_ShrDep_count);
- return gen_shift_binop(node, left, right, new_bd_ia32_Shr,
- match_immediate);
-}
-
-static ir_node *gen_ia32_l_SarDep(ir_node *node)
-{
- ir_node *left = get_irn_n(node, n_ia32_l_SarDep_val);
- ir_node *right = get_irn_n(node, n_ia32_l_SarDep_count);
- return gen_shift_binop(node, left, right, new_bd_ia32_Sar,
- match_immediate);
-}
-
static ir_node *gen_ia32_l_Add(ir_node *node)
{
ir_node *left = get_irn_n(node, n_ia32_l_Add_left);
match_am | match_immediate | match_mode_neutral);
}
-/**
- * Transforms a l_ShlD/l_ShrD into a ShlD/ShrD. Those nodes have 3 data inputs:
- * op1 - target to be shifted
- * op2 - contains bits to be shifted into target
- * op3 - shift count
- * Only op3 can be an immediate.
- */
-static ir_node *gen_lowered_64bit_shifts(ir_node *node, ir_node *high,
- ir_node *low, ir_node *count)
-{
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *new_high = be_transform_node(high);
- ir_node *new_low = be_transform_node(low);
- ir_node *new_count;
- ir_node *new_node;
-
- /* the shift amount can be any mode that is bigger than 5 bits, since all
- * other bits are ignored anyway */
- while (is_Conv(count) &&
- get_irn_n_edges(count) == 1 &&
- mode_is_int(get_irn_mode(count))) {
- assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
- count = get_Conv_op(count);
- }
- new_count = create_immediate_or_transform(count, 0);
-
- if (is_ia32_l_ShlD(node)) {
- new_node = new_bd_ia32_ShlD(dbgi, new_block, new_high, new_low,
- new_count);
- } else {
- new_node = new_bd_ia32_ShrD(dbgi, new_block, new_high, new_low,
- new_count);
- }
- SET_IA32_ORIG_NODE(new_node, node);
-
- return new_node;
-}
-
-static ir_node *gen_ia32_l_ShlD(ir_node *node)
-{
- ir_node *high = get_irn_n(node, n_ia32_l_ShlD_val_high);
- ir_node *low = get_irn_n(node, n_ia32_l_ShlD_val_low);
- ir_node *count = get_irn_n(node, n_ia32_l_ShlD_count);
- return gen_lowered_64bit_shifts(node, high, low, count);
-}
-
-static ir_node *gen_ia32_l_ShrD(ir_node *node)
-{
- ir_node *high = get_irn_n(node, n_ia32_l_ShrD_val_high);
- ir_node *low = get_irn_n(node, n_ia32_l_ShrD_val_low);
- ir_node *count = get_irn_n(node, n_ia32_l_ShrD_count);
- return gen_lowered_64bit_shifts(node, high, low, count);
-}
-
static ir_node *gen_ia32_l_LLtoFloat(ir_node *node)
{
ir_node *src_block = get_nodes_block(node);
ir_node *block = be_transform_node(src_block);
- ir_graph *irg = current_ir_graph;
+ ir_graph *irg = get_Block_irg(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *frame = get_irg_frame(irg);
ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
ir_node *new_val_high = be_transform_node(val_high);
ir_node *in[2];
ir_node *sync, *fild, *res;
- ir_node *store_low, *store_high;
+ ir_node *store_low;
+ ir_node *store_high;
+ ir_node *mem_low;
+ ir_node *mem_high;
if (ia32_cg_config.use_sse2) {
- panic("ia32_l_LLtoFloat not implemented for SSE2");
+ panic("not implemented for SSE2");
}
/* do a store */
SET_IA32_ORIG_NODE(store_low, node);
SET_IA32_ORIG_NODE(store_high, node);
+ mem_low = new_r_Proj(store_low, mode_M, pn_ia32_Store_M);
+ mem_high = new_r_Proj(store_high, mode_M, pn_ia32_Store_M);
+
set_ia32_use_frame(store_low);
set_ia32_use_frame(store_high);
set_ia32_op_type(store_low, ia32_AddrModeD);
set_ia32_op_type(store_high, ia32_AddrModeD);
set_ia32_ls_mode(store_low, mode_Iu);
set_ia32_ls_mode(store_high, mode_Is);
+ arch_add_irn_flags(store_low, arch_irn_flags_spill);
+ arch_add_irn_flags(store_high, arch_irn_flags_spill);
add_ia32_am_offs_int(store_high, 4);
- in[0] = store_low;
- in[1] = store_high;
+ in[0] = mem_low;
+ in[1] = mem_high;
sync = new_rd_Sync(dbgi, block, 2, in);
/* do a fild */
- fild = new_bd_ia32_vfild(dbgi, block, frame, noreg_GP, sync);
+ fild = new_bd_ia32_fild(dbgi, block, frame, noreg_GP, sync);
set_ia32_use_frame(fild);
set_ia32_op_type(fild, ia32_AddrModeS);
SET_IA32_ORIG_NODE(fild, node);
- res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
+ res = new_r_Proj(fild, mode_fp, pn_ia32_fild_res);
if (! mode_is_signed(get_irn_mode(val_high))) {
ia32_address_mode_t am;
- ir_node *count = ia32_create_Immediate(NULL, 0, 31);
+ ir_node *count = ia32_create_Immediate(irg, NULL, 0, 31);
ir_node *fadd;
am.addr.base = get_symconst_base();
am.addr.offset = 0;
am.addr.scale = 2;
am.addr.symconst_ent = ia32_gen_fp_known_const(ia32_ULLBIAS);
+ am.addr.tls_segment = false;
am.addr.use_frame = 0;
am.addr.frame_entity = NULL;
am.addr.symconst_sign = 0;
am.mem_proj = nomem;
am.op_type = ia32_AddrModeS;
am.new_op1 = res;
- am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
+ am.new_op2 = ia32_new_NoReg_fp(irg);
am.pinned = op_pin_state_floats;
am.commutative = 1;
am.ins_permuted = false;
- fadd = new_bd_ia32_vfadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
+ fadd = new_bd_ia32_fadd(dbgi, block, am.addr.base, am.addr.index, am.addr.mem,
am.new_op1, am.new_op2, get_fpcw());
set_am_attributes(fadd, &am);
set_irn_mode(fadd, mode_T);
- res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
+ res = new_rd_Proj(NULL, fadd, mode_fp, pn_ia32_res);
}
return res;
}
ir_node *frame = get_irg_frame(irg);
ir_node *val = get_irn_n(node, n_ia32_l_FloattoLL_val);
ir_node *new_val = be_transform_node(val);
- ir_node *fist, *mem;
+ ir_node *fist;
- mem = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val, &fist);
+ fist = gen_vfist(dbgi, block, frame, noreg_GP, nomem, new_val);
SET_IA32_ORIG_NODE(fist, node);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
+ arch_add_irn_flags(fist, arch_irn_flags_spill);
- return mem;
+ assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
+ return new_r_Proj(fist, mode_M, pn_ia32_fist_M);
}
static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
static ir_node *gen_Proj_Load(ir_node *node)
{
ir_node *new_pred;
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *pred = get_Proj_pred(node);
- dbg_info *dbgi = get_irn_dbg_info(node);
- long proj = get_Proj_proj(node);
+ ir_node *pred = get_Proj_pred(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long proj = get_Proj_proj(node);
/* loads might be part of source address mode matches, so we don't
* transform the ProjMs yet (with the exception of loads whose result is
/* renumber the proj */
new_pred = be_transform_node(pred);
if (is_ia32_Load(new_pred)) {
- switch (proj) {
+ switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
- case pn_Load_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
}
- } else if (is_ia32_Conv_I2I(new_pred) ||
- is_ia32_Conv_I2I8Bit(new_pred)) {
+ } else if (is_ia32_Conv_I2I(new_pred)) {
set_irn_mode(new_pred, mode_T);
- if (proj == pn_Load_res) {
+ switch ((pn_Load)proj) {
+ case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
- } else if (proj == pn_Load_M) {
+ case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
+ case pn_Load_X_except:
+ /* This Load might raise an exception. Mark it. */
+ set_ia32_exc_label(new_pred, 1);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Conv_I2I_X_regular);
}
} else if (is_ia32_xLoad(new_pred)) {
- switch (proj) {
+ switch ((pn_Load)proj) {
case pn_Load_res:
return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
case pn_Load_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
- case pn_Load_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_regular);
}
- } else if (is_ia32_vfld(new_pred)) {
- switch (proj) {
+ } else if (is_ia32_fld(new_pred)) {
+ switch ((pn_Load)proj) {
case pn_Load_res:
- return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
+ return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fld_res);
case pn_Load_M:
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
- case pn_Load_X_regular:
- return new_rd_Jmp(dbgi, block);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fld_M);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_except);
+ case pn_Load_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fld_X_regular);
}
} else {
/* can happen for ProJMs when source address mode happened for the
return new_rd_Proj(dbgi, new_pred, mode_M, 1);
}
- panic("No idea how to transform proj");
+ panic("No idea how to transform Proj(Load) %+F", node);
+}
+
+static ir_node *gen_Proj_Store(ir_node *node)
+{
+ ir_node *pred = get_Proj_pred(node);
+ ir_node *new_pred = be_transform_node(pred);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ long pn = get_Proj_proj(node);
+
+ if (is_ia32_Store(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Store_X_regular);
+ }
+ } else if (is_ia32_fist(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fist_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fist_X_regular);
+ }
+ } else if (is_ia32_fisttp(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fisttp_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fisttp_X_regular);
+ }
+ } else if (is_ia32_fst(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fst_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_fst_X_regular);
+ }
+ } else if (is_ia32_xStore(new_pred)) {
+ switch ((pn_Store)pn) {
+ case pn_Store_M:
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xStore_M);
+ case pn_Store_X_except:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_except);
+ case pn_Store_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xStore_X_regular);
+ }
+ } else if (is_Sync(new_pred)) {
+ /* hack for the case that gen_float_const_Store produced a Sync */
+ if (pn == pn_Store_M) {
+ return new_pred;
+ }
+ panic("exception control flow not implemented yet");
+ } else if (get_ia32_op_type(new_pred) == ia32_AddrModeD) {
+ /* destination address mode */
+ if (pn == pn_Store_M) {
+ return new_pred;
+ }
+ panic("exception control flow for destination AM not implemented yet");
+ }
+
+ panic("No idea how to transform Proj(Store) %+F", node);
}
/**
*/
static ir_node *gen_Proj_Div(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
- long proj = get_Proj_proj(node);
+ long proj = get_Proj_proj(node);
- assert(pn_ia32_Div_M == pn_ia32_IDiv_M);
- assert(pn_ia32_Div_div_res == pn_ia32_IDiv_div_res);
+ assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
+ assert((long)pn_ia32_Div_div_res == (long)pn_ia32_IDiv_div_res);
- switch (proj) {
+ switch ((pn_Div)proj) {
case pn_Div_M:
if (is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
} else if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
- } else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
+ } else if (is_ia32_fdiv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_fdiv_M);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
} else if (is_ia32_xDiv(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
- } else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ } else if (is_ia32_fdiv(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_fp, pn_ia32_fdiv_res);
} else {
panic("Div transformed to unexpected thing %+F", new_pred);
}
- case pn_Div_X_regular:
- return new_rd_Jmp(dbgi, block);
case pn_Div_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
+ case pn_Div_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
}
panic("No idea how to transform proj->Div");
long proj = get_Proj_proj(node);
assert(is_ia32_Div(new_pred) || is_ia32_IDiv(new_pred));
- assert(pn_ia32_Div_M == pn_ia32_IDiv_M);
- assert(pn_ia32_Div_mod_res == pn_ia32_IDiv_mod_res);
+ assert((long)pn_ia32_Div_M == (long)pn_ia32_IDiv_M);
+ assert((long)pn_ia32_Div_mod_res == (long)pn_ia32_IDiv_mod_res);
- switch (proj) {
+ switch ((pn_Mod)proj) {
case pn_Mod_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
case pn_Mod_res:
return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
case pn_Mod_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
- default:
- break;
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_except);
+ case pn_Mod_X_regular:
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_regular);
}
panic("No idea how to transform proj->Mod");
}
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
- switch (proj) {
+ switch ((pn_CopyB)proj) {
case pn_CopyB_M:
if (is_ia32_CopyB_i(new_pred)) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
}
break;
- default:
+ case pn_CopyB_X_regular:
+ if (is_ia32_CopyB_i(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_regular);
+ } else if (is_ia32_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_regular);
+ }
+ break;
+ case pn_CopyB_X_except:
+ if (is_ia32_CopyB_i(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_i_X_except);
+ } else if (is_ia32_CopyB(new_pred)) {
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_CopyB_X_except);
+ }
break;
}
dbg_info *const dbgi = get_irn_dbg_info(node);
ir_node *const src_block = get_nodes_block(node);
ir_node *const block = be_transform_node(src_block);
- ir_node *const src_mem = get_irn_n(node, be_pos_Call_mem);
- ir_node *const src_sp = get_irn_n(node, be_pos_Call_sp);
+ ir_node *const src_mem = get_irn_n(node, n_be_Call_mem);
+ ir_node *const src_sp = get_irn_n(node, n_be_Call_sp);
ir_node *const sp = be_transform_node(src_sp);
- ir_node *const src_ptr = get_irn_n(node, be_pos_Call_ptr);
+ ir_node *const src_ptr = get_irn_n(node, n_be_Call_ptr);
ia32_address_mode_t am;
ia32_address_t *const addr = &am.addr;
ir_node * mem;
unsigned const pop = be_Call_get_pop(node);
ir_type *const call_tp = be_Call_get_type(node);
int old_no_pic_adjust;
+ int throws_exception = ir_throws_exception(node);
/* Run the x87 simulator if the call returns a float value */
if (get_method_n_ress(call_tp) > 0) {
ir_mode *const res_mode = get_type_mode(res_type);
if (res_mode != NULL && mode_is_float(res_mode)) {
- ir_graph *irg = current_ir_graph;
- ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
- irg_data->do_x87_sim = 1;
+ ir_graph *const irg = get_Block_irg(block);
+ ia32_request_x87_sim(irg);
}
}
/* special case for PIC trampoline calls */
old_no_pic_adjust = ia32_no_pic_adjust;
- ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic;
+ ia32_no_pic_adjust = be_options.pic;
match_arguments(&am, src_block, NULL, src_ptr, src_mem,
- match_am | match_immediate);
+ match_am | match_immediate | match_upconv);
ia32_no_pic_adjust = old_no_pic_adjust;
i = get_irn_arity(node) - 1;
fpcw = be_transform_node(get_irn_n(node, i--));
- for (; i >= be_pos_Call_first_arg; --i) {
- arch_register_req_t const *const req = arch_get_register_req(node, i);
+ for (; i >= n_be_Call_first_arg; --i) {
+ arch_register_req_t const *const req
+ = arch_get_irn_register_req_in(node, i);
ir_node *const reg_parm = be_transform_node(get_irn_n(node, i));
assert(req->type == arch_register_req_type_limited);
mem = transform_AM_mem(block, src_ptr, src_mem, addr->mem);
call = new_bd_ia32_Call(dbgi, block, addr->base, addr->index, mem,
am.new_op2, sp, fpcw, eax, ecx, edx, pop, call_tp);
+ ir_set_throws_exception(call, throws_exception);
set_am_attributes(call, &am);
call = fix_mem_proj(call, &am);
ir_node *frame = get_Builtin_param(node, 1);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_tarval *tv = get_Const_tarval(param);
+ ir_graph *irg = get_irn_irg(node);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
set_ia32_am_offs_int(load, 0);
set_ia32_use_frame(load);
- set_ia32_frame_ent(load, ia32_get_return_address_entity());
+ set_ia32_frame_ent(load, ia32_get_return_address_entity(irg));
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
- arch_irn_add_flags(load, arch_irn_flags_rematerializable);
+ arch_add_irn_flags(load, arch_irn_flags_rematerializable);
}
SET_IA32_ORIG_NODE(load, node);
ir_node *frame = get_Builtin_param(node, 1);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_tarval *tv = get_Const_tarval(param);
+ ir_graph *irg = get_irn_irg(node);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_ls_mode(load, mode_Iu);
- ent = ia32_get_frame_address_entity();
+ ent = ia32_get_frame_address_entity(irg);
if (ent != NULL) {
set_ia32_am_offs_int(load, 0);
set_ia32_use_frame(load);
}
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
- && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_fld_res
+ && (int)pn_ia32_fld_res == (int)pn_ia32_Load_res
&& (int)pn_ia32_Load_res == (int)pn_ia32_res);
- arch_irn_add_flags(load, arch_irn_flags_rematerializable);
+ arch_add_irn_flags(load, arch_irn_flags_rematerializable);
}
SET_IA32_ORIG_NODE(load, node);
static ir_node *gen_prefetch(ir_node *node)
{
dbg_info *dbgi;
- ir_node *ptr, *block, *mem, *base, *index;
+ ir_node *ptr, *block, *mem, *base, *idx;
ir_node *param, *new_node;
long rw, locality;
ir_tarval *tv;
memset(&addr, 0, sizeof(addr));
ptr = get_Builtin_param(node, 0);
ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
- base = addr.base;
- index = addr.index;
+ base = addr.base;
+ idx = addr.index;
if (base == NULL) {
base = noreg_GP;
base = be_transform_node(base);
}
- if (index == NULL) {
- index = noreg_GP;
+ if (idx == NULL) {
+ idx = noreg_GP;
} else {
- index = be_transform_node(index);
+ idx = be_transform_node(idx);
}
dbgi = get_irn_dbg_info(node);
if (rw == 1 && ia32_cg_config.use_3dnow_prefetch) {
/* we have 3DNow!, this was already checked above */
- new_node = new_bd_ia32_PrefetchW(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_PrefetchW(dbgi, block, base, idx, mem);
} else if (ia32_cg_config.use_sse_prefetch) {
/* note: rw == 1 is IGNORED in that case */
param = get_Builtin_param(node, 2);
/* SSE style prefetch */
switch (locality) {
case 0:
- new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_PrefetchNTA(dbgi, block, base, idx, mem);
break;
case 1:
- new_node = new_bd_ia32_Prefetch2(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch2(dbgi, block, base, idx, mem);
break;
case 2:
- new_node = new_bd_ia32_Prefetch1(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch1(dbgi, block, base, idx, mem);
break;
default:
- new_node = new_bd_ia32_Prefetch0(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch0(dbgi, block, base, idx, mem);
break;
}
} else {
assert(ia32_cg_config.use_3dnow_prefetch);
/* 3DNow! style prefetch */
- new_node = new_bd_ia32_Prefetch(dbgi, block, base, index, mem);
+ new_node = new_bd_ia32_Prefetch(dbgi, block, base, idx, mem);
}
set_irn_pinned(new_node, get_irn_pinned(node));
SET_IA32_ORIG_NODE(set, node);
/* conv to 32bit */
- conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
+ conv = new_bd_ia32_Conv_I2I_8bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
SET_IA32_ORIG_NODE(conv, node);
/* neg */
/* or */
orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
+ set_ia32_ls_mode(orn, mode_Iu);
set_ia32_commutative(orn);
/* add 1 */
ir_node *real = skip_Proj(bsr);
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
- ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
+ ir_graph *irg = get_Block_irg(block);
+ ir_node *imm = ia32_create_Immediate(irg, NULL, 0, 31);
return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
}
* chance for CSE, constant folding and other goodies for some of these
* operations)
*/
- ir_node *count = ia32_create_Immediate(NULL, 0, 16);
- ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
- ir_node *xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
- shr, new_param);
- ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xor);
- ir_node *flags;
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const count = ia32_create_Immediate(irg, NULL, 0, 16);
+ ir_node *const shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
+ ir_node *const xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, shr, new_param);
+ ir_node *const xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn);
+ ir_node *flags;
+
+ set_ia32_ls_mode(xorn, mode_Iu);
+ set_ia32_commutative(xorn);
set_irn_mode(xor2, mode_T);
flags = new_r_Proj(xor2, mode_Iu, pn_ia32_XorHighLow_flags);
SET_IA32_ORIG_NODE(new_node, node);
/* conv to 32bit */
- new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_node, mode_Bu);
+ new_node = new_bd_ia32_Conv_I2I_8bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
ia32_address_t *addr = &am.addr;
ir_node *cnt;
- match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am);
+ match_arguments(&am, block, NULL, param, NULL, match_am | match_16bit_am | match_upconv);
cnt = new_bd_ia32_Popcnt(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op2);
set_am_attributes(cnt, &am);
* But I'm too lazy to fix this now, as the code should get lowered before
* the backend anyway.
*/
+ ir_graph *const irg = get_Block_irg(new_block);
/* m1 = x & 0x55555555 */
- imm = ia32_create_Immediate(NULL, 0, 0x55555555);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x55555555);
m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
/* s1 = x >> 1 */
- simm = ia32_create_Immediate(NULL, 0, 1);
+ simm = ia32_create_Immediate(irg, NULL, 0, 1);
s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
/* m2 = s1 & 0x55555555 */
m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
/* m4 = m3 & 0x33333333 */
- imm = ia32_create_Immediate(NULL, 0, 0x33333333);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x33333333);
m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
/* s2 = m3 >> 2 */
- simm = ia32_create_Immediate(NULL, 0, 2);
+ simm = ia32_create_Immediate(irg, NULL, 0, 2);
s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
/* m5 = s2 & 0x33333333 */
m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
/* m7 = m6 & 0x0F0F0F0F */
- imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x0F0F0F0F);
m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
/* s3 = m6 >> 4 */
- simm = ia32_create_Immediate(NULL, 0, 4);
+ simm = ia32_create_Immediate(irg, NULL, 0, 4);
s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
/* m8 = s3 & 0x0F0F0F0F */
m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
/* m10 = m9 & 0x00FF00FF */
- imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x00FF00FF);
m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
/* s4 = m9 >> 8 */
- simm = ia32_create_Immediate(NULL, 0, 8);
+ simm = ia32_create_Immediate(irg, NULL, 0, 8);
s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
/* m11 = s4 & 0x00FF00FF */
m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
/* m13 = m12 & 0x0000FFFF */
- imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x0000FFFF);
m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
/* s5 = m12 >> 16 */
- simm = ia32_create_Immediate(NULL, 0, 16);
+ simm = ia32_create_Immediate(irg, NULL, 0, 16);
s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
/* res = m13 + s5 */
ir_node *new_block = be_transform_node(block);
ir_mode *mode = get_irn_mode(param);
unsigned size = get_mode_size_bits(mode);
- ir_node *m1, *m2, *m3, *m4, *s1, *s2, *s3, *s4;
switch (size) {
case 32:
- if (ia32_cg_config.use_i486) {
+ if (ia32_cg_config.use_bswap) {
/* swap available */
return new_bd_ia32_Bswap(dbgi, new_block, param);
+ } else {
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const i8 = ia32_create_Immediate(irg, NULL, 0, 8);
+ ir_node *const rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
+ ir_node *const i16 = ia32_create_Immediate(irg, NULL, 0, 16);
+ ir_node *const rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
+ ir_node *const rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
+ set_ia32_ls_mode(rol1, mode_Hu);
+ set_ia32_ls_mode(rol2, mode_Iu);
+ set_ia32_ls_mode(rol3, mode_Hu);
+ return rol3;
}
- s1 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
- s2 = new_bd_ia32_Shl(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
-
- m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s2, ia32_create_Immediate(NULL, 0, 0xFF00));
- m2 = new_bd_ia32_Lea(dbgi, new_block, s1, m1);
-
- s3 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 8));
-
- m3 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, s3, ia32_create_Immediate(NULL, 0, 0xFF0000));
- m4 = new_bd_ia32_Lea(dbgi, new_block, m2, m3);
-
- s4 = new_bd_ia32_Shr(dbgi, new_block, param, ia32_create_Immediate(NULL, 0, 24));
- return new_bd_ia32_Lea(dbgi, new_block, m4, s4);
case 16:
/* swap16 always available */
*/
static ir_node *gen_outport(ir_node *node)
{
- ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
+ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
ir_node *oldv = get_Builtin_param(node, 1);
ir_mode *mode = get_irn_mode(oldv);
ir_node *value = be_transform_node(oldv);
ir_type *tp = get_Builtin_type(node);
ir_type *rstp = get_method_res_type(tp, 0);
ir_mode *mode = get_type_mode(rstp);
- ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
+ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *mem = be_transform_node(get_Builtin_mem(node));
dbg_info *dbgi = get_irn_dbg_info(node);
}
addr.mem = be_transform_node(mem);
+ ir_graph *const irg = get_Block_irg(new_block);
/* mov ecx, <env> */
- val = ia32_create_Immediate(NULL, 0, 0xB9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ val = ia32_create_Immediate(irg, NULL, 0, 0xB9);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
addr.offset += 4;
/* jmp rel <callee> */
- val = ia32_create_Immediate(NULL, 0, 0xE9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ val = ia32_create_Immediate(irg, NULL, 0, 0xE9);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
case ir_bk_inner_trampoline:
return gen_inner_trampoline(node);
}
- panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
+ panic("Builtin %s not implemented", get_builtin_kind_name(kind));
}
/**
case ir_bk_parity:
case ir_bk_popcount:
case ir_bk_bswap:
- assert(get_Proj_proj(proj) == pn_Builtin_1_result);
+ assert(get_Proj_proj(proj) == pn_Builtin_max+1);
return new_node;
case ir_bk_trap:
case ir_bk_debugbreak:
assert(get_Proj_proj(proj) == pn_Builtin_M);
return new_node;
case ir_bk_inport:
- if (get_Proj_proj(proj) == pn_Builtin_1_result) {
+ if (get_Proj_proj(proj) == pn_Builtin_max+1) {
return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res);
} else {
assert(get_Proj_proj(proj) == pn_Builtin_M);
return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M);
}
case ir_bk_inner_trampoline:
- if (get_Proj_proj(proj) == pn_Builtin_1_result) {
+ if (get_Proj_proj(proj) == pn_Builtin_max+1) {
return get_Tuple_pred(new_node, 1);
} else {
assert(get_Proj_proj(proj) == pn_Builtin_M);
return get_Tuple_pred(new_node, 0);
}
}
- panic("Builtin %s not implemented in IA32", get_builtin_kind_name(kind));
+ panic("Builtin %s not implemented", get_builtin_kind_name(kind));
}
static ir_node *gen_be_IncSP(ir_node *node)
{
ir_node *res = be_duplicate_node(node);
- arch_irn_add_flags(res, arch_irn_flags_modify_flags);
+ arch_add_irn_flags(res, arch_irn_flags_modify_flags);
return res;
}
ir_mode *mode = get_irn_mode(node);
ir_node *res;
- if (proj == pn_be_Call_M_regular) {
+ if (proj == pn_be_Call_M) {
return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
}
/* transform call modes */
if (mode_is_data(mode)) {
- const arch_register_class_t *cls = arch_get_irn_reg_class_out(node);
+ const arch_register_class_t *cls = arch_get_irn_reg_class(node);
mode = cls->mode;
}
/* Map from be_Call to ia32_Call proj number */
if (proj == pn_be_Call_sp) {
proj = pn_ia32_Call_stack;
- } else if (proj == pn_be_Call_M_regular) {
+ } else if (proj == pn_be_Call_M) {
proj = pn_ia32_Call_M;
+ } else if (proj == pn_be_Call_X_except) {
+ proj = pn_ia32_Call_X_except;
+ } else if (proj == pn_be_Call_X_regular) {
+ proj = pn_ia32_Call_X_regular;
} else {
- arch_register_req_t const *const req = arch_get_register_req_out(node);
- int const n_outs = arch_irn_get_n_outs(new_call);
- int i;
+ arch_register_req_t const *const req = arch_get_irn_register_req(node);
- assert(proj >= pn_be_Call_first_res);
- assert(req->type & arch_register_req_type_limited);
+ assert(proj >= pn_be_Call_first_res);
+ assert(arch_register_req_is(req, limited));
- for (i = 0; i < n_outs; ++i) {
- arch_register_req_t const *const new_req
- = arch_get_out_register_req(new_call, i);
-
- if (!(new_req->type & arch_register_req_type_limited) ||
- new_req->cls != req->cls ||
+ be_foreach_out(new_call, i) {
+ arch_register_req_t const *const new_req = arch_get_irn_register_req_out(new_call, i);
+ if (!arch_register_req_is(new_req, limited) ||
+ new_req->cls != req->cls ||
*new_req->limited != *req->limited)
continue;
proj = i;
- break;
+ goto found;
}
- assert(i < n_outs);
+ panic("no matching out requirement found");
+found:;
}
res = new_rd_Proj(dbgi, new_call, mode, proj);
/* TODO arch_set_irn_register() only operates on Projs, need variant with index */
switch (proj) {
- case pn_ia32_Call_stack:
- arch_set_irn_register(res, &ia32_registers[REG_ESP]);
- break;
+ case pn_ia32_Call_stack:
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
+ break;
- case pn_ia32_Call_fpcw:
- arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
- break;
+ case pn_ia32_Call_fpcw:
+ arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
+ break;
}
return res;
}
-/**
- * Transform the Projs from a Cmp.
- */
-static ir_node *gen_Proj_Cmp(ir_node *node)
-{
- /* this probably means not all mode_b nodes were lowered... */
- panic("trying to directly transform Proj_Cmp %+F (mode_b not lowered?)",
- node);
-}
-
static ir_node *gen_Proj_ASM(ir_node *node)
{
ir_mode *mode = get_irn_mode(node);
long pos = get_Proj_proj(node);
if (mode == mode_M) {
- pos = arch_irn_get_n_outs(new_pred)-1;
+ pos = arch_get_irn_n_outs(new_pred)-1;
} else if (mode_is_int(mode) || mode_is_reference(mode)) {
mode = mode_Iu;
} else if (mode_is_float(mode)) {
- mode = mode_E;
+ mode = ia32_mode_E;
} else {
panic("unexpected proj mode at ASM");
}
long proj;
switch (get_irn_opcode(pred)) {
- case iro_Store:
- proj = get_Proj_proj(node);
- if (proj == pn_Store_M) {
- return be_transform_node(pred);
- } else {
- panic("No idea how to transform proj->Store");
- }
case iro_Load:
return gen_Proj_Load(node);
+ case iro_Store:
+ return gen_Proj_Store(node);
case iro_ASM:
return gen_Proj_ASM(node);
case iro_Builtin:
return gen_Proj_be_AddSP(node);
case beo_Call:
return gen_Proj_be_Call(node);
- case iro_Cmp:
- return gen_Proj_Cmp(node);
case iro_Start:
proj = get_Proj_proj(node);
switch (proj) {
return jump;
}
-
- case pn_Start_P_tls:
- return ia32_gen_Proj_tls(node);
}
break;
be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
- be_set_transform_function(op_ia32_l_SarDep, gen_ia32_l_SarDep);
be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
- be_set_transform_function(op_ia32_l_ShlDep, gen_ia32_l_ShlDep);
- be_set_transform_function(op_ia32_l_ShlD, gen_ia32_l_ShlD);
- be_set_transform_function(op_ia32_l_ShrDep, gen_ia32_l_ShrDep);
- be_set_transform_function(op_ia32_l_ShrD, gen_ia32_l_ShrD);
be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
- be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
+ be_set_transform_function(op_ia32_NoReg_FP, be_duplicate_node);
be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
be_set_transform_function(op_ia32_Push, be_duplicate_node);
be_set_transform_function(op_Shrs, gen_Shrs);
be_set_transform_function(op_Store, gen_Store);
be_set_transform_function(op_Sub, gen_Sub);
+ be_set_transform_function(op_Switch, gen_Switch);
be_set_transform_function(op_SymConst, gen_SymConst);
be_set_transform_function(op_Unknown, ia32_gen_Unknown);
+
+ be_set_upper_bits_clean_function(op_Mux, ia32_mux_upper_bits_clean);
}
/**
static void ia32_pretransform_node(void)
{
ir_graph *irg = current_ir_graph;
- ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
- irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
+ irg_data->noreg_fp = be_pre_transform_node(irg_data->noreg_fp);
irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
irg_data->get_eip = be_pre_transform_node(irg_data->get_eip);
irg_data->fpu_trunc_mode = be_pre_transform_node(irg_data->fpu_trunc_mode);
nomem = get_irg_no_mem(irg);
noreg_GP = ia32_new_NoReg_gp(irg);
-
- get_fpcw();
}
/**
for (j = get_method_n_ress(mtp) - 1; j >= 0; --j) {
ir_type *res_tp = get_method_res_type(mtp, j);
ir_node *res, *new_res;
- const ir_edge_t *edge, *next;
- ir_mode *mode;
+ ir_mode *res_mode;
if (! is_atomic_type(res_tp)) {
/* no floating point return */
continue;
}
- mode = get_type_mode(res_tp);
- if (! mode_is_float(mode)) {
+ res_mode = get_type_mode(res_tp);
+ if (! mode_is_float(res_mode)) {
/* no floating point return */
continue;
}
- res = be_get_Proj_for_pn(call, pn_ia32_Call_vf0 + j);
+ res = be_get_Proj_for_pn(call, pn_ia32_Call_st0 + j);
new_res = NULL;
/* now patch the users */
- foreach_out_edge_safe(res, edge, next) {
+ foreach_out_edge_safe(res, edge) {
ir_node *succ = get_edge_src_irn(edge);
/* ignore Keeps */
dbg_info *db = get_irn_dbg_info(succ);
ir_node *block = get_nodes_block(succ);
ir_node *base = get_irn_n(succ, n_ia32_xStore_base);
- ir_node *index = get_irn_n(succ, n_ia32_xStore_index);
+ ir_node *idx = get_irn_n(succ, n_ia32_xStore_index);
ir_node *mem = get_irn_n(succ, n_ia32_xStore_mem);
ir_node *value = get_irn_n(succ, n_ia32_xStore_val);
ir_mode *mode = get_ia32_ls_mode(succ);
- ir_node *st = new_bd_ia32_vfst(db, block, base, index, mem, value, mode);
+ ir_node *st = new_bd_ia32_fst(db, block, base, idx, mem, value, mode);
+ //ir_node *mem = new_r_Proj(st, mode_M, pn_ia32_fst_M);
set_ia32_am_offs_int(st, get_ia32_am_offs_int(succ));
if (is_ia32_use_frame(succ))
set_ia32_use_frame(st);
set_irn_pinned(st, get_irn_pinned(succ));
set_ia32_op_type(st, ia32_AddrModeD);
+ assert((long)pn_ia32_xStore_M == (long)pn_ia32_fst_M);
+ assert((long)pn_ia32_xStore_X_regular == (long)pn_ia32_fst_X_regular);
+ assert((long)pn_ia32_xStore_X_except == (long)pn_ia32_fst_X_except);
+
exchange(succ, st);
- } else {
- if (new_res == NULL) {
- dbg_info *db = get_irn_dbg_info(call);
- ir_node *block = get_nodes_block(call);
- ir_node *frame = get_irg_frame(current_ir_graph);
- ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
- ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
- ir_node *vfst, *xld, *new_mem;
-
- /* store st(0) on stack */
- vfst = new_bd_ia32_vfst(db, block, frame, noreg_GP, call_mem, res, mode);
- set_ia32_op_type(vfst, ia32_AddrModeD);
- set_ia32_use_frame(vfst);
-
- /* load into SSE register */
- xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst, mode);
- set_ia32_op_type(xld, ia32_AddrModeS);
- set_ia32_use_frame(xld);
-
- new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res);
- new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
-
- if (old_mem != NULL) {
- edges_reroute(old_mem, new_mem, current_ir_graph);
- kill_node(old_mem);
- }
+
+ continue;
+ }
+
+ if (new_res == NULL) {
+ dbg_info *db = get_irn_dbg_info(call);
+ ir_node *block = get_nodes_block(call);
+ ir_node *frame = get_irg_frame(current_ir_graph);
+ ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
+ ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
+ ir_node *vfst, *xld, *new_mem;
+ ir_node *vfst_mem;
+
+ /* store st(0) on stack */
+ vfst = new_bd_ia32_fst(db, block, frame, noreg_GP, call_mem,
+ res, res_mode);
+ set_ia32_op_type(vfst, ia32_AddrModeD);
+ set_ia32_use_frame(vfst);
+ arch_add_irn_flags(vfst, arch_irn_flags_spill);
+
+ vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_fst_M);
+
+ /* load into SSE register */
+ xld = new_bd_ia32_xLoad(db, block, frame, noreg_GP, vfst_mem,
+ res_mode);
+ set_ia32_op_type(xld, ia32_AddrModeS);
+ set_ia32_use_frame(xld);
+
+ new_res = new_r_Proj(xld, res_mode, pn_ia32_xLoad_res);
+ new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
+
+ if (old_mem != NULL) {
+ edges_reroute(old_mem, new_mem);
+ kill_node(old_mem);
}
- set_irn_n(succ, get_edge_src_pos(edge), new_res);
}
+ set_irn_n(succ, get_edge_src_pos(edge), new_res);
}
}
}
initial_fpcw = NULL;
ia32_no_pic_adjust = 0;
+ old_initial_fpcw = be_get_initial_reg_value(irg, &ia32_registers[REG_FPCW]);
+
be_timer_push(T_HEIGHTS);
ia32_heights = heights_new(irg);
be_timer_pop(T_HEIGHTS);
projects / libfirm / blobdiff