/*
- * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
- *
* This file is part of libFirm.
- *
- * This file may be distributed and/or modified under the terms of the
- * GNU General Public License version 2 as published by the Free Software
- * Foundation and appearing in the file LICENSE.GPL included in the
- * packaging of this file.
- *
- * Licensees holding valid libFirm Professional Edition licenses may use
- * this file in accordance with the libFirm Commercial License.
- * Agreement provided with the Software.
- *
- * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
- * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE.
+ * Copyright (C) 2012 University of Karlsruhe.
*/
/**
typedef ir_node *construct_unop_func(dbg_info *db, ir_node *block, ir_node *op);
-static ir_node *create_immediate_or_transform(ir_node *node,
- char immediate_constraint_type);
+static ir_node *create_immediate_or_transform(ir_node *node);
static ir_node *create_I2I_Conv(ir_mode *src_mode, ir_mode *tgt_mode,
dbg_info *dbgi, ir_node *block,
ir_mode *mode = get_irn_mode(node);
ir_tarval *tv = get_Const_tarval(node);
- assert(is_Const(node));
-
if (mode_is_float(mode)) {
ir_graph *irg = get_irn_irg(node);
const arch_env_t *arch_env = be_get_irg_arch_env(irg);
#ifdef CONSTRUCT_SSE_CONST
} else if (tarval_is_one(tv)) {
int cnst = mode == mode_F ? 26 : 55;
- ir_node *imm1 = ia32_create_Immediate(NULL, 0, cnst);
- ir_node *imm2 = ia32_create_Immediate(NULL, 0, 2);
+ ir_node *imm1 = ia32_create_Immediate(irg, NULL, 0, cnst);
+ ir_node *imm2 = ia32_create_Immediate(irg, NULL, 0, 2);
ir_node *pslld, *psrld;
load = new_bd_ia32_xAllOnes(dbgi, block);
(get_tarval_sub_bits(tv, 2) << 16) |
(get_tarval_sub_bits(tv, 3) << 24);
if (val == 0) {
- ir_node *imm32 = ia32_create_Immediate(NULL, 0, 32);
+ ir_node *imm32 = ia32_create_Immediate(irg, NULL, 0, 32);
ir_node *cnst, *psllq;
/* fine, lower 32bit are zero, produce 32bit value */
}
/**
- * Check, if a given node is a Down-Conv, ie. a integer Conv
+ * Check, if a given node is a Down-Conv, i.e. a integer Conv
* from a mode with a mode with more bits to a mode with lesser bits.
* Moreover, we return only true if the node has not more than 1 user.
*
}
}
+static ir_node *get_noreg(ir_mode *const mode)
+{
+ if (!mode_is_float(mode)) {
+ return noreg_GP;
+ } else if (ia32_cg_config.use_sse2) {
+ return ia32_new_NoReg_xmm(current_ir_graph);
+ } else {
+ return ia32_new_NoReg_fp(current_ir_graph);
+ }
+}
+
/**
* matches operands of a node into ia32 addressing/operand modes. This covers
* usage of source address mode, immediates, operations with non 32-bit modes,
* op2 input */
new_op2 = NULL;
if (!(flags & match_try_am) && use_immediate) {
- new_op2 = ia32_try_create_Immediate(op2, 0);
+ new_op2 = ia32_try_create_Immediate(op2, 'i');
}
if (new_op2 == NULL &&
use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
build_address(am, op2, ia32_create_am_normal);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
- if (mode_is_float(mode)) {
- new_op2 = ia32_new_NoReg_fp(current_ir_graph);
- } else {
- new_op2 = noreg_GP;
- }
+ new_op2 = get_noreg(mode);
am->op_type = ia32_AddrModeS;
} else if (commutative && (new_op2 == NULL || use_am_and_immediates) &&
use_am &&
ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
- ir_node *noreg;
build_address(am, op1, ia32_create_am_normal);
- if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_fp(current_ir_graph);
- } else {
- noreg = noreg_GP;
- }
-
+ ir_node *const noreg = get_noreg(mode);
if (new_op2 != NULL) {
new_op1 = noreg;
} else {
op2 = op;
assert(get_mode_size_bits(get_irn_mode(op2)) >= 5);
}
- new_op2 = create_immediate_or_transform(op2, 0);
+ new_op2 = create_immediate_or_transform(op2);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
assert(get_mode_size_bits(get_irn_mode(count)) >= 5);
count = get_Conv_op(count);
}
- new_count = create_immediate_or_transform(count, 0);
+ new_count = create_immediate_or_transform(count);
new_node = func(dbgi, new_block, new_high, new_low, new_count);
return new_node;
}
/**
- * test wether 2 values result in 'x' and '32-x' when interpreted as a shift
+ * Tests whether 2 values result in 'x' and '32-x' when interpreted as a shift
* value.
*/
static bool is_complementary_shifts(ir_node *value1, ir_node *value2)
ir_node *pval = new_bd_ia32_ProduceVal(dbgi, block);
res = new_bd_ia32_Cltd(dbgi, block, val, pval);
} else {
- ir_node *imm31 = ia32_create_Immediate(NULL, 0, 31);
+ ir_graph *const irg = get_Block_irg(block);
+ ir_node *const imm31 = ia32_create_Immediate(irg, NULL, 0, 31);
res = new_bd_ia32_Sar(dbgi, block, val, imm31);
}
SET_IA32_ORIG_NODE(res, orig);
if (use_dest_am(src_block, op1, mem, ptr, op2)) {
build_address(&am, op1, ia32_create_am_double_use);
- new_op = create_immediate_or_transform(op2, 0);
+ new_op = create_immediate_or_transform(op2);
} else if (commutative && use_dest_am(src_block, op2, mem, ptr, op1)) {
build_address(&am, op2, ia32_create_am_double_use);
- new_op = create_immediate_or_transform(op1, 0);
+ new_op = create_immediate_or_transform(op1);
} else {
return NULL;
}
}
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_AddMem, new_bd_ia32_AddMem8Bit,
+ new_bd_ia32_AddMem, new_bd_ia32_AddMem_8bit,
match_commutative | match_immediate);
break;
case iro_Sub:
ir_fprintf(stderr, "Optimisation warning: not-normalized sub ,C found\n");
}
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_SubMem, new_bd_ia32_SubMem8Bit,
+ new_bd_ia32_SubMem, new_bd_ia32_SubMem_8bit,
match_immediate);
break;
case iro_And:
op1 = get_And_left(val);
op2 = get_And_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_AndMem, new_bd_ia32_AndMem8Bit,
+ new_bd_ia32_AndMem, new_bd_ia32_AndMem_8bit,
match_commutative | match_immediate);
break;
case iro_Or:
op1 = get_Or_left(val);
op2 = get_Or_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_OrMem, new_bd_ia32_OrMem8Bit,
+ new_bd_ia32_OrMem, new_bd_ia32_OrMem_8bit,
match_commutative | match_immediate);
break;
case iro_Eor:
op1 = get_Eor_left(val);
op2 = get_Eor_right(val);
new_node = dest_am_binop(val, op1, op2, mem, ptr, mode,
- new_bd_ia32_XorMem, new_bd_ia32_XorMem8Bit,
+ new_bd_ia32_XorMem, new_bd_ia32_XorMem_8bit,
match_commutative | match_immediate);
break;
case iro_Shl:
} else {
panic("invalid size of Store float to mem (%+F)", node);
}
- ir_node *imm = ia32_create_Immediate(NULL, 0, val);
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const imm = ia32_create_Immediate(irg, NULL, 0, val);
ir_node *new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
addr.index, addr.mem, imm);
&& get_mode_size_bits(get_irn_mode(val)) >= dest_bits) {
val = get_Conv_op(val);
}
- new_val = create_immediate_or_transform(val, 0);
+ new_val = create_immediate_or_transform(val);
assert(mode != mode_b);
- if (dest_bits == 8) {
- new_node = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- } else {
- new_node = new_bd_ia32_Store(dbgi, new_block, addr.base,
- addr.index, addr.mem, new_val);
- }
+ new_node = dest_bits == 8
+ ? new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, new_val)
+ : new_bd_ia32_Store (dbgi, new_block, addr.base, addr.index, addr.mem, new_val);
}
ir_set_throws_exception(new_node, throws_exception);
const ir_switch_table *table = get_Switch_table(node);
unsigned n_outs = get_Switch_n_outs(node);
ir_node *new_node;
- ir_entity *entity;
assert(get_mode_size_bits(sel_mode) <= 32);
assert(!mode_is_float(sel_mode));
if (get_mode_size_bits(sel_mode) < 32)
new_sel = transform_upconv(sel, node);
- entity = new_entity(NULL, id_unique("TBL%u"), get_unknown_type());
+ ir_type *const utype = get_unknown_type();
+ ir_entity *const entity = new_entity(utype, id_unique("TBL%u"), utype);
set_entity_visibility(entity, ir_visibility_private);
add_entity_linkage(entity, IR_LINKAGE_CONSTANT);
cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
}
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_bd_ia32_Test8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem,
- am.new_op1, am.new_op2,
- am.ins_permuted);
- } else {
- new_node = new_bd_ia32_Test(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted);
- }
+ new_node = get_mode_size_bits(cmp_mode) == 8
+ ? new_bd_ia32_Test_8bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted)
+ : new_bd_ia32_Test (dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
} else {
/* Cmp(left, right) */
match_arguments(&am, block, left, right, NULL,
cmp_mode = mode_is_signed(cmp_mode) ? mode_Is : mode_Iu;
}
- if (get_mode_size_bits(cmp_mode) == 8) {
- new_node = new_bd_ia32_Cmp8Bit(dbgi, new_block, addr->base,
- addr->index, addr->mem, am.new_op1,
- am.new_op2, am.ins_permuted);
- } else {
- new_node = new_bd_ia32_Cmp(dbgi, new_block, addr->base, addr->index,
- addr->mem, am.new_op1, am.new_op2,
- am.ins_permuted);
- }
+ new_node = get_mode_size_bits(cmp_mode) == 8
+ ? new_bd_ia32_Cmp_8bit(dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted)
+ : new_bd_ia32_Cmp (dbgi, new_block, addr->base, addr->index, addr->mem, am.new_op1, am.new_op2, am.ins_permuted);
}
set_am_attributes(new_node, &am);
set_ia32_ls_mode(new_node, cmp_mode);
/* we might need to conv the result up */
if (get_mode_size_bits(mode) > 8) {
- new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_node, mode_Bu);
+ new_node = new_bd_ia32_Conv_I2I_8bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, orig_node);
}
set_irn_pinned(fist, op_pin_state_floats);
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
+ arch_add_irn_flags(fist, arch_irn_flags_spill);
assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
mem = new_r_Proj(fist, mode_M, pn_ia32_fist_M);
store = new_bd_ia32_fst(dbgi, block, frame, noreg_GP, nomem, node, tgt_mode);
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
+ arch_add_irn_flags(store, arch_irn_flags_spill);
SET_IA32_ORIG_NODE(store, node);
store_mem = new_r_Proj(store, mode_M, pn_ia32_fst_M);
ir_node *(*func)(dbg_info*, ir_node*, ir_node*, ir_node*, ir_node*, ir_node*, ir_mode*);
func = get_mode_size_bits(mode) == 8 ?
- new_bd_ia32_Conv_I2I8Bit : new_bd_ia32_Conv_I2I;
+ new_bd_ia32_Conv_I2I_8bit : new_bd_ia32_Conv_I2I;
return func(dbgi, block, base, index, mem, val, mode);
}
set_ia32_use_frame(store);
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Iu);
+ arch_add_irn_flags(store, arch_irn_flags_spill);
store_mem = new_r_Proj(store, mode_M, pn_ia32_Store_M);
if (!mode_is_signed(mode)) {
ir_node *in[2];
/* store a zero */
- ir_node *zero_const = ia32_create_Immediate(NULL, 0, 0);
+ ir_node *zero_const = ia32_create_Immediate(irg, NULL, 0, 0);
ir_node *zero_store = new_bd_ia32_Store(dbgi, block, get_irg_frame(irg),
noreg_GP, nomem, zero_const);
set_ia32_op_type(zero_store, ia32_AddrModeD);
add_ia32_am_offs_int(zero_store, 4);
set_ia32_ls_mode(zero_store, mode_Iu);
+ arch_add_irn_flags(zero_store, arch_irn_flags_spill);
in[0] = zero_store_mem;
in[1] = store_mem;
return res;
}
-static ir_node *create_immediate_or_transform(ir_node *node,
- char immediate_constraint_type)
+static ir_node *create_immediate_or_transform(ir_node *const node)
{
- ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
+ ir_node *new_node = ia32_try_create_Immediate(node, 'i');
if (new_node == NULL) {
new_node = be_transform_node(node);
}
*/
static ir_node *gen_be_Return(ir_node *node)
{
- ir_graph *irg = current_ir_graph;
ir_node *ret_val = get_irn_n(node, n_be_Return_val);
ir_node *ret_mem = get_irn_n(node, n_be_Return_mem);
ir_node *new_ret_val = be_transform_node(ret_val);
ir_node *new_ret_mem = be_transform_node(ret_mem);
- ir_entity *ent = get_irg_entity(irg);
- ir_type *tp = get_entity_type(ent);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
+ ir_graph *irg = get_Block_irg(block);
+ ir_entity *ent = get_irg_entity(irg);
+ ir_type *tp = get_entity_type(ent);
ir_type *res_type;
ir_mode *mode;
ir_node *frame;
int arity;
unsigned pop;
ir_node **in;
- ir_node *new_node;
assert(ret_val != NULL);
if (be_Return_get_n_rets(node) < 1 || ! ia32_cg_config.use_sse2) {
set_ia32_ls_mode(sse_store, mode);
set_ia32_op_type(sse_store, ia32_AddrModeD);
set_ia32_use_frame(sse_store);
+ arch_add_irn_flags(sse_store, arch_irn_flags_spill);
store_mem = new_r_Proj(sse_store, mode_M, pn_ia32_xStoreSimple_M);
/* load into x87 register */
in[i] = be_transform_node(op);
}
}
- new_node = be_new_Return(dbgi, irg, block, arity, pop, arity, in);
+ ir_node *const new_node = be_new_Return(dbgi, block, arity, pop, arity, in);
copy_node_attr(irg, node, new_node);
return new_node;
{
ir_node *src_block = get_nodes_block(node);
ir_node *block = be_transform_node(src_block);
- ir_graph *irg = current_ir_graph;
+ ir_graph *irg = get_Block_irg(block);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *frame = get_irg_frame(irg);
ir_node *val_low = get_irn_n(node, n_ia32_l_LLtoFloat_val_low);
set_ia32_op_type(store_high, ia32_AddrModeD);
set_ia32_ls_mode(store_low, mode_Iu);
set_ia32_ls_mode(store_high, mode_Is);
+ arch_add_irn_flags(store_low, arch_irn_flags_spill);
+ arch_add_irn_flags(store_high, arch_irn_flags_spill);
add_ia32_am_offs_int(store_high, 4);
in[0] = mem_low;
if (! mode_is_signed(get_irn_mode(val_high))) {
ia32_address_mode_t am;
- ir_node *count = ia32_create_Immediate(NULL, 0, 31);
+ ir_node *count = ia32_create_Immediate(irg, NULL, 0, 31);
ir_node *fadd;
am.addr.base = get_symconst_base();
am.mem_proj = nomem;
am.op_type = ia32_AddrModeS;
am.new_op1 = res;
- am.new_op2 = ia32_new_NoReg_fp(current_ir_graph);
+ am.new_op2 = ia32_new_NoReg_fp(irg);
am.pinned = op_pin_state_floats;
am.commutative = 1;
am.ins_permuted = false;
set_ia32_use_frame(fist);
set_ia32_op_type(fist, ia32_AddrModeD);
set_ia32_ls_mode(fist, mode_Ls);
+ arch_add_irn_flags(fist, arch_irn_flags_spill);
assert((long)pn_ia32_fist_M == (long) pn_ia32_fisttp_M);
return new_r_Proj(fist, mode_M, pn_ia32_fist_M);
case pn_Load_X_regular:
return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_regular);
}
- } else if (is_ia32_Conv_I2I(new_pred) ||
- is_ia32_Conv_I2I8Bit(new_pred)) {
+ } else if (is_ia32_Conv_I2I(new_pred)) {
set_irn_mode(new_pred, mode_T);
switch ((pn_Load)proj) {
case pn_Load_res:
dbg_info *dbgi = get_irn_dbg_info(node);
long pn = get_Proj_proj(node);
- if (is_ia32_Store(new_pred) || is_ia32_Store8Bit(new_pred)) {
+ if (is_ia32_Store(new_pred)) {
switch ((pn_Store)pn) {
case pn_Store_M:
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Store_M);
ir_mode *const res_mode = get_type_mode(res_type);
if (res_mode != NULL && mode_is_float(res_mode)) {
- ir_graph *irg = current_ir_graph;
- ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
- irg_data->do_x87_sim = 1;
+ ir_graph *const irg = get_Block_irg(block);
+ ia32_request_x87_sim(irg);
}
}
SET_IA32_ORIG_NODE(set, node);
/* conv to 32bit */
- conv = new_bd_ia32_Conv_I2I8Bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
+ conv = new_bd_ia32_Conv_I2I_8bit(dbgi, block, noreg_GP, noreg_GP, nomem, set, mode_Bu);
SET_IA32_ORIG_NODE(conv, node);
/* neg */
ir_node *real = skip_Proj(bsr);
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
- ir_node *imm = ia32_create_Immediate(NULL, 0, 31);
+ ir_graph *irg = get_Block_irg(block);
+ ir_node *imm = ia32_create_Immediate(irg, NULL, 0, 31);
return new_bd_ia32_Xor(dbgi, block, noreg_GP, noreg_GP, nomem, bsr, imm);
}
* chance for CSE, constant folding and other goodies for some of these
* operations)
*/
- ir_node *count = ia32_create_Immediate(NULL, 0, 16);
- ir_node *shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
- ir_node *xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem,
- shr, new_param);
- ir_node *xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn);
- ir_node *flags;
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const count = ia32_create_Immediate(irg, NULL, 0, 16);
+ ir_node *const shr = new_bd_ia32_Shr(dbgi, new_block, new_param, count);
+ ir_node *const xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP, nomem, shr, new_param);
+ ir_node *const xor2 = new_bd_ia32_XorHighLow(dbgi, new_block, xorn);
+ ir_node *flags;
set_ia32_ls_mode(xorn, mode_Iu);
set_ia32_commutative(xorn);
SET_IA32_ORIG_NODE(new_node, node);
/* conv to 32bit */
- new_node = new_bd_ia32_Conv_I2I8Bit(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_node, mode_Bu);
+ new_node = new_bd_ia32_Conv_I2I_8bit(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, mode_Bu);
SET_IA32_ORIG_NODE(new_node, node);
return new_node;
}
* But I'm too lazy to fix this now, as the code should get lowered before
* the backend anyway.
*/
+ ir_graph *const irg = get_Block_irg(new_block);
/* m1 = x & 0x55555555 */
- imm = ia32_create_Immediate(NULL, 0, 0x55555555);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x55555555);
m1 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_param, imm);
/* s1 = x >> 1 */
- simm = ia32_create_Immediate(NULL, 0, 1);
+ simm = ia32_create_Immediate(irg, NULL, 0, 1);
s1 = new_bd_ia32_Shr(dbgi, new_block, new_param, simm);
/* m2 = s1 & 0x55555555 */
m3 = new_bd_ia32_Lea(dbgi, new_block, m2, m1);
/* m4 = m3 & 0x33333333 */
- imm = ia32_create_Immediate(NULL, 0, 0x33333333);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x33333333);
m4 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m3, imm);
/* s2 = m3 >> 2 */
- simm = ia32_create_Immediate(NULL, 0, 2);
+ simm = ia32_create_Immediate(irg, NULL, 0, 2);
s2 = new_bd_ia32_Shr(dbgi, new_block, m3, simm);
/* m5 = s2 & 0x33333333 */
m6 = new_bd_ia32_Lea(dbgi, new_block, m4, m5);
/* m7 = m6 & 0x0F0F0F0F */
- imm = ia32_create_Immediate(NULL, 0, 0x0F0F0F0F);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x0F0F0F0F);
m7 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m6, imm);
/* s3 = m6 >> 4 */
- simm = ia32_create_Immediate(NULL, 0, 4);
+ simm = ia32_create_Immediate(irg, NULL, 0, 4);
s3 = new_bd_ia32_Shr(dbgi, new_block, m6, simm);
/* m8 = s3 & 0x0F0F0F0F */
m9 = new_bd_ia32_Lea(dbgi, new_block, m7, m8);
/* m10 = m9 & 0x00FF00FF */
- imm = ia32_create_Immediate(NULL, 0, 0x00FF00FF);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x00FF00FF);
m10 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m9, imm);
/* s4 = m9 >> 8 */
- simm = ia32_create_Immediate(NULL, 0, 8);
+ simm = ia32_create_Immediate(irg, NULL, 0, 8);
s4 = new_bd_ia32_Shr(dbgi, new_block, m9, simm);
/* m11 = s4 & 0x00FF00FF */
m12 = new_bd_ia32_Lea(dbgi, new_block, m10, m11);
/* m13 = m12 & 0x0000FFFF */
- imm = ia32_create_Immediate(NULL, 0, 0x0000FFFF);
+ imm = ia32_create_Immediate(irg, NULL, 0, 0x0000FFFF);
m13 = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, m12, imm);
/* s5 = m12 >> 16 */
- simm = ia32_create_Immediate(NULL, 0, 16);
+ simm = ia32_create_Immediate(irg, NULL, 0, 16);
s5 = new_bd_ia32_Shr(dbgi, new_block, m12, simm);
/* res = m13 + s5 */
/* swap available */
return new_bd_ia32_Bswap(dbgi, new_block, param);
} else {
- ir_node *i8 = ia32_create_Immediate(NULL, 0, 8);
- ir_node *rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
- ir_node *i16 = ia32_create_Immediate(NULL, 0, 16);
- ir_node *rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
- ir_node *rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
+ ir_graph *const irg = get_Block_irg(new_block);
+ ir_node *const i8 = ia32_create_Immediate(irg, NULL, 0, 8);
+ ir_node *const rol1 = new_bd_ia32_Rol(dbgi, new_block, param, i8);
+ ir_node *const i16 = ia32_create_Immediate(irg, NULL, 0, 16);
+ ir_node *const rol2 = new_bd_ia32_Rol(dbgi, new_block, rol1, i16);
+ ir_node *const rol3 = new_bd_ia32_Rol(dbgi, new_block, rol2, i8);
set_ia32_ls_mode(rol1, mode_Hu);
set_ia32_ls_mode(rol2, mode_Iu);
set_ia32_ls_mode(rol3, mode_Hu);
*/
static ir_node *gen_outport(ir_node *node)
{
- ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
+ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
ir_node *oldv = get_Builtin_param(node, 1);
ir_mode *mode = get_irn_mode(oldv);
ir_node *value = be_transform_node(oldv);
ir_type *tp = get_Builtin_type(node);
ir_type *rstp = get_method_res_type(tp, 0);
ir_mode *mode = get_type_mode(rstp);
- ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
+ ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0));
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *mem = be_transform_node(get_Builtin_mem(node));
dbg_info *dbgi = get_irn_dbg_info(node);
}
addr.mem = be_transform_node(mem);
+ ir_graph *const irg = get_Block_irg(new_block);
/* mov ecx, <env> */
- val = ia32_create_Immediate(NULL, 0, 0xB9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ val = ia32_create_Immediate(irg, NULL, 0, 0xB9);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
addr.offset += 4;
/* jmp rel <callee> */
- val = ia32_create_Immediate(NULL, 0, 0xE9);
- store = new_bd_ia32_Store8Bit(dbgi, new_block, addr.base,
- addr.index, addr.mem, val);
+ val = ia32_create_Immediate(irg, NULL, 0, 0xE9);
+ store = new_bd_ia32_Store_8bit(dbgi, new_block, addr.base, addr.index, addr.mem, val);
set_irn_pinned(store, get_irn_pinned(node));
set_ia32_op_type(store, ia32_AddrModeD);
set_ia32_ls_mode(store, mode_Bu);
proj = pn_ia32_Call_X_regular;
} else {
arch_register_req_t const *const req = arch_get_irn_register_req(node);
- int const n_outs = arch_get_irn_n_outs(new_call);
- int i;
-
- assert(proj >= pn_be_Call_first_res);
- assert(req->type & arch_register_req_type_limited);
- for (i = 0; i < n_outs; ++i) {
- arch_register_req_t const *const new_req
- = arch_get_irn_register_req_out(new_call, i);
+ assert(proj >= pn_be_Call_first_res);
+ assert(arch_register_req_is(req, limited));
- if (!(new_req->type & arch_register_req_type_limited) ||
- new_req->cls != req->cls ||
+ be_foreach_out(new_call, i) {
+ arch_register_req_t const *const new_req = arch_get_irn_register_req_out(new_call, i);
+ if (!arch_register_req_is(new_req, limited) ||
+ new_req->cls != req->cls ||
*new_req->limited != *req->limited)
continue;
proj = i;
- break;
+ goto found;
}
- assert(i < n_outs);
+ panic("no matching out requirement found");
+found:;
}
res = new_rd_Proj(dbgi, new_call, mode, proj);
static void ia32_pretransform_node(void)
{
ir_graph *irg = current_ir_graph;
- ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
irg_data->noreg_fp = be_pre_transform_node(irg_data->noreg_fp);
res, res_mode);
set_ia32_op_type(vfst, ia32_AddrModeD);
set_ia32_use_frame(vfst);
+ arch_add_irn_flags(vfst, arch_irn_flags_spill);
vfst_mem = new_r_Proj(vfst, mode_M, pn_ia32_fst_M);
projects / libfirm / blobdiff