#include "irprog_t.h"
#include "iredges_t.h"
#include "irgmod.h"
-#include "irvrfy.h"
#include "ircons.h"
#include "irgwalk.h"
#include "irprintf.h"
#include "irdom.h"
#include "error.h"
#include "array_t.h"
-#include "height.h"
+#include "heights.h"
#include "../benode.h"
#include "../besched.h"
#define DFP_INTMAX "9223372036854775807"
#define ULL_BIAS "18446744073709551616"
-#define ENT_SFP_SIGN ".LC_ia32_sfp_sign"
-#define ENT_DFP_SIGN ".LC_ia32_dfp_sign"
-#define ENT_SFP_ABS ".LC_ia32_sfp_abs"
-#define ENT_DFP_ABS ".LC_ia32_dfp_abs"
-#define ENT_ULL_BIAS ".LC_ia32_ull_bias"
+#define ENT_SFP_SIGN "C_ia32_sfp_sign"
+#define ENT_DFP_SIGN "C_ia32_dfp_sign"
+#define ENT_SFP_ABS "C_ia32_sfp_abs"
+#define ENT_DFP_ABS "C_ia32_dfp_abs"
+#define ENT_ULL_BIAS "C_ia32_ull_bias"
-#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
+#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static ir_node *initial_fpcw = NULL;
-int no_pic_adjust;
+int ia32_no_pic_adjust;
typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
*/
static bool is_simple_x87_Const(ir_node *node)
{
- tarval *tv = get_Const_tarval(node);
+ ir_tarval *tv = get_Const_tarval(node);
if (tarval_is_null(tv) || tarval_is_one(tv))
return true;
*/
static bool is_simple_sse_Const(ir_node *node)
{
- tarval *tv = get_Const_tarval(node);
- ir_mode *mode = get_tarval_mode(tv);
+ ir_tarval *tv = get_Const_tarval(node);
+ ir_mode *mode = get_tarval_mode(tv);
if (mode == mode_F)
return true;
return false;
}
+/**
+ * return NoREG or pic_base in case of PIC.
+ * This is necessary as base address for newly created symbols
+ */
+static ir_node *get_symconst_base(void)
+{
+ ir_graph *irg = current_ir_graph;
+
+ if (be_get_irg_options(irg)->pic) {
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ return arch_env->impl->get_pic_base(irg);
+ }
+
+ return noreg_GP;
+}
+
/**
* Transforms a Const.
*/
if (mode_is_float(mode)) {
ir_node *res = NULL;
ir_node *load;
+ ir_node *base;
ir_entity *floatent;
if (ia32_cg_config.use_sse2) {
- tarval *tv = get_Const_tarval(node);
+ ir_tarval *tv = get_Const_tarval(node);
if (tarval_is_null(tv)) {
load = new_bd_ia32_xZero(dbgi, block);
set_ia32_ls_mode(load, mode);
}
}
#endif /* CONSTRUCT_SSE_CONST */
- floatent = create_float_const_entity(node);
+ floatent = ia32_create_float_const_entity(node);
- load = new_bd_ia32_xLoad(dbgi, block, noreg_GP, noreg_GP, nomem, mode);
+ base = get_symconst_base();
+ load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
+ mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
arch_irn_add_flags(load, arch_irn_flags_rematerializable);
- res = new_r_Proj(block, load, mode_xmm, pn_ia32_xLoad_res);
+ res = new_r_Proj(load, mode_xmm, pn_ia32_xLoad_res);
}
} else {
if (is_Const_null(node)) {
set_ia32_ls_mode(load, mode);
} else {
ir_mode *ls_mode;
+ ir_node *base;
- floatent = create_float_const_entity(node);
+ floatent = ia32_create_float_const_entity(node);
/* create_float_const_ent is smart and sometimes creates
smaller entities */
ls_mode = get_type_mode(get_entity_type(floatent));
-
- load = new_bd_ia32_vfld(dbgi, block, noreg_GP, noreg_GP, nomem,
+ base = get_symconst_base();
+ load = new_bd_ia32_vfld(dbgi, block, base, noreg_GP, nomem,
ls_mode);
set_ia32_op_type(load, ia32_AddrModeS);
set_ia32_am_sc(load, floatent);
arch_irn_add_flags(load, arch_irn_flags_rematerializable);
- res = new_r_Proj(block, load, mode_vfp, pn_ia32_vfld_res);
+ res = new_r_Proj(load, mode_vfp, pn_ia32_vfld_res);
}
}
#ifdef CONSTRUCT_SSE_CONST
be_dep_on_frame(load);
return res;
} else { /* non-float mode */
- ir_node *cnst;
- tarval *tv = get_Const_tarval(node);
- long val;
+ ir_node *cnst;
+ ir_tarval *tv = get_Const_tarval(node);
+ long val;
tv = tarval_convert_to(tv, mode_Iu);
};
static ir_entity *ent_cache[ia32_known_const_max];
- const char *ent_name, *cnst_str;
- ir_type *tp;
- ir_entity *ent;
- tarval *tv;
- ir_mode *mode;
+ const char *ent_name, *cnst_str;
+ ir_type *tp;
+ ir_entity *ent;
+ ir_tarval *tv;
+ ir_mode *mode;
ent_name = names[kct].ent_name;
if (! ent_cache[kct]) {
ent = new_entity(get_glob_type(), new_id_from_str(ent_name), tp);
set_entity_ld_ident(ent, get_entity_ident(ent));
- set_entity_visibility(ent, visibility_local);
- set_entity_variability(ent, variability_constant);
- set_entity_allocation(ent, allocation_static);
+ add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
+ set_entity_visibility(ent, ir_visibility_private);
if (kct == ia32_ULLBIAS) {
ir_initializer_t *initializer = create_initializer_compound(2);
set_initializer_compound_value(initializer, 0,
- create_initializer_tarval(get_tarval_null(mode)));
+ create_initializer_tarval(get_mode_null(mode)));
set_initializer_compound_value(initializer, 1,
create_initializer_tarval(tv));
return 0;
/* don't do AM if other node inputs depend on the load (via mem-proj) */
- if (other != NULL && prevents_AM(block, load, other))
+ if (other != NULL && ia32_prevents_AM(block, load, other))
return 0;
- if (other2 != NULL && prevents_AM(block, load, other2))
+ if (other2 != NULL && ia32_prevents_AM(block, load, other2))
return 0;
return 1;
{
/* construct load address */
memset(addr, 0, sizeof(addr[0]));
- ia32_create_address_mode(addr, ptr, 0);
+ ia32_create_address_mode(addr, ptr, ia32_create_am_normal);
addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
ir_node *mem;
ir_node *new_mem;
+ /* floating point immediates */
if (is_Const(node)) {
- ir_entity *entity = create_float_const_entity(node);
- addr->base = noreg_GP;
+ ir_entity *entity = ia32_create_float_const_entity(node);
+ addr->base = get_symconst_base();
addr->index = noreg_GP;
addr->mem = nomem;
addr->symconst_ent = entity;
return 0;
/* we only want to skip the conv when we're the only user
- * (not optimal but for now...)
- */
+ * (because this test is used in the context of address-mode selection
+ * and we don't want to use address mode for multiple users) */
if (get_irn_n_edges(node) > 1)
return 0;
get_mode_size_bits(dest_mode) <= get_mode_size_bits(src_mode);
}
-/* Skip all Down-Conv's on a given node and return the resulting node. */
+/** Skip all Down-Conv's on a given node and return the resulting node. */
ir_node *ia32_skip_downconv(ir_node *node)
{
while (is_downconv(node))
return node;
}
+static bool is_sameconv(ir_node *node)
+{
+ ir_mode *src_mode;
+ ir_mode *dest_mode;
+
+ if (!is_Conv(node))
+ return 0;
+
+ /* we only want to skip the conv when we're the only user
+ * (because this test is used in the context of address-mode selection
+ * and we don't want to use address mode for multiple users) */
+ if (get_irn_n_edges(node) > 1)
+ return 0;
+
+ src_mode = get_irn_mode(get_Conv_op(node));
+ dest_mode = get_irn_mode(node);
+ return
+ ia32_mode_needs_gp_reg(src_mode) &&
+ ia32_mode_needs_gp_reg(dest_mode) &&
+ get_mode_size_bits(dest_mode) == get_mode_size_bits(src_mode);
+}
+
+/** Skip all signedness convs */
+static ir_node *ia32_skip_sameconv(ir_node *node)
+{
+ while (is_sameconv(node))
+ node = get_Conv_op(node);
+
+ return node;
+}
+
static ir_node *create_upconv(ir_node *node, ir_node *orig_node)
{
ir_mode *mode = get_irn_mode(node);
if (op1 != NULL) {
op1 = ia32_skip_downconv(op1);
}
+ } else {
+ op2 = ia32_skip_sameconv(op2);
+ if (op1 != NULL) {
+ op1 = ia32_skip_sameconv(op1);
+ }
}
/* match immediates. firm nodes are normalized: constants are always on the
* op2 input */
new_op2 = NULL;
if (!(flags & match_try_am) && use_immediate) {
- new_op2 = try_create_Immediate(op2, 0);
+ new_op2 = ia32_try_create_Immediate(op2, 0);
}
if (new_op2 == NULL &&
use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
- build_address(am, op2, 0);
+ build_address(am, op2, ia32_create_am_normal);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (mode_is_float(mode)) {
- new_op2 = ia32_new_NoReg_vfp(env_cg);
+ new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
} else {
new_op2 = noreg_GP;
}
use_am &&
ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
ir_node *noreg;
- build_address(am, op1, 0);
+ build_address(am, op1, ia32_create_am_normal);
if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_vfp(env_cg);
+ noreg = ia32_new_NoReg_vfp(current_ir_graph);
} else {
noreg = noreg_GP;
}
if (mode != mode_T) {
set_irn_mode(node, mode_T);
- return new_rd_Proj(NULL, get_nodes_block(node), node, mode, pn_ia32_res);
+ return new_rd_Proj(NULL, node, mode, pn_ia32_res);
} else {
return node;
}
n_ia32_l_binop_right, /**< ia32 right input */
n_ia32_l_binop_eflags /**< ia32 eflags input */
};
-COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
-COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
-COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
-COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
-COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
-COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags)
/**
* Construct a binary operation which also consumes the eflags.
if (initial_fpcw != NULL)
return initial_fpcw;
- fpcw = be_abi_get_ignore_irn(env_cg->birg->abi,
- &ia32_fp_cw_regs[REG_FPCW]);
+ fpcw = be_abi_get_ignore_irn(be_get_irg_abi(current_ir_graph),
+ &ia32_registers[REG_FPCW]);
initial_fpcw = be_transform_node(fpcw);
return initial_fpcw;
return new_node;
}
-static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
+static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
ia32_address_t *addr)
{
ir_node *base, *index, *res;
*/
static ir_node *gen_Mulh(ir_node *node)
{
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *op1 = get_Mulh_left(node);
- ir_node *op2 = get_Mulh_right(node);
- ir_mode *mode = get_irn_mode(node);
- ir_node *new_node;
- ir_node *proj_res_high;
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *op1 = get_Mulh_left(node);
+ ir_node *op2 = get_Mulh_right(node);
+ ir_mode *mode = get_irn_mode(node);
+ ir_node *new_node;
+ ir_node *proj_res_high;
if (get_mode_size_bits(mode) != 32) {
panic("Mulh without 32bit size not supported in ia32 backend (%+F)", node);
if (mode_is_signed(mode)) {
new_node = gen_binop(node, op1, op2, new_bd_ia32_IMul1OP, match_commutative | match_am);
- proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
+ proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_IMul1OP_res_high);
} else {
new_node = gen_binop(node, op1, op2, new_bd_ia32_Mul, match_commutative | match_am);
- proj_res_high = new_rd_Proj(dbgi, new_block, new_node, mode_Iu, pn_ia32_Mul_res_high);
+ proj_res_high = new_rd_Proj(dbgi, new_node, mode_Iu, pn_ia32_Mul_res_high);
}
return proj_res_high;
}
/* is it a zero extension? */
if (is_Const(op2)) {
- tarval *tv = get_Const_tarval(op2);
- long v = get_tarval_long(tv);
+ ir_tarval *tv = get_Const_tarval(op2);
+ long v = get_tarval_long(tv);
if (v == 0xFF || v == 0xFFFF) {
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *right = get_Shrs_right(node);
if (is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
- long val = get_tarval_long(tv);
+ ir_tarval *tv = get_Const_tarval(right);
+ long val = get_tarval_long(tv);
if (val == 31) {
/* this is a sign extension */
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *shl_left = get_Shl_left(left);
ir_node *shl_right = get_Shl_right(left);
if (is_Const(shl_right)) {
- tarval *tv1 = get_Const_tarval(right);
- tarval *tv2 = get_Const_tarval(shl_right);
+ ir_tarval *tv1 = get_Const_tarval(right);
+ ir_tarval *tv2 = get_Const_tarval(shl_right);
if (tv1 == tv2 && tarval_is_long(tv1)) {
long val = get_tarval_long(tv1);
if (val == 16 || val == 24) {
*/
static ir_node *gen_Rotl(ir_node *node)
{
- ir_node *rotate = NULL;
ir_node *op1 = get_Rotl_left(node);
ir_node *op2 = get_Rotl_right(node);
- /* Firm has only RotL, so we are looking for a right (op2)
- operand "-e+mode_size_bits" (it's an already modified "mode_size_bits-e",
- that means we can create a RotR instead of an Add and a RotL */
-
- if (is_Add(op2)) {
- ir_node *add = op2;
- ir_node *left = get_Add_left(add);
- ir_node *right = get_Add_right(add);
- if (is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
- ir_mode *mode = get_irn_mode(node);
- long bits = get_mode_size_bits(mode);
-
- if (is_Minus(left) &&
- tarval_is_long(tv) &&
- get_tarval_long(tv) == bits &&
- bits == 32)
- {
- DB((dbg, LEVEL_1, "RotL into RotR ... "));
- rotate = gen_Ror(node, op1, get_Minus_op(left));
- }
- }
- }
-
- if (rotate == NULL) {
- rotate = gen_Rol(node, op1, op2);
+ if (is_Minus(op2)) {
+ return gen_Ror(node, op1, get_Minus_op(op2));
}
- return rotate;
+ return gen_Rol(node, op1, op2);
}
/* TODO: non-optimal... if we have many xXors, then we should
* rather create a load for the const and use that instead of
* several AM nodes... */
- ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
+ ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph);
- new_node = new_bd_ia32_xXor(dbgi, block, noreg_GP, noreg_GP,
- nomem, new_op, noreg_xmm);
+ new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
+ noreg_GP, nomem, new_op, noreg_xmm);
size = get_mode_size_bits(mode);
ent = ia32_gen_fp_known_const(size == 32 ? ia32_SSIGN : ia32_DSIGN);
return gen_unop(node, op, new_bd_ia32_Not, match_mode_neutral);
}
-
-
-/**
- * Transforms an Abs node.
- *
- * @return The created ia32 Abs node
- */
-static ir_node *gen_Abs(ir_node *node)
+static ir_node *create_abs(dbg_info *dbgi, ir_node *block, ir_node *op,
+ bool negate, ir_node *node)
{
- ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
- ir_node *op = get_Abs_op(node);
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_mode *mode = get_irn_mode(node);
+ ir_mode *mode = get_irn_mode(op);
ir_node *new_op;
ir_node *new_node;
int size;
new_op = be_transform_node(op);
if (ia32_cg_config.use_sse2) {
- ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
- new_node = new_bd_ia32_xAnd(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, new_op, noreg_fp);
+ ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
+ new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
+ noreg_GP, nomem, new_op, noreg_fp);
size = get_mode_size_bits(mode);
ent = ia32_gen_fp_known_const(size == 32 ? ia32_SABS : ia32_DABS);
set_ia32_op_type(new_node, ia32_AddrModeS);
set_ia32_ls_mode(new_node, mode);
+
+ /* TODO, implement -Abs case */
+ assert(!negate);
} else {
new_node = new_bd_ia32_vfabs(dbgi, new_block, new_op);
SET_IA32_ORIG_NODE(new_node, node);
+ if (negate) {
+ new_node = new_bd_ia32_vfchs(dbgi, new_block, new_node);
+ SET_IA32_ORIG_NODE(new_node, node);
+ }
}
} else {
- ir_node *xor, *sign_extension;
+ ir_node *xorn;
+ ir_node *sign_extension;
if (get_mode_size_bits(mode) == 32) {
new_op = be_transform_node(op);
sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
- xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
+ xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
nomem, new_op, sign_extension);
- SET_IA32_ORIG_NODE(xor, node);
+ SET_IA32_ORIG_NODE(xorn, node);
- new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, xor, sign_extension);
+ if (negate) {
+ new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
+ nomem, sign_extension, xorn);
+ } else {
+ new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
+ nomem, xorn, sign_extension);
+ }
SET_IA32_ORIG_NODE(new_node, node);
}
* @param node the node to transform
* @param pnc_out the compare mode to use
*/
-static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
+static ir_node *get_flags_node(ir_node *node, int *pnc_out)
{
ir_node *flags;
ir_node *new_op;
if (is_Proj(node)) {
ir_node *pred = get_Proj_pred(node);
if (is_Cmp(pred)) {
- pn_Cmp pnc = get_Proj_proj(node);
+ int pnc = get_Proj_pn_cmp(node);
if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
ir_node *l = get_Cmp_left(pred);
ir_node *r = get_Cmp_right(pred);
}
}
}
- flags = be_transform_node(pred);
+ /* add ia32 compare flags */
+ {
+ ir_node *l = get_Cmp_left(pred);
+ ir_mode *mode = get_irn_mode(l);
+ if (mode_is_float(mode))
+ pnc |= ia32_pn_Cmp_float;
+ else if (! mode_is_signed(mode))
+ pnc |= ia32_pn_Cmp_unsigned;
+ }
*pnc_out = pnc;
+ flags = be_transform_node(pred);
return flags;
}
}
ir_node *index;
dbg_info *dbgi = get_irn_dbg_info(node);
ir_mode *mode = get_Load_mode(node);
- ir_mode *res_mode;
ir_node *new_node;
ia32_address_t addr;
/* construct load address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
base = addr.base;
index = addr.index;
if (ia32_cg_config.use_sse2) {
new_node = new_bd_ia32_xLoad(dbgi, block, base, index, new_mem,
mode);
- res_mode = mode_xmm;
} else {
new_node = new_bd_ia32_vfld(dbgi, block, base, index, new_mem,
mode);
- res_mode = mode_vfp;
}
} else {
assert(mode != mode_b);
} else {
new_node = new_bd_ia32_Load(dbgi, block, base, index, new_mem);
}
- res_mode = mode_Iu;
}
set_irn_pinned(new_node, get_irn_pinned(node));
set_address(new_node, &addr);
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
- && pn_ia32_vfld_res == pn_ia32_Load_res
- && pn_ia32_Load_res == pn_ia32_res);
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
+ && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ && (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
}
/* don't do AM if other node inputs depend on the load (via mem-proj) */
if (other != NULL &&
get_nodes_block(other) == block &&
- heights_reachable_in_block(heights, other, load)) {
+ heights_reachable_in_block(ia32_heights, other, load)) {
return 0;
}
- if (prevents_AM(block, load, mem))
+ if (ia32_prevents_AM(block, load, mem))
return 0;
/* Store should be attached to the load via mem */
- assert(heights_reachable_in_block(heights, mem, load));
+ assert(heights_reachable_in_block(ia32_heights, mem, load));
return 1;
}
return new_node;
}
+static int ia32_get_negated_pnc(int pnc)
+{
+ ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
+ return get_negated_pnc(pnc, mode);
+}
+
static ir_node *try_create_SetMem(ir_node *node, ir_node *ptr, ir_node *mem)
{
ir_mode *mode = get_irn_mode(node);
ir_node *mux_true = get_Mux_true(node);
ir_node *mux_false = get_Mux_false(node);
ir_node *cond;
- ir_node *new_mem;
dbg_info *dbgi;
ir_node *block;
ir_node *new_block;
ir_node *flags;
ir_node *new_node;
bool negated;
- pn_Cmp pnc;
+ int pnc;
ia32_address_t addr;
if (get_mode_size_bits(mode) != 8)
if (pnc & ia32_pn_Cmp_float)
return NULL;
if (negated)
- pnc = get_negated_pnc(pnc, pnc & ia32_pn_Cmp_float ? mode_F : mode_Is);
+ pnc = ia32_get_negated_pnc(pnc);
build_address_ptr(&addr, ptr, mem);
dbgi = get_irn_dbg_info(node);
block = get_nodes_block(node);
new_block = be_transform_node(block);
- new_mem = be_transform_node(mem);
new_node = new_bd_ia32_SetccMem(dbgi, new_block, addr.base,
addr.index, addr.mem, flags, pnc);
set_address(new_node, &addr);
{
ir_mode *mode = get_irn_mode(cns);
unsigned size = get_mode_size_bytes(mode);
- tarval *tv = get_Const_tarval(cns);
+ ir_tarval *tv = get_Const_tarval(cns);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_node *ptr = get_Store_ptr(node);
/* Note: fisttp ALWAYS pop the tos. We have to ensure here that the value is copied
if other users exists */
ir_node *vfisttp = new_bd_ia32_vfisttp(dbgi, block, base, index, mem, val);
- ir_node *value = new_r_Proj(block, vfisttp, mode_E, pn_ia32_vfisttp_res);
+ ir_node *value = new_r_Proj(vfisttp, mode_E, pn_ia32_vfisttp_res);
be_new_Keep(block, 1, &value);
- new_node = new_r_Proj(block, vfisttp, mode_M, pn_ia32_vfisttp_M);
+ new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M);
*fist = vfisttp;
} else {
- ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
+ ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
/* do a fist */
new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
/* construct store address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
if (addr.base == NULL) {
addr.base = noreg_GP;
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *sel = get_Cond_selector(node);
+ ir_node *sel = get_Cond_selector(node);
ir_mode *sel_mode = get_irn_mode(sel);
ir_node *flags = NULL;
ir_node *new_node;
- pn_Cmp pnc;
+ int pnc;
if (sel_mode != mode_b) {
return create_Switch(node);
/** we can only have eq and lg projs */
foreach_out_edge(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
- pn_Cmp pnc = get_Proj_proj(proj);
+ pn_Cmp pnc = get_Proj_pn_cmp(proj);
if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
return false;
}
}
static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
- pn_Cmp pnc)
+ int pnc)
{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
match_arguments(&am, block, val_false, val_true, flags,
match_commutative | match_am | match_16bit_am | match_mode_neutral);
+ if (am.ins_permuted)
+ pnc = ia32_get_negated_pnc(pnc);
+
new_node = new_bd_ia32_CMovcc(dbgi, new_block, addr->base, addr->index,
addr->mem, am.new_op1, am.new_op2, new_flags,
- am.ins_permuted, pnc);
+ pnc);
set_am_attributes(new_node, &am);
SET_IA32_ORIG_NODE(new_node, node);
* Creates a ia32 Setcc instruction.
*/
static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
- ir_node *flags, pn_Cmp pnc, ir_node *orig_node)
+ ir_node *flags, int pnc,
+ ir_node *orig_node)
{
ir_mode *mode = get_irn_mode(orig_node);
ir_node *new_node;
/**
* Create instruction for an unsigned Difference or Zero.
*/
-static ir_node *create_Doz(ir_node *psi, ir_node *a, ir_node *b)
+static ir_node *create_doz(ir_node *psi, ir_node *a, ir_node *b)
{
- ir_mode *mode = get_irn_mode(psi);
- ir_node *new_node, *sub, *sbb, *eflags, *block;
+ ir_mode *mode = get_irn_mode(psi);
+ ir_node *new_node;
+ ir_node *sub;
+ ir_node *sbb;
+ ir_node *notn;
+ ir_node *eflags;
+ ir_node *block;
dbg_info *dbgi;
} else {
sub = new_node;
set_irn_mode(sub, mode_T);
- new_node = new_rd_Proj(NULL, block, sub, mode, pn_ia32_res);
+ new_node = new_rd_Proj(NULL, sub, mode, pn_ia32_res);
}
- eflags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags);
+ eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
- dbgi = get_irn_dbg_info(psi);
- sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
+ dbgi = get_irn_dbg_info(psi);
+ sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
+ notn = new_bd_ia32_Not(dbgi, block, sbb);
- new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, sbb);
+ new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
set_ia32_commutative(new_node);
return new_node;
}
* @param new_mode IN/OUT for the mode of the constants, if NULL
* smallest possible mode will be used
*/
-static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode) {
+static ir_entity *ia32_create_const_array(ir_node *c0, ir_node *c1, ir_mode **new_mode)
+{
ir_entity *ent;
ir_mode *mode = *new_mode;
ir_type *tp;
ir_initializer_t *initializer;
- tarval *tv0 = get_Const_tarval(c0);
- tarval *tv1 = get_Const_tarval(c1);
+ ir_tarval *tv0 = get_Const_tarval(c0);
+ ir_tarval *tv1 = get_Const_tarval(c1);
if (mode == NULL) {
/* detect the best mode for the constants */
tp = ia32_create_float_type(mode, 4);
tp = ia32_create_float_array(tp);
- ent = new_entity(get_glob_type(), ia32_unique_id(".LC%u"), tp);
+ ent = new_entity(get_glob_type(), id_unique("C%u"), tp);
set_entity_ld_ident(ent, get_entity_ident(ent));
- set_entity_visibility(ent, visibility_local);
- set_entity_variability(ent, variability_constant);
- set_entity_allocation(ent, allocation_static);
+ set_entity_visibility(ent, ir_visibility_private);
+ add_entity_linkage(ent, IR_LINKAGE_CONSTANT);
initializer = create_initializer_compound(2);
return ent;
}
+/**
+ * Possible transformations for creating a Setcc.
+ */
+enum setcc_transform_insn {
+ SETCC_TR_ADD,
+ SETCC_TR_ADDxx,
+ SETCC_TR_LEA,
+ SETCC_TR_LEAxx,
+ SETCC_TR_SHL,
+ SETCC_TR_NEG,
+ SETCC_TR_NOT,
+ SETCC_TR_AND,
+ SETCC_TR_SET,
+ SETCC_TR_SBB,
+};
+
+typedef struct setcc_transform {
+ unsigned num_steps;
+ int pnc;
+ struct {
+ enum setcc_transform_insn transform;
+ long val;
+ int scale;
+ } steps[4];
+} setcc_transform_t;
+
+/**
+ * Setcc can only handle 0 and 1 result.
+ * Find a transformation that creates 0 and 1 from
+ * tv_t and tv_f.
+ */
+static void find_const_transform(int pnc, ir_tarval *t, ir_tarval *f,
+ setcc_transform_t *res)
+{
+ unsigned step = 0;
+
+ res->num_steps = 0;
+
+ if (tarval_is_null(t)) {
+ ir_tarval *tmp = t;
+ t = f;
+ f = tmp;
+ pnc = ia32_get_negated_pnc(pnc);
+ } else if (tarval_cmp(t, f) == pn_Cmp_Lt) {
+ // now, t is the bigger one
+ ir_tarval *tmp = t;
+ t = f;
+ f = tmp;
+ pnc = ia32_get_negated_pnc(pnc);
+ }
+ res->pnc = pnc;
+
+ if (! tarval_is_null(f)) {
+ ir_tarval *t_sub = tarval_sub(t, f, NULL);
+
+ t = t_sub;
+ res->steps[step].transform = SETCC_TR_ADD;
+
+ if (t == tarval_bad)
+ panic("constant subtract failed");
+ if (! tarval_is_long(f))
+ panic("tarval is not long");
+
+ res->steps[step].val = get_tarval_long(f);
+ ++step;
+ f = tarval_sub(f, f, NULL);
+ assert(tarval_is_null(f));
+ }
+
+ if (tarval_is_one(t)) {
+ res->steps[step].transform = SETCC_TR_SET;
+ res->num_steps = ++step;
+ return;
+ }
+
+ if (tarval_is_minus_one(t)) {
+ res->steps[step].transform = SETCC_TR_NEG;
+ ++step;
+ res->steps[step].transform = SETCC_TR_SET;
+ res->num_steps = ++step;
+ return;
+ }
+ if (tarval_is_long(t)) {
+ long v = get_tarval_long(t);
+
+ res->steps[step].val = 0;
+ switch (v) {
+ case 9:
+ if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
+ --step;
+ res->steps[step].transform = SETCC_TR_LEAxx;
+ res->steps[step].scale = 3; /* (a << 3) + a */
+ break;
+ case 8:
+ if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
+ --step;
+ res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
+ res->steps[step].scale = 3; /* (a << 3) */
+ break;
+ case 5:
+ if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
+ --step;
+ res->steps[step].transform = SETCC_TR_LEAxx;
+ res->steps[step].scale = 2; /* (a << 2) + a */
+ break;
+ case 4:
+ if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
+ --step;
+ res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
+ res->steps[step].scale = 2; /* (a << 2) */
+ break;
+ case 3:
+ if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
+ --step;
+ res->steps[step].transform = SETCC_TR_LEAxx;
+ res->steps[step].scale = 1; /* (a << 1) + a */
+ break;
+ case 2:
+ if (step > 0 && res->steps[step - 1].transform == SETCC_TR_ADD)
+ --step;
+ res->steps[step].transform = res->steps[step].val == 0 ? SETCC_TR_SHL : SETCC_TR_LEA;
+ res->steps[step].scale = 1; /* (a << 1) */
+ break;
+ case 1:
+ res->num_steps = step;
+ return;
+ default:
+ if (! tarval_is_single_bit(t)) {
+ res->steps[step].transform = SETCC_TR_AND;
+ res->steps[step].val = v;
+ ++step;
+ res->steps[step].transform = SETCC_TR_NEG;
+ } else {
+ int v = get_tarval_lowest_bit(t);
+ assert(v >= 0);
+
+ res->steps[step].transform = SETCC_TR_SHL;
+ res->steps[step].scale = v;
+ }
+ }
+ ++step;
+ res->steps[step].transform = SETCC_TR_SET;
+ res->num_steps = ++step;
+ return;
+ }
+ panic("tarval is not long");
+}
+
/**
* Transforms a Mux node into some code sequence.
*
*/
static ir_node *gen_Mux(ir_node *node)
{
- dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *block = get_nodes_block(node);
- ir_node *new_block = be_transform_node(block);
- ir_node *mux_true = get_Mux_true(node);
- ir_node *mux_false = get_Mux_false(node);
- ir_node *cond = get_Mux_sel(node);
- ir_mode *mode = get_irn_mode(node);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_node *block = get_nodes_block(node);
+ ir_node *new_block = be_transform_node(block);
+ ir_node *mux_true = get_Mux_true(node);
+ ir_node *mux_false = get_Mux_false(node);
+ ir_node *cond = get_Mux_sel(node);
+ ir_mode *mode = get_irn_mode(node);
ir_node *flags;
ir_node *new_node;
- pn_Cmp pnc;
+ int is_abs;
+ int pnc;
assert(get_irn_mode(cond) == mode_b);
+ is_abs = be_mux_is_abs(cond, mux_true, mux_false);
+ if (is_abs != 0) {
+ return create_abs(dbgi, block, be_get_abs_op(cond), is_abs < 0, node);
+ }
+
/* Note: a Mux node uses a Load two times IFF it's used in the compare AND in the result */
if (mode_is_float(mode)) {
ir_node *cmp = get_Proj_pred(cond);
ir_node *cmp_left = get_Cmp_left(cmp);
ir_node *cmp_right = get_Cmp_right(cmp);
- pn_Cmp pnc = get_Proj_proj(cond);
+ int pnc = get_Proj_proj(cond);
if (ia32_cg_config.use_sse2) {
if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
}
}
}
+
if (is_Const(mux_true) && is_Const(mux_false)) {
ia32_address_mode_t am;
ir_node *load;
}
am.ls_mode = new_mode;
- am.addr.base = noreg_GP;
+ am.addr.base = get_symconst_base();
am.addr.index = new_node;
am.addr.mem = nomem;
am.addr.offset = 0;
load = new_bd_ia32_vfld(dbgi, block, am.addr.base, am.addr.index, am.addr.mem, new_mode);
set_am_attributes(load, &am);
- return new_rd_Proj(NULL, block, load, mode_vfp, pn_ia32_res);
+ return new_rd_Proj(NULL, load, mode_vfp, pn_ia32_res);
}
panic("cannot transform floating point Mux");
if (is_Proj(cond)) {
ir_node *cmp = get_Proj_pred(cond);
if (is_Cmp(cmp)) {
- ir_node *cmp_left = get_Cmp_left(cmp);
- ir_node *cmp_right = get_Cmp_right(cmp);
- pn_Cmp pnc = get_Proj_proj(cond);
-
- /* check for unsigned Doz first */
- if ((pnc & pn_Cmp_Gt) && !mode_is_signed(mode) &&
- is_Const_0(mux_false) && is_Sub(mux_true) &&
- get_Sub_left(mux_true) == cmp_left && get_Sub_right(mux_true) == cmp_right) {
- /* Mux(a >=u b, a - b, 0) unsigned Doz */
- return create_Doz(node, cmp_left, cmp_right);
- } else if ((pnc & pn_Cmp_Lt) && !mode_is_signed(mode) &&
- is_Const_0(mux_true) && is_Sub(mux_false) &&
- get_Sub_left(mux_false) == cmp_left && get_Sub_right(mux_false) == cmp_right) {
- /* Mux(a <=u b, 0, a - b) unsigned Doz */
- return create_Doz(node, cmp_left, cmp_right);
+ ir_node *cmp_left = get_Cmp_left(cmp);
+ ir_node *cmp_right = get_Cmp_right(cmp);
+ ir_node *val_true = mux_true;
+ ir_node *val_false = mux_false;
+ int pnc = get_Proj_proj(cond);
+
+ if (is_Const(val_true) && is_Const_null(val_true)) {
+ ir_node *tmp = val_false;
+ val_false = val_true;
+ val_true = tmp;
+ pnc = ia32_get_negated_pnc(pnc);
+ }
+ if (is_Const_0(val_false) && is_Sub(val_true)) {
+ if ((pnc == pn_Cmp_Gt || pnc == pn_Cmp_Ge)
+ && get_Sub_left(val_true) == cmp_left
+ && get_Sub_right(val_true) == cmp_right) {
+ return create_doz(node, cmp_left, cmp_right);
+ }
+ if ((pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le)
+ && get_Sub_left(val_true) == cmp_right
+ && get_Sub_right(val_true) == cmp_left) {
+ return create_doz(node, cmp_right, cmp_left);
+ }
}
}
}
if (is_Const(mux_true) && is_Const(mux_false)) {
/* both are const, good */
- if (is_Const_1(mux_true) && is_Const_0(mux_false)) {
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
- } else if (is_Const_0(mux_true) && is_Const_1(mux_false)) {
- pnc = get_negated_pnc(pnc, pnc & ia32_pn_Cmp_float ? mode_F : mode_Is);
- new_node = create_set_32bit(dbgi, new_block, flags, pnc, node);
- } else {
- /* Not that simple. */
- goto need_cmov;
+ ir_tarval *tv_true = get_Const_tarval(mux_true);
+ ir_tarval *tv_false = get_Const_tarval(mux_false);
+ setcc_transform_t res;
+ int step;
+
+ find_const_transform(pnc, tv_true, tv_false, &res);
+ new_node = node;
+ for (step = (int)res.num_steps - 1; step >= 0; --step) {
+ ir_node *imm;
+
+ switch (res.steps[step].transform) {
+ case SETCC_TR_ADD:
+ imm = ia32_immediate_from_long(res.steps[step].val);
+ new_node = new_bd_ia32_Add(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
+ break;
+ case SETCC_TR_ADDxx:
+ new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
+ break;
+ case SETCC_TR_LEA:
+ new_node = new_bd_ia32_Lea(dbgi, new_block, noreg_GP, new_node);
+ set_ia32_am_scale(new_node, res.steps[step].scale);
+ set_ia32_am_offs_int(new_node, res.steps[step].val);
+ break;
+ case SETCC_TR_LEAxx:
+ new_node = new_bd_ia32_Lea(dbgi, new_block, new_node, new_node);
+ set_ia32_am_scale(new_node, res.steps[step].scale);
+ set_ia32_am_offs_int(new_node, res.steps[step].val);
+ break;
+ case SETCC_TR_SHL:
+ imm = ia32_immediate_from_long(res.steps[step].scale);
+ new_node = new_bd_ia32_Shl(dbgi, new_block, new_node, imm);
+ break;
+ case SETCC_TR_NEG:
+ new_node = new_bd_ia32_Neg(dbgi, new_block, new_node);
+ break;
+ case SETCC_TR_NOT:
+ new_node = new_bd_ia32_Not(dbgi, new_block, new_node);
+ break;
+ case SETCC_TR_AND:
+ imm = ia32_immediate_from_long(res.steps[step].val);
+ new_node = new_bd_ia32_And(dbgi, new_block, noreg_GP, noreg_GP, nomem, new_node, imm);
+ break;
+ case SETCC_TR_SET:
+ new_node = create_set_32bit(dbgi, new_block, flags, res.pnc, node);
+ break;
+ case SETCC_TR_SBB:
+ new_node = new_bd_ia32_Sbb0(dbgi, new_block, flags);
+ break;
+ default:
+ panic("unknown setcc transform");
+ }
}
} else {
-need_cmov:
new_node = create_CMov(node, cond, flags, pnc);
}
return new_node;
}
SET_IA32_ORIG_NODE(load, node);
- return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
+ return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
}
/**
set_ia32_op_type(load, ia32_AddrModeS);
SET_IA32_ORIG_NODE(load, node);
- new_node = new_r_Proj(block, load, mode_E, pn_ia32_vfld_res);
+ new_node = new_r_Proj(load, mode_E, pn_ia32_vfld_res);
return new_node;
}
ia32_address_t *addr = &am.addr;
fild = new_bd_ia32_vfild(dbgi, block, addr->base, addr->index, addr->mem);
- new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
+ new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
set_am_attributes(fild, &am);
SET_IA32_ORIG_NODE(fild, node);
set_ia32_op_type(fild, ia32_AddrModeS);
set_ia32_ls_mode(fild, store_mode);
- new_node = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
+ new_node = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
return new_node;
}
/* if fp_no_float_fold is not set then we assume that we
* don't have any float operations in a non
* mode_float_arithmetic mode and can skip strict upconvs */
- if (src_bits < tgt_bits
- && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) {
+ if (src_bits < tgt_bits) {
DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
return new_op;
} else {
static ir_node *create_immediate_or_transform(ir_node *node,
char immediate_constraint_type)
{
- ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
+ ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
if (new_node == NULL) {
new_node = be_transform_node(node);
}
set_ia32_op_type(fld, ia32_AddrModeS);
set_ia32_use_frame(fld);
- mproj = new_r_Proj(block, fld, mode_M, pn_ia32_vfld_M);
- fld = new_r_Proj(block, fld, mode_vfp, pn_ia32_vfld_res);
+ mproj = new_r_Proj(fld, mode_M, pn_ia32_vfld_M);
+ fld = new_r_Proj(fld, mode_vfp, pn_ia32_vfld_res);
/* create a new barrier */
arity = get_irn_arity(barrier);
new_barrier = new_ir_node(dbgi, irg, block,
get_irn_op(barrier), get_irn_mode(barrier),
arity, in);
- copy_node_attr(barrier, new_barrier);
+ copy_node_attr(irg, barrier, new_barrier);
be_duplicate_deps(barrier, new_barrier);
be_set_transformed_node(barrier, new_barrier);
* and fix this later */
phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
get_irn_in(node) + 1);
- copy_node_attr(node, phi);
+ copy_node_attr(irg, node, phi);
be_duplicate_deps(node, phi);
arch_set_out_register_req(phi, 0, req);
ir_node *sub, *res, *flags, *block;
res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
- new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
+ new_bd_ia32_Sub,
+ match_mode_neutral | match_am | match_immediate);
block = get_nodes_block(res);
if (! is_Proj(res)) {
sub = res;
set_irn_mode(sub, mode_T);
- res = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_res);
+ res = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_res);
} else {
sub = get_Proj_pred(res);
}
- flags = new_rd_Proj(NULL, block, sub, mode_Iu, pn_ia32_Sub_flags);
+ flags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
new_node = new_bd_ia32_Jcc(dbgi, block, flags, pn_Cmp_Lt | ia32_pn_Cmp_unsigned);
SET_IA32_ORIG_NODE(new_node, node);
} else {
match_mode_neutral);
if (is_Proj(lowered)) {
- lowered = get_Proj_pred(lowered);
+ lowered = get_Proj_pred(lowered);
} else {
assert(is_ia32_Add(lowered));
set_irn_mode(lowered, mode_T);
match_am | match_immediate | match_mode_neutral);
if (is_Proj(lowered)) {
- lowered = get_Proj_pred(lowered);
+ lowered = get_Proj_pred(lowered);
} else {
assert(is_ia32_Sub(lowered));
set_irn_mode(lowered, mode_T);
SET_IA32_ORIG_NODE(fild, node);
- res = new_r_Proj(block, fild, mode_vfp, pn_ia32_vfild_res);
+ res = new_r_Proj(fild, mode_vfp, pn_ia32_vfild_res);
if (! mode_is_signed(get_irn_mode(val_high))) {
ia32_address_mode_t am;
ir_node *count = ia32_create_Immediate(NULL, 0, 31);
ir_node *fadd;
- am.addr.base = noreg_GP;
+ am.addr.base = get_symconst_base();
am.addr.index = new_bd_ia32_Shr(dbgi, block, new_val_high, count);
am.addr.mem = nomem;
am.addr.offset = 0;
am.mem_proj = nomem;
am.op_type = ia32_AddrModeS;
am.new_op1 = res;
- am.new_op2 = ia32_new_NoReg_vfp(env_cg);
+ am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
am.pinned = op_pin_state_floats;
am.commutative = 1;
am.ins_permuted = 0;
set_am_attributes(fadd, &am);
set_irn_mode(fadd, mode_T);
- res = new_rd_Proj(NULL, block, fadd, mode_vfp, pn_ia32_res);
+ res = new_rd_Proj(NULL, fadd, mode_vfp, pn_ia32_res);
}
return res;
}
return mem;
}
-/**
- * the BAD transformer.
- */
-static ir_node *bad_transform(ir_node *node)
-{
- panic("No transform function for %+F available.", node);
- return NULL;
-}
-
static ir_node *gen_Proj_l_FloattoLL(ir_node *node)
{
ir_node *block = be_transform_node(get_nodes_block(node));
assert(pn == pn_ia32_l_FloattoLL_res_low);
}
- proj = new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
+ proj = new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
return proj;
}
*/
static ir_node *gen_Proj_be_AddSP(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
if (proj == pn_be_AddSP_sp) {
- ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
+ ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
pn_ia32_SubSP_stack);
- arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
return res;
} else if (proj == pn_be_AddSP_res) {
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu,
+ return new_rd_Proj(dbgi, new_pred, mode_Iu,
pn_ia32_SubSP_addr);
} else if (proj == pn_be_AddSP_M) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_SubSP_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_SubSP_M);
}
panic("No idea how to transform proj->AddSP");
*/
static ir_node *gen_Proj_be_SubSP(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
if (proj == pn_be_SubSP_sp) {
- ir_node *res = new_rd_Proj(dbgi, block, new_pred, mode_Iu,
+ ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
pn_ia32_AddSP_stack);
- arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
return res;
} else if (proj == pn_be_SubSP_M) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_AddSP_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M);
}
panic("No idea how to transform proj->SubSP");
*/
if (is_Load(pred) && proj == pn_Load_M && get_irn_n_edges(pred) > 1) {
ir_node *res;
- ir_node *old_block = get_nodes_block(node);
/* this is needed, because sometimes we have loops that are only
reachable through the ProjM */
be_enqueue_preds(node);
/* do it in 2 steps, to silence firm verifier */
- res = new_rd_Proj(dbgi, old_block, pred, mode_M, pn_Load_M);
+ res = new_rd_Proj(dbgi, pred, mode_M, pn_Load_M);
set_Proj_proj(res, pn_ia32_mem);
return res;
}
if (is_ia32_Load(new_pred)) {
switch (proj) {
case pn_Load_res:
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Load_res);
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Load_res);
case pn_Load_M:
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Load_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Load_M);
case pn_Load_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Load_X_exc);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Load_X_exc);
default:
break;
}
is_ia32_Conv_I2I8Bit(new_pred)) {
set_irn_mode(new_pred, mode_T);
if (proj == pn_Load_res) {
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_res);
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_res);
} else if (proj == pn_Load_M) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_mem);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_mem);
}
} else if (is_ia32_xLoad(new_pred)) {
switch (proj) {
case pn_Load_res:
- return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xLoad_res);
+ return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xLoad_res);
case pn_Load_M:
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xLoad_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xLoad_M);
case pn_Load_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_xLoad_X_exc);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_xLoad_X_exc);
default:
break;
}
} else if (is_ia32_vfld(new_pred)) {
switch (proj) {
case pn_Load_res:
- return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfld_res);
+ return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfld_res);
case pn_Load_M:
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfld_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfld_M);
case pn_Load_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Load_X_except:
/* This Load might raise an exception. Mark it. */
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_vfld_X_exc);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_vfld_X_exc);
default:
break;
}
if (proj != pn_Load_M) {
panic("internal error: transformed node not a Load");
}
- return new_rd_Proj(dbgi, block, new_pred, mode_M, 1);
+ return new_rd_Proj(dbgi, new_pred, mode_M, 1);
}
panic("No idea how to transform proj");
case iro_Div:
switch (proj) {
case pn_Div_M:
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
case pn_Div_res:
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
case pn_Div_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_Div_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
default:
break;
}
case iro_Mod:
switch (proj) {
case pn_Mod_M:
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
case pn_Mod_res:
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
case pn_Mod_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
default:
break;
}
case iro_DivMod:
switch (proj) {
case pn_DivMod_M:
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_Div_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_Div_M);
case pn_DivMod_res_div:
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_div_res);
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_div_res);
case pn_DivMod_res_mod:
- return new_rd_Proj(dbgi, block, new_pred, mode_Iu, pn_ia32_Div_mod_res);
+ return new_rd_Proj(dbgi, new_pred, mode_Iu, pn_ia32_Div_mod_res);
case pn_DivMod_X_regular:
return new_rd_Jmp(dbgi, block);
case pn_DivMod_X_except:
set_ia32_exc_label(new_pred, 1);
- return new_rd_Proj(dbgi, block, new_pred, mode_X, pn_ia32_Div_X_exc);
+ return new_rd_Proj(dbgi, new_pred, mode_X, pn_ia32_Div_X_exc);
default:
break;
}
*/
static ir_node *gen_Proj_CopyB(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
long proj = get_Proj_proj(node);
switch (proj) {
- case pn_CopyB_M_regular:
+ case pn_CopyB_M:
if (is_ia32_CopyB_i(new_pred)) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_i_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_i_M);
} else if (is_ia32_CopyB(new_pred)) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_CopyB_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_CopyB_M);
}
break;
default:
*/
static ir_node *gen_Proj_Quot(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
dbg_info *dbgi = get_irn_dbg_info(node);
switch (proj) {
case pn_Quot_M:
if (is_ia32_xDiv(new_pred)) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_xDiv_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_xDiv_M);
} else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, block, new_pred, mode_M, pn_ia32_vfdiv_M);
+ return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_vfdiv_M);
}
break;
case pn_Quot_res:
if (is_ia32_xDiv(new_pred)) {
- return new_rd_Proj(dbgi, block, new_pred, mode_xmm, pn_ia32_xDiv_res);
+ return new_rd_Proj(dbgi, new_pred, mode_xmm, pn_ia32_xDiv_res);
} else if (is_ia32_vfdiv(new_pred)) {
- return new_rd_Proj(dbgi, block, new_pred, mode_vfp, pn_ia32_vfdiv_res);
+ return new_rd_Proj(dbgi, new_pred, mode_vfp, pn_ia32_vfdiv_res);
}
break;
case pn_Quot_X_regular:
ir_mode *const res_mode = get_type_mode(res_type);
if (res_mode != NULL && mode_is_float(res_mode)) {
- env_cg->do_x87_sim = 1;
+ ir_graph *irg = current_ir_graph;
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ irg_data->do_x87_sim = 1;
}
}
assert(be_Call_get_entity(node) == NULL);
/* special case for PIC trampoline calls */
- old_no_pic_adjust = no_pic_adjust;
- no_pic_adjust = env_cg->birg->main_env->options->pic;
+ old_no_pic_adjust = ia32_no_pic_adjust;
+ ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic;
match_arguments(&am, src_block, NULL, src_ptr, src_mem,
match_am | match_immediate);
- no_pic_adjust = old_no_pic_adjust;
+ ia32_no_pic_adjust = old_no_pic_adjust;
i = get_irn_arity(node) - 1;
fpcw = be_transform_node(get_irn_n(node, i--));
assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
switch (*req->limited) {
- case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
- case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
- case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
+ case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
+ case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
+ case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
default: panic("Invalid GP register for register parameter");
}
}
/**
* Transform Builtin trap
*/
-static ir_node *gen_trap(ir_node *node) {
+static ir_node *gen_trap(ir_node *node)
+{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *mem = be_transform_node(get_Builtin_mem(node));
/**
* Transform Builtin debugbreak
*/
-static ir_node *gen_debugbreak(ir_node *node) {
+static ir_node *gen_debugbreak(ir_node *node)
+{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *mem = be_transform_node(get_Builtin_mem(node));
/**
* Transform Builtin return_address
*/
-static ir_node *gen_return_address(ir_node *node) {
- ir_node *param = get_Builtin_param(node, 0);
- ir_node *frame = get_Builtin_param(node, 1);
- dbg_info *dbgi = get_irn_dbg_info(node);
- tarval *tv = get_Const_tarval(param);
+static ir_node *gen_return_address(ir_node *node)
+{
+ ir_node *param = get_Builtin_param(node, 0);
+ ir_node *frame = get_Builtin_param(node, 1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_tarval *tv = get_Const_tarval(param);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
set_ia32_frame_ent(load, ia32_get_return_address_entity());
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
- && pn_ia32_vfld_res == pn_ia32_Load_res
- && pn_ia32_Load_res == pn_ia32_res);
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
+ && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ && (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_irn_add_flags(load, arch_irn_flags_rematerializable);
}
SET_IA32_ORIG_NODE(load, node);
- return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
+ return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
}
/**
* Transform Builtin frame_address
*/
-static ir_node *gen_frame_address(ir_node *node) {
- ir_node *param = get_Builtin_param(node, 0);
- ir_node *frame = get_Builtin_param(node, 1);
- dbg_info *dbgi = get_irn_dbg_info(node);
- tarval *tv = get_Const_tarval(param);
+static ir_node *gen_frame_address(ir_node *node)
+{
+ ir_node *param = get_Builtin_param(node, 0);
+ ir_node *frame = get_Builtin_param(node, 1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_tarval *tv = get_Const_tarval(param);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
}
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
- && pn_ia32_vfld_res == pn_ia32_Load_res
- && pn_ia32_Load_res == pn_ia32_res);
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
+ && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ && (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_irn_add_flags(load, arch_irn_flags_rematerializable);
}
SET_IA32_ORIG_NODE(load, node);
- return new_r_Proj(block, load, mode_Iu, pn_ia32_Load_res);
+ return new_r_Proj(load, mode_Iu, pn_ia32_Load_res);
}
/**
* Transform Builtin frame_address
*/
-static ir_node *gen_prefetch(ir_node *node) {
+static ir_node *gen_prefetch(ir_node *node)
+{
dbg_info *dbgi;
ir_node *ptr, *block, *mem, *base, *index;
ir_node *param, *new_node;
long rw, locality;
- tarval *tv;
+ ir_tarval *tv;
ia32_address_t addr;
if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
/* construct load address */
memset(&addr, 0, sizeof(addr));
ptr = get_Builtin_param(node, 0);
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
base = addr.base;
index = addr.index;
SET_IA32_ORIG_NODE(new_node, node);
be_dep_on_frame(new_node);
- return new_r_Proj(block, new_node, mode_M, pn_ia32_Prefetch_M);
+ return new_r_Proj(new_node, mode_M, pn_ia32_Prefetch_M);
}
/**
ir_node *real = skip_Proj(bsf);
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
- ir_node *flag, *set, *conv, *neg, *or;
+ ir_node *flag, *set, *conv, *neg, *orn;
/* bsf x */
if (get_irn_mode(real) != mode_T) {
set_irn_mode(real, mode_T);
- bsf = new_r_Proj(block, real, mode_Iu, pn_ia32_res);
+ bsf = new_r_Proj(real, mode_Iu, pn_ia32_res);
}
- flag = new_r_Proj(block, real, mode_b, pn_ia32_flags);
+ flag = new_r_Proj(real, mode_b, pn_ia32_flags);
/* sete */
set = new_bd_ia32_Setcc(dbgi, block, flag, pn_Cmp_Eq);
neg = new_bd_ia32_Neg(dbgi, block, conv);
/* or */
- or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
- set_ia32_commutative(or);
+ orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
+ set_ia32_commutative(orn);
/* add 1 */
- return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1));
+ return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, orn, ia32_create_Immediate(NULL, 0, 1));
}
/**
/**
* Transform builtin popcount
*/
-static ir_node *gen_popcount(ir_node *node) {
+static ir_node *gen_popcount(ir_node *node)
+{
ir_node *param = get_Builtin_param(node, 0);
dbg_info *dbgi = get_irn_dbg_info(node);
/**
* Transform builtin byte swap.
*/
-static ir_node *gen_bswap(ir_node *node) {
+static ir_node *gen_bswap(ir_node *node)
+{
ir_node *param = be_transform_node(get_Builtin_param(node, 0));
dbg_info *dbgi = get_irn_dbg_info(node);
/**
* Transform builtin outport.
*/
-static ir_node *gen_outport(ir_node *node) {
+static ir_node *gen_outport(ir_node *node)
+{
ir_node *port = create_immediate_or_transform(get_Builtin_param(node, 0), 0);
ir_node *oldv = get_Builtin_param(node, 1);
ir_mode *mode = get_irn_mode(oldv);
/**
* Transform builtin inport.
*/
-static ir_node *gen_inport(ir_node *node) {
+static ir_node *gen_inport(ir_node *node)
+{
ir_type *tp = get_Builtin_type(node);
ir_type *rstp = get_method_res_type(tp, 0);
ir_mode *mode = get_type_mode(rstp);
/**
* Transform a builtin inner trampoline
*/
-static ir_node *gen_inner_trampoline(ir_node *node) {
+static ir_node *gen_inner_trampoline(ir_node *node)
+{
ir_node *ptr = get_Builtin_param(node, 0);
ir_node *callee = get_Builtin_param(node, 1);
ir_node *env = be_transform_node(get_Builtin_param(node, 2));
/* construct store address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
if (addr.base == NULL) {
addr.base = noreg_GP;
/**
* Transform Builtin node.
*/
-static ir_node *gen_Builtin(ir_node *node) {
+static ir_node *gen_Builtin(ir_node *node)
+{
ir_builtin_kind kind = get_Builtin_kind(node);
switch (kind) {
/**
* Transform Proj(Builtin) node.
*/
-static ir_node *gen_Proj_Builtin(ir_node *proj) {
+static ir_node *gen_Proj_Builtin(ir_node *proj)
+{
ir_node *node = get_Proj_pred(proj);
ir_node *new_node = be_transform_node(node);
ir_builtin_kind kind = get_Builtin_kind(node);
return new_node;
case ir_bk_inport:
if (get_Proj_proj(proj) == pn_Builtin_1_result) {
- return new_r_Proj(get_nodes_block(new_node),
- new_node, get_irn_mode(proj), pn_ia32_Inport_res);
+ return new_r_Proj(new_node, get_irn_mode(proj), pn_ia32_Inport_res);
} else {
assert(get_Proj_proj(proj) == pn_Builtin_M);
- return new_r_Proj(get_nodes_block(new_node),
- new_node, mode_M, pn_ia32_Inport_M);
+ return new_r_Proj(new_node, mode_M, pn_ia32_Inport_M);
}
case ir_bk_inner_trampoline:
if (get_Proj_proj(proj) == pn_Builtin_1_result) {
*/
static ir_node *gen_Proj_be_Call(ir_node *node)
{
- ir_node *block = be_transform_node(get_nodes_block(node));
ir_node *call = get_Proj_pred(node);
ir_node *new_call = be_transform_node(call);
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *res;
if (proj == pn_be_Call_M_regular) {
- return new_rd_Proj(dbgi, block, new_call, mode_M, n_ia32_Call_mem);
+ return new_rd_Proj(dbgi, new_call, mode_M, n_ia32_Call_mem);
}
/* transform call modes */
if (mode_is_data(mode)) {
assert(i < n_outs);
}
- res = new_rd_Proj(dbgi, block, new_call, mode, proj);
+ res = new_rd_Proj(dbgi, new_call, mode, proj);
/* TODO arch_set_irn_register() only operates on Projs, need variant with index */
switch (proj) {
case pn_ia32_Call_stack:
- arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
break;
case pn_ia32_Call_fpcw:
- arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]);
+ arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
break;
}
*/
static ir_node *gen_Proj_Bound(ir_node *node)
{
- ir_node *new_node, *block;
+ ir_node *new_node;
ir_node *pred = get_Proj_pred(node);
switch (get_Proj_proj(node)) {
return be_transform_node(get_Bound_mem(pred));
case pn_Bound_X_regular:
new_node = be_transform_node(pred);
- block = get_nodes_block(new_node);
- return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_true);
+ return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_true);
case pn_Bound_X_except:
new_node = be_transform_node(pred);
- block = get_nodes_block(new_node);
- return new_r_Proj(block, new_node, mode_X, pn_ia32_Jcc_false);
+ return new_r_Proj(new_node, mode_X, pn_ia32_Jcc_false);
case pn_Bound_res:
return be_transform_node(get_Bound_index(pred));
default:
ir_mode *mode = get_irn_mode(node);
ir_node *pred = get_Proj_pred(node);
ir_node *new_pred = be_transform_node(pred);
- ir_node *block = get_nodes_block(new_pred);
long pos = get_Proj_proj(node);
if (mode == mode_M) {
panic("unexpected proj mode at ASM");
}
- return new_r_Proj(block, new_pred, mode, pos);
+ return new_r_Proj(new_pred, mode, pos);
}
/**
}
case pn_Start_P_tls:
- return gen_Proj_tls(node);
+ return ia32_gen_Proj_tls(node);
}
break;
ir_mode *mode = get_irn_mode(node);
if (ia32_mode_needs_gp_reg(mode)) {
ir_node *new_pred = be_transform_node(pred);
- ir_node *block = be_transform_node(get_nodes_block(node));
- ir_node *new_proj = new_r_Proj(block, new_pred,
- mode_Iu, get_Proj_proj(node));
+ ir_node *new_proj = new_r_Proj(new_pred, mode_Iu,
+ get_Proj_proj(node));
new_proj->node_nr = node->node_nr;
return new_proj;
}
static void register_transformers(void)
{
/* first clear the generic function pointer for all ops */
- clear_irp_opcodes_generic_func();
-
-#define GEN(a) { be_transform_func *func = gen_##a; op_##a->ops.generic = (op_func) func; }
-#define BAD(a) op_##a->ops.generic = (op_func)bad_transform
-
- GEN(Add);
- GEN(Sub);
- GEN(Mul);
- GEN(Mulh);
- GEN(And);
- GEN(Or);
- GEN(Eor);
-
- GEN(Shl);
- GEN(Shr);
- GEN(Shrs);
- GEN(Rotl);
-
- GEN(Quot);
-
- GEN(Div);
- GEN(Mod);
- GEN(DivMod);
-
- GEN(Minus);
- GEN(Conv);
- GEN(Abs);
- GEN(Not);
-
- GEN(Load);
- GEN(Store);
- GEN(Cond);
-
- GEN(Cmp);
- GEN(ASM);
- GEN(CopyB);
- GEN(Mux);
- GEN(Proj);
- GEN(Phi);
- GEN(Jmp);
- GEN(IJmp);
- GEN(Bound);
-
- /* transform ops from intrinsic lowering */
- GEN(ia32_l_Add);
- GEN(ia32_l_Adc);
- GEN(ia32_l_Mul);
- GEN(ia32_l_IMul);
- GEN(ia32_l_ShlDep);
- GEN(ia32_l_ShrDep);
- GEN(ia32_l_SarDep);
- GEN(ia32_l_ShlD);
- GEN(ia32_l_ShrD);
- GEN(ia32_l_Sub);
- GEN(ia32_l_Sbb);
- GEN(ia32_l_LLtoFloat);
- GEN(ia32_l_FloattoLL);
-
- GEN(Const);
- GEN(SymConst);
- GEN(Unknown);
-
- /* we should never see these nodes */
- BAD(Raise);
- BAD(Sel);
- BAD(InstOf);
- BAD(Cast);
- BAD(Free);
- BAD(Tuple);
- BAD(Id);
- //BAD(Bad);
- BAD(Confirm);
- BAD(Filter);
- BAD(CallBegin);
- BAD(EndReg);
- BAD(EndExcept);
-
- /* handle builtins */
- GEN(Builtin);
-
- /* handle generic backend nodes */
- GEN(be_FrameAddr);
- GEN(be_Call);
- GEN(be_IncSP);
- GEN(be_Return);
- GEN(be_AddSP);
- GEN(be_SubSP);
- GEN(be_Copy);
-
-#undef GEN
-#undef BAD
+ be_start_transform_setup();
+
+ be_set_transform_function(op_Add, gen_Add);
+ be_set_transform_function(op_And, gen_And);
+ be_set_transform_function(op_ASM, ia32_gen_ASM);
+ be_set_transform_function(op_be_AddSP, gen_be_AddSP);
+ be_set_transform_function(op_be_Call, gen_be_Call);
+ be_set_transform_function(op_be_Copy, gen_be_Copy);
+ be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr);
+ be_set_transform_function(op_be_IncSP, gen_be_IncSP);
+ be_set_transform_function(op_be_Return, gen_be_Return);
+ be_set_transform_function(op_be_SubSP, gen_be_SubSP);
+ be_set_transform_function(op_Bound, gen_Bound);
+ be_set_transform_function(op_Builtin, gen_Builtin);
+ be_set_transform_function(op_Cmp, gen_Cmp);
+ be_set_transform_function(op_Cond, gen_Cond);
+ be_set_transform_function(op_Const, gen_Const);
+ be_set_transform_function(op_Conv, gen_Conv);
+ be_set_transform_function(op_CopyB, ia32_gen_CopyB);
+ be_set_transform_function(op_Div, gen_Div);
+ be_set_transform_function(op_DivMod, gen_DivMod);
+ be_set_transform_function(op_Eor, gen_Eor);
+ be_set_transform_function(op_ia32_l_Adc, gen_ia32_l_Adc);
+ be_set_transform_function(op_ia32_l_Add, gen_ia32_l_Add);
+ be_set_transform_function(op_ia32_Leave, be_duplicate_node);
+ be_set_transform_function(op_ia32_l_FloattoLL, gen_ia32_l_FloattoLL);
+ be_set_transform_function(op_ia32_l_IMul, gen_ia32_l_IMul);
+ be_set_transform_function(op_ia32_l_LLtoFloat, gen_ia32_l_LLtoFloat);
+ be_set_transform_function(op_ia32_l_Mul, gen_ia32_l_Mul);
+ be_set_transform_function(op_ia32_l_SarDep, gen_ia32_l_SarDep);
+ be_set_transform_function(op_ia32_l_Sbb, gen_ia32_l_Sbb);
+ be_set_transform_function(op_ia32_l_ShlDep, gen_ia32_l_ShlDep);
+ be_set_transform_function(op_ia32_l_ShlD, gen_ia32_l_ShlD);
+ be_set_transform_function(op_ia32_l_ShrDep, gen_ia32_l_ShrDep);
+ be_set_transform_function(op_ia32_l_ShrD, gen_ia32_l_ShrD);
+ be_set_transform_function(op_ia32_l_Sub, gen_ia32_l_Sub);
+ be_set_transform_function(op_ia32_GetEIP, be_duplicate_node);
+ be_set_transform_function(op_ia32_Minus64Bit, be_duplicate_node);
+ be_set_transform_function(op_ia32_NoReg_GP, be_duplicate_node);
+ be_set_transform_function(op_ia32_NoReg_VFP, be_duplicate_node);
+ be_set_transform_function(op_ia32_NoReg_XMM, be_duplicate_node);
+ be_set_transform_function(op_ia32_PopEbp, be_duplicate_node);
+ be_set_transform_function(op_ia32_Push, be_duplicate_node);
+ be_set_transform_function(op_IJmp, gen_IJmp);
+ be_set_transform_function(op_Jmp, gen_Jmp);
+ be_set_transform_function(op_Load, gen_Load);
+ be_set_transform_function(op_Minus, gen_Minus);
+ be_set_transform_function(op_Mod, gen_Mod);
+ be_set_transform_function(op_Mul, gen_Mul);
+ be_set_transform_function(op_Mulh, gen_Mulh);
+ be_set_transform_function(op_Mux, gen_Mux);
+ be_set_transform_function(op_Not, gen_Not);
+ be_set_transform_function(op_Or, gen_Or);
+ be_set_transform_function(op_Phi, gen_Phi);
+ be_set_transform_function(op_Proj, gen_Proj);
+ be_set_transform_function(op_Quot, gen_Quot);
+ be_set_transform_function(op_Rotl, gen_Rotl);
+ be_set_transform_function(op_Shl, gen_Shl);
+ be_set_transform_function(op_Shr, gen_Shr);
+ be_set_transform_function(op_Shrs, gen_Shrs);
+ be_set_transform_function(op_Store, gen_Store);
+ be_set_transform_function(op_Sub, gen_Sub);
+ be_set_transform_function(op_SymConst, gen_SymConst);
+ be_set_transform_function(op_Unknown, ia32_gen_Unknown);
}
/**
*/
static void ia32_pretransform_node(void)
{
- ia32_code_gen_t *cg = env_cg;
+ ir_graph *irg = current_ir_graph;
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
- cg->unknown_gp = be_pre_transform_node(cg->unknown_gp);
- cg->unknown_vfp = be_pre_transform_node(cg->unknown_vfp);
- cg->unknown_xmm = be_pre_transform_node(cg->unknown_xmm);
- cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
- cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
- cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
+ irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
+ irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
+ irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
- nomem = get_irg_no_mem(current_ir_graph);
- noreg_GP = ia32_new_NoReg_gp(cg);
+ nomem = get_irg_no_mem(irg);
+ noreg_GP = ia32_new_NoReg_gp(irg);
get_fpcw();
}
-/**
- * Walker, checks if all ia32 nodes producing more than one result have their
- * Projs, otherwise creates new Projs and keeps them using a be_Keep node.
- */
-static void add_missing_keep_walker(ir_node *node, void *data)
-{
- int n_outs, i;
- unsigned found_projs = 0;
- const ir_edge_t *edge;
- ir_mode *mode = get_irn_mode(node);
- ir_node *last_keep;
- (void) data;
- if (mode != mode_T)
- return;
- if (!is_ia32_irn(node))
- return;
-
- n_outs = arch_irn_get_n_outs(node);
- if (n_outs <= 0)
- return;
- if (is_ia32_SwitchJmp(node))
- return;
-
- assert(n_outs < (int) sizeof(unsigned) * 8);
- foreach_out_edge(node, edge) {
- ir_node *proj = get_edge_src_irn(edge);
- int pn;
-
- /* The node could be kept */
- if (is_End(proj))
- continue;
-
- if (get_irn_mode(proj) == mode_M)
- continue;
-
- pn = get_Proj_proj(proj);
- assert(pn < n_outs);
- found_projs |= 1 << pn;
- }
-
-
- /* are keeps missing? */
- last_keep = NULL;
- for (i = 0; i < n_outs; ++i) {
- ir_node *block;
- ir_node *in[1];
- const arch_register_req_t *req;
- const arch_register_class_t *cls;
-
- if (found_projs & (1 << i)) {
- continue;
- }
-
- req = arch_get_out_register_req(node, i);
- cls = req->cls;
- if (cls == NULL) {
- continue;
- }
- if (cls == &ia32_reg_classes[CLASS_ia32_flags]) {
- continue;
- }
-
- block = get_nodes_block(node);
- in[0] = new_r_Proj(block, node, arch_register_class_mode(cls), i);
- if (last_keep != NULL) {
- be_Keep_add_node(last_keep, cls, in[0]);
- } else {
- last_keep = be_new_Keep(block, 1, in);
- if (sched_is_scheduled(node)) {
- sched_add_after(node, last_keep);
- }
- }
- }
-}
-
-/**
- * Adds missing keeps to nodes. Adds missing Proj nodes for unused outputs
- * and keeps them.
- */
-void ia32_add_missing_keeps(ia32_code_gen_t *cg)
-{
- ir_graph *irg = be_get_birg_irg(cg->birg);
- irg_walk_graph(irg, add_missing_keep_walker, NULL, NULL);
-}
-
/**
* Post-process all calls if we are in SSE mode.
* The ABI requires that the results are in st0, copy them
* to a xmm register.
*/
-static void postprocess_fp_call_results(void) {
+static void postprocess_fp_call_results(void)
+{
int i;
for (i = ARR_LEN(call_list) - 1; i >= 0; --i) {
ir_node *block = get_nodes_block(call);
ir_node *frame = get_irg_frame(current_ir_graph);
ir_node *old_mem = be_get_Proj_for_pn(call, pn_ia32_Call_M);
- ir_node *call_mem = new_r_Proj(block, call, mode_M, pn_ia32_Call_M);
+ ir_node *call_mem = new_r_Proj(call, mode_M, pn_ia32_Call_M);
ir_node *vfst, *xld, *new_mem;
/* store st(0) on stack */
set_ia32_op_type(xld, ia32_AddrModeS);
set_ia32_use_frame(xld);
- new_res = new_r_Proj(block, xld, mode, pn_ia32_xLoad_res);
- new_mem = new_r_Proj(block, xld, mode_M, pn_ia32_xLoad_M);
+ new_res = new_r_Proj(xld, mode, pn_ia32_xLoad_res);
+ new_mem = new_r_Proj(xld, mode_M, pn_ia32_xLoad_M);
if (old_mem != NULL) {
edges_reroute(old_mem, new_mem, current_ir_graph);
}
/* do the transformation */
-void ia32_transform_graph(ia32_code_gen_t *cg)
+void ia32_transform_graph(ir_graph *irg)
{
int cse_last;
register_transformers();
- env_cg = cg;
- initial_fpcw = NULL;
- no_pic_adjust = 0;
+ initial_fpcw = NULL;
+ ia32_no_pic_adjust = 0;
be_timer_push(T_HEIGHTS);
- heights = heights_new(cg->irg);
+ ia32_heights = heights_new(irg);
be_timer_pop(T_HEIGHTS);
- ia32_calculate_non_address_mode_nodes(cg->birg);
+ ia32_calculate_non_address_mode_nodes(irg);
/* the transform phase is not safe for CSE (yet) because several nodes get
* attributes set after their creation */
call_list = NEW_ARR_F(ir_node *, 0);
call_types = NEW_ARR_F(ir_type *, 0);
- be_transform_graph(cg->birg, ia32_pretransform_node);
+ be_transform_graph(irg, ia32_pretransform_node);
if (ia32_cg_config.use_sse2)
postprocess_fp_call_results();
set_opt_cse(cse_last);
ia32_free_non_address_mode_nodes();
- heights_free(heights);
- heights = NULL;
+ heights_free(ia32_heights);
+ ia32_heights = NULL;
}
void ia32_init_transform(void)
projects / libfirm / blobdiff