#define ENT_DFP_ABS "C_ia32_dfp_abs"
#define ENT_ULL_BIAS "C_ia32_ull_bias"
-#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
+#define mode_vfp (ia32_reg_classes[CLASS_ia32_vfp].mode)
#define mode_xmm (ia32_reg_classes[CLASS_ia32_xmm].mode)
DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
static ir_node *initial_fpcw = NULL;
-int no_pic_adjust;
+int ia32_no_pic_adjust;
typedef ir_node *construct_binop_func(dbg_info *db, ir_node *block,
ir_node *base, ir_node *index, ir_node *mem, ir_node *op1,
*/
static bool is_simple_x87_Const(ir_node *node)
{
- tarval *tv = get_Const_tarval(node);
+ ir_tarval *tv = get_Const_tarval(node);
if (tarval_is_null(tv) || tarval_is_one(tv))
return true;
*/
static bool is_simple_sse_Const(ir_node *node)
{
- tarval *tv = get_Const_tarval(node);
- ir_mode *mode = get_tarval_mode(tv);
+ ir_tarval *tv = get_Const_tarval(node);
+ ir_mode *mode = get_tarval_mode(tv);
if (mode == mode_F)
return true;
*/
static ir_node *get_symconst_base(void)
{
- if (be_get_irg_options(env_cg->irg)->pic) {
- return arch_code_generator_get_pic_base(env_cg);
+ ir_graph *irg = current_ir_graph;
+
+ if (be_get_irg_options(irg)->pic) {
+ const arch_env_t *arch_env = be_get_irg_arch_env(irg);
+ return arch_env->impl->get_pic_base(irg);
}
return noreg_GP;
ir_entity *floatent;
if (ia32_cg_config.use_sse2) {
- tarval *tv = get_Const_tarval(node);
+ ir_tarval *tv = get_Const_tarval(node);
if (tarval_is_null(tv)) {
load = new_bd_ia32_xZero(dbgi, block);
set_ia32_ls_mode(load, mode);
}
}
#endif /* CONSTRUCT_SSE_CONST */
- floatent = create_float_const_entity(node);
+ floatent = ia32_create_float_const_entity(node);
base = get_symconst_base();
load = new_bd_ia32_xLoad(dbgi, block, base, noreg_GP, nomem,
ir_mode *ls_mode;
ir_node *base;
- floatent = create_float_const_entity(node);
+ floatent = ia32_create_float_const_entity(node);
/* create_float_const_ent is smart and sometimes creates
smaller entities */
ls_mode = get_type_mode(get_entity_type(floatent));
be_dep_on_frame(load);
return res;
} else { /* non-float mode */
- ir_node *cnst;
- tarval *tv = get_Const_tarval(node);
- long val;
+ ir_node *cnst;
+ ir_tarval *tv = get_Const_tarval(node);
+ long val;
tv = tarval_convert_to(tv, mode_Iu);
};
static ir_entity *ent_cache[ia32_known_const_max];
- const char *ent_name, *cnst_str;
- ir_type *tp;
- ir_entity *ent;
- tarval *tv;
- ir_mode *mode;
+ const char *ent_name, *cnst_str;
+ ir_type *tp;
+ ir_entity *ent;
+ ir_tarval *tv;
+ ir_mode *mode;
ent_name = names[kct].ent_name;
if (! ent_cache[kct]) {
return 0;
/* don't do AM if other node inputs depend on the load (via mem-proj) */
- if (other != NULL && prevents_AM(block, load, other))
+ if (other != NULL && ia32_prevents_AM(block, load, other))
return 0;
- if (other2 != NULL && prevents_AM(block, load, other2))
+ if (other2 != NULL && ia32_prevents_AM(block, load, other2))
return 0;
return 1;
{
/* construct load address */
memset(addr, 0, sizeof(addr[0]));
- ia32_create_address_mode(addr, ptr, 0);
+ ia32_create_address_mode(addr, ptr, ia32_create_am_normal);
addr->base = addr->base ? be_transform_node(addr->base) : noreg_GP;
addr->index = addr->index ? be_transform_node(addr->index) : noreg_GP;
/* floating point immediates */
if (is_Const(node)) {
- ir_entity *entity = create_float_const_entity(node);
+ ir_entity *entity = ia32_create_float_const_entity(node);
addr->base = get_symconst_base();
addr->index = noreg_GP;
addr->mem = nomem;
* op2 input */
new_op2 = NULL;
if (!(flags & match_try_am) && use_immediate) {
- new_op2 = try_create_Immediate(op2, 0);
+ new_op2 = ia32_try_create_Immediate(op2, 0);
}
if (new_op2 == NULL &&
use_am && ia32_use_source_address_mode(block, op2, op1, other_op, flags)) {
- build_address(am, op2, 0);
+ build_address(am, op2, ia32_create_am_normal);
new_op1 = (op1 == NULL ? NULL : be_transform_node(op1));
if (mode_is_float(mode)) {
- new_op2 = ia32_new_NoReg_vfp(env_cg);
+ new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
} else {
new_op2 = noreg_GP;
}
use_am &&
ia32_use_source_address_mode(block, op1, op2, other_op, flags)) {
ir_node *noreg;
- build_address(am, op1, 0);
+ build_address(am, op1, ia32_create_am_normal);
if (mode_is_float(mode)) {
- noreg = ia32_new_NoReg_vfp(env_cg);
+ noreg = ia32_new_NoReg_vfp(current_ir_graph);
} else {
noreg = noreg_GP;
}
n_ia32_l_binop_right, /**< ia32 right input */
n_ia32_l_binop_eflags /**< ia32 eflags input */
};
-COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Adc_left, n_Adc_left)
-COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Adc_right, n_Adc_right)
-COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Adc_eflags, n_Adc_eflags)
-COMPILETIME_ASSERT(n_ia32_l_binop_left == n_ia32_l_Sbb_minuend, n_Sbb_minuend)
-COMPILETIME_ASSERT(n_ia32_l_binop_right == n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
-COMPILETIME_ASSERT(n_ia32_l_binop_eflags == n_ia32_l_Sbb_eflags, n_Sbb_eflags)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Adc_left, n_Adc_left)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Adc_right, n_Adc_right)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Adc_eflags, n_Adc_eflags)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_left == (int)n_ia32_l_Sbb_minuend, n_Sbb_minuend)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_right == (int)n_ia32_l_Sbb_subtrahend, n_Sbb_subtrahend)
+COMPILETIME_ASSERT((int)n_ia32_l_binop_eflags == (int)n_ia32_l_Sbb_eflags, n_Sbb_eflags)
/**
* Construct a binary operation which also consumes the eflags.
if (initial_fpcw != NULL)
return initial_fpcw;
- fpcw = be_abi_get_ignore_irn(be_get_irg_abi(env_cg->irg),
- &ia32_fp_cw_regs[REG_FPCW]);
+ fpcw = be_abi_get_ignore_irn(be_get_irg_abi(current_ir_graph),
+ &ia32_registers[REG_FPCW]);
initial_fpcw = be_transform_node(fpcw);
return initial_fpcw;
return new_node;
}
-static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
+static ir_node *create_lea_from_address(dbg_info *dbgi, ir_node *block,
ia32_address_t *addr)
{
ir_node *base, *index, *res;
/* is it a zero extension? */
if (is_Const(op2)) {
- tarval *tv = get_Const_tarval(op2);
- long v = get_tarval_long(tv);
+ ir_tarval *tv = get_Const_tarval(op2);
+ long v = get_tarval_long(tv);
if (v == 0xFF || v == 0xFFFF) {
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *right = get_Shrs_right(node);
if (is_Const(right)) {
- tarval *tv = get_Const_tarval(right);
- long val = get_tarval_long(tv);
+ ir_tarval *tv = get_Const_tarval(right);
+ long val = get_tarval_long(tv);
if (val == 31) {
/* this is a sign extension */
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *shl_left = get_Shl_left(left);
ir_node *shl_right = get_Shl_right(left);
if (is_Const(shl_right)) {
- tarval *tv1 = get_Const_tarval(right);
- tarval *tv2 = get_Const_tarval(shl_right);
+ ir_tarval *tv1 = get_Const_tarval(right);
+ ir_tarval *tv2 = get_Const_tarval(shl_right);
if (tv1 == tv2 && tarval_is_long(tv1)) {
long val = get_tarval_long(tv1);
if (val == 16 || val == 24) {
/* TODO: non-optimal... if we have many xXors, then we should
* rather create a load for the const and use that instead of
* several AM nodes... */
- ir_node *noreg_xmm = ia32_new_NoReg_xmm(env_cg);
+ ir_node *noreg_xmm = ia32_new_NoReg_xmm(current_ir_graph);
new_node = new_bd_ia32_xXor(dbgi, block, get_symconst_base(),
noreg_GP, nomem, new_op, noreg_xmm);
new_op = be_transform_node(op);
if (ia32_cg_config.use_sse2) {
- ir_node *noreg_fp = ia32_new_NoReg_xmm(env_cg);
+ ir_node *noreg_fp = ia32_new_NoReg_xmm(current_ir_graph);
new_node = new_bd_ia32_xAnd(dbgi, new_block, get_symconst_base(),
noreg_GP, nomem, new_op, noreg_fp);
}
}
} else {
- ir_node *xor;
+ ir_node *xorn;
ir_node *sign_extension;
if (get_mode_size_bits(mode) == 32) {
sign_extension = create_sex_32_64(dbgi, new_block, new_op, node);
- xor = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
+ xorn = new_bd_ia32_Xor(dbgi, new_block, noreg_GP, noreg_GP,
nomem, new_op, sign_extension);
- SET_IA32_ORIG_NODE(xor, node);
+ SET_IA32_ORIG_NODE(xorn, node);
if (negate) {
new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, sign_extension, xor);
+ nomem, sign_extension, xorn);
} else {
new_node = new_bd_ia32_Sub(dbgi, new_block, noreg_GP, noreg_GP,
- nomem, xor, sign_extension);
+ nomem, xorn, sign_extension);
}
SET_IA32_ORIG_NODE(new_node, node);
}
* @param node the node to transform
* @param pnc_out the compare mode to use
*/
-static ir_node *get_flags_node(ir_node *node, pn_Cmp *pnc_out)
+static ir_node *get_flags_node(ir_node *node, int *pnc_out)
{
ir_node *flags;
ir_node *new_op;
if (is_Proj(node)) {
ir_node *pred = get_Proj_pred(node);
if (is_Cmp(pred)) {
- pn_Cmp pnc = get_Proj_proj(node);
+ int pnc = get_Proj_pn_cmp(node);
if (ia32_cg_config.use_bt && (pnc == pn_Cmp_Lg || pnc == pn_Cmp_Eq)) {
ir_node *l = get_Cmp_left(pred);
ir_node *r = get_Cmp_right(pred);
/* construct load address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
base = addr.base;
index = addr.index;
set_address(new_node, &addr);
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
- && pn_ia32_vfld_res == pn_ia32_Load_res
- && pn_ia32_Load_res == pn_ia32_res);
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
+ && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ && (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_irn_add_flags(new_node, arch_irn_flags_rematerializable);
}
/* don't do AM if other node inputs depend on the load (via mem-proj) */
if (other != NULL &&
get_nodes_block(other) == block &&
- heights_reachable_in_block(heights, other, load)) {
+ heights_reachable_in_block(ia32_heights, other, load)) {
return 0;
}
- if (prevents_AM(block, load, mem))
+ if (ia32_prevents_AM(block, load, mem))
return 0;
/* Store should be attached to the load via mem */
- assert(heights_reachable_in_block(heights, mem, load));
+ assert(heights_reachable_in_block(ia32_heights, mem, load));
return 1;
}
return new_node;
}
-static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
+static int ia32_get_negated_pnc(int pnc)
{
ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
return get_negated_pnc(pnc, mode);
ir_node *flags;
ir_node *new_node;
bool negated;
- pn_Cmp pnc;
+ int pnc;
ia32_address_t addr;
if (get_mode_size_bits(mode) != 8)
{
ir_mode *mode = get_irn_mode(cns);
unsigned size = get_mode_size_bytes(mode);
- tarval *tv = get_Const_tarval(cns);
+ ir_tarval *tv = get_Const_tarval(cns);
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
ir_node *ptr = get_Store_ptr(node);
new_node = new_r_Proj(vfisttp, mode_M, pn_ia32_vfisttp_M);
*fist = vfisttp;
} else {
- ir_node *trunc_mode = ia32_new_Fpu_truncate(env_cg);
+ ir_node *trunc_mode = ia32_new_Fpu_truncate(current_ir_graph);
/* do a fist */
new_node = new_bd_ia32_vfist(dbgi, block, base, index, mem, val, trunc_mode);
/* construct store address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
if (addr.base == NULL) {
addr.base = noreg_GP;
ir_node *block = get_nodes_block(node);
ir_node *new_block = be_transform_node(block);
dbg_info *dbgi = get_irn_dbg_info(node);
- ir_node *sel = get_Cond_selector(node);
+ ir_node *sel = get_Cond_selector(node);
ir_mode *sel_mode = get_irn_mode(sel);
ir_node *flags = NULL;
ir_node *new_node;
- pn_Cmp pnc;
+ int pnc;
if (sel_mode != mode_b) {
return create_Switch(node);
/** we can only have eq and lg projs */
foreach_out_edge(node, edge) {
ir_node *proj = get_edge_src_irn(edge);
- pn_Cmp pnc = get_Proj_proj(proj);
+ pn_Cmp pnc = get_Proj_pn_cmp(proj);
if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg)
return false;
}
}
static ir_node *create_CMov(ir_node *node, ir_node *flags, ir_node *new_flags,
- pn_Cmp pnc)
+ int pnc)
{
dbg_info *dbgi = get_irn_dbg_info(node);
ir_node *block = get_nodes_block(node);
* Creates a ia32 Setcc instruction.
*/
static ir_node *create_set_32bit(dbg_info *dbgi, ir_node *new_block,
- ir_node *flags, pn_Cmp pnc,
+ ir_node *flags, int pnc,
ir_node *orig_node)
{
ir_mode *mode = get_irn_mode(orig_node);
ir_node *new_node;
ir_node *sub;
ir_node *sbb;
- ir_node *not;
+ ir_node *notn;
ir_node *eflags;
ir_node *block;
}
eflags = new_rd_Proj(NULL, sub, mode_Iu, pn_ia32_Sub_flags);
- dbgi = get_irn_dbg_info(psi);
- sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
- not = new_bd_ia32_Not(dbgi, block, sbb);
+ dbgi = get_irn_dbg_info(psi);
+ sbb = new_bd_ia32_Sbb0(dbgi, block, eflags);
+ notn = new_bd_ia32_Not(dbgi, block, sbb);
- new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, not);
+ new_node = new_bd_ia32_And(dbgi, block, noreg_GP, noreg_GP, nomem, new_node, notn);
set_ia32_commutative(new_node);
return new_node;
}
ir_mode *mode = *new_mode;
ir_type *tp;
ir_initializer_t *initializer;
- tarval *tv0 = get_Const_tarval(c0);
- tarval *tv1 = get_Const_tarval(c1);
+ ir_tarval *tv0 = get_Const_tarval(c0);
+ ir_tarval *tv1 = get_Const_tarval(c1);
if (mode == NULL) {
/* detect the best mode for the constants */
typedef struct setcc_transform {
unsigned num_steps;
- pn_Cmp pnc;
+ int pnc;
struct {
enum setcc_transform_insn transform;
long val;
* Find a transformation that creates 0 and 1 from
* tv_t and tv_f.
*/
-static void find_const_transform(pn_Cmp pnc, tarval *t, tarval *f,
+static void find_const_transform(int pnc, ir_tarval *t, ir_tarval *f,
setcc_transform_t *res)
{
unsigned step = 0;
res->num_steps = 0;
if (tarval_is_null(t)) {
- tarval *tmp = t;
+ ir_tarval *tmp = t;
t = f;
f = tmp;
pnc = ia32_get_negated_pnc(pnc);
} else if (tarval_cmp(t, f) == pn_Cmp_Lt) {
// now, t is the bigger one
- tarval *tmp = t;
+ ir_tarval *tmp = t;
t = f;
f = tmp;
pnc = ia32_get_negated_pnc(pnc);
res->pnc = pnc;
if (! tarval_is_null(f)) {
- tarval *t_sub = tarval_sub(t, f, NULL);
+ ir_tarval *t_sub = tarval_sub(t, f, NULL);
t = t_sub;
res->steps[step].transform = SETCC_TR_ADD;
ir_node *flags;
ir_node *new_node;
int is_abs;
- pn_Cmp pnc;
+ int pnc;
assert(get_irn_mode(cond) == mode_b);
ir_node *cmp = get_Proj_pred(cond);
ir_node *cmp_left = get_Cmp_left(cmp);
ir_node *cmp_right = get_Cmp_right(cmp);
- pn_Cmp pnc = get_Proj_proj(cond);
+ int pnc = get_Proj_proj(cond);
if (ia32_cg_config.use_sse2) {
if (pnc == pn_Cmp_Lt || pnc == pn_Cmp_Le) {
ir_node *cmp_right = get_Cmp_right(cmp);
ir_node *val_true = mux_true;
ir_node *val_false = mux_false;
- pn_Cmp pnc = get_Proj_proj(cond);
+ int pnc = get_Proj_proj(cond);
if (is_Const(val_true) && is_Const_null(val_true)) {
ir_node *tmp = val_false;
if (is_Const(mux_true) && is_Const(mux_false)) {
/* both are const, good */
- tarval *tv_true = get_Const_tarval(mux_true);
- tarval *tv_false = get_Const_tarval(mux_false);
+ ir_tarval *tv_true = get_Const_tarval(mux_true);
+ ir_tarval *tv_false = get_Const_tarval(mux_false);
setcc_transform_t res;
int step;
/* if fp_no_float_fold is not set then we assume that we
* don't have any float operations in a non
* mode_float_arithmetic mode and can skip strict upconvs */
- if (src_bits < tgt_bits
- && !(get_irg_fp_model(current_ir_graph) & fp_no_float_fold)) {
+ if (src_bits < tgt_bits) {
DB((dbg, LEVEL_1, "killed Conv(float, float) ..."));
return new_op;
} else {
static ir_node *create_immediate_or_transform(ir_node *node,
char immediate_constraint_type)
{
- ir_node *new_node = try_create_Immediate(node, immediate_constraint_type);
+ ir_node *new_node = ia32_try_create_Immediate(node, immediate_constraint_type);
if (new_node == NULL) {
new_node = be_transform_node(node);
}
ir_node *sub, *res, *flags, *block;
res = gen_binop(node, get_Bound_index(node), get_Bound_upper(node),
- new_bd_ia32_Sub, match_mode_neutral | match_am | match_immediate);
+ new_bd_ia32_Sub,
+ match_mode_neutral | match_am | match_immediate);
block = get_nodes_block(res);
if (! is_Proj(res)) {
match_mode_neutral);
if (is_Proj(lowered)) {
- lowered = get_Proj_pred(lowered);
+ lowered = get_Proj_pred(lowered);
} else {
assert(is_ia32_Add(lowered));
set_irn_mode(lowered, mode_T);
match_am | match_immediate | match_mode_neutral);
if (is_Proj(lowered)) {
- lowered = get_Proj_pred(lowered);
+ lowered = get_Proj_pred(lowered);
} else {
assert(is_ia32_Sub(lowered));
set_irn_mode(lowered, mode_T);
am.mem_proj = nomem;
am.op_type = ia32_AddrModeS;
am.new_op1 = res;
- am.new_op2 = ia32_new_NoReg_vfp(env_cg);
+ am.new_op2 = ia32_new_NoReg_vfp(current_ir_graph);
am.pinned = op_pin_state_floats;
am.commutative = 1;
am.ins_permuted = 0;
if (proj == pn_be_AddSP_sp) {
ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
pn_ia32_SubSP_stack);
- arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
return res;
} else if (proj == pn_be_AddSP_res) {
return new_rd_Proj(dbgi, new_pred, mode_Iu,
if (proj == pn_be_SubSP_sp) {
ir_node *res = new_rd_Proj(dbgi, new_pred, mode_Iu,
pn_ia32_AddSP_stack);
- arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
return res;
} else if (proj == pn_be_SubSP_M) {
return new_rd_Proj(dbgi, new_pred, mode_M, pn_ia32_AddSP_M);
ir_mode *const res_mode = get_type_mode(res_type);
if (res_mode != NULL && mode_is_float(res_mode)) {
- env_cg->do_x87_sim = 1;
+ ir_graph *irg = current_ir_graph;
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
+ irg_data->do_x87_sim = 1;
}
}
assert(be_Call_get_entity(node) == NULL);
/* special case for PIC trampoline calls */
- old_no_pic_adjust = no_pic_adjust;
- no_pic_adjust = be_get_irg_options(env_cg->irg)->pic;
+ old_no_pic_adjust = ia32_no_pic_adjust;
+ ia32_no_pic_adjust = be_get_irg_options(current_ir_graph)->pic;
match_arguments(&am, src_block, NULL, src_ptr, src_mem,
match_am | match_immediate);
- no_pic_adjust = old_no_pic_adjust;
+ ia32_no_pic_adjust = old_no_pic_adjust;
i = get_irn_arity(node) - 1;
fpcw = be_transform_node(get_irn_n(node, i--));
assert(req->cls == &ia32_reg_classes[CLASS_ia32_gp]);
switch (*req->limited) {
- case 1 << REG_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
- case 1 << REG_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
- case 1 << REG_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
+ case 1 << REG_GP_EAX: assert(eax == noreg_GP); eax = reg_parm; break;
+ case 1 << REG_GP_ECX: assert(ecx == noreg_GP); ecx = reg_parm; break;
+ case 1 << REG_GP_EDX: assert(edx == noreg_GP); edx = reg_parm; break;
default: panic("Invalid GP register for register parameter");
}
}
*/
static ir_node *gen_return_address(ir_node *node)
{
- ir_node *param = get_Builtin_param(node, 0);
- ir_node *frame = get_Builtin_param(node, 1);
- dbg_info *dbgi = get_irn_dbg_info(node);
- tarval *tv = get_Const_tarval(param);
+ ir_node *param = get_Builtin_param(node, 0);
+ ir_node *frame = get_Builtin_param(node, 1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_tarval *tv = get_Const_tarval(param);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
set_ia32_frame_ent(load, ia32_get_return_address_entity());
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
- && pn_ia32_vfld_res == pn_ia32_Load_res
- && pn_ia32_Load_res == pn_ia32_res);
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
+ && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ && (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_irn_add_flags(load, arch_irn_flags_rematerializable);
}
*/
static ir_node *gen_frame_address(ir_node *node)
{
- ir_node *param = get_Builtin_param(node, 0);
- ir_node *frame = get_Builtin_param(node, 1);
- dbg_info *dbgi = get_irn_dbg_info(node);
- tarval *tv = get_Const_tarval(param);
+ ir_node *param = get_Builtin_param(node, 0);
+ ir_node *frame = get_Builtin_param(node, 1);
+ dbg_info *dbgi = get_irn_dbg_info(node);
+ ir_tarval *tv = get_Const_tarval(param);
unsigned long value = get_tarval_long(tv);
ir_node *block = be_transform_node(get_nodes_block(node));
}
if (get_irn_pinned(node) == op_pin_state_floats) {
- assert(pn_ia32_xLoad_res == pn_ia32_vfld_res
- && pn_ia32_vfld_res == pn_ia32_Load_res
- && pn_ia32_Load_res == pn_ia32_res);
+ assert((int)pn_ia32_xLoad_res == (int)pn_ia32_vfld_res
+ && (int)pn_ia32_vfld_res == (int)pn_ia32_Load_res
+ && (int)pn_ia32_Load_res == (int)pn_ia32_res);
arch_irn_add_flags(load, arch_irn_flags_rematerializable);
}
ir_node *ptr, *block, *mem, *base, *index;
ir_node *param, *new_node;
long rw, locality;
- tarval *tv;
+ ir_tarval *tv;
ia32_address_t addr;
if (!ia32_cg_config.use_sse_prefetch && !ia32_cg_config.use_3dnow_prefetch) {
/* construct load address */
memset(&addr, 0, sizeof(addr));
ptr = get_Builtin_param(node, 0);
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
base = addr.base;
index = addr.index;
ir_node *real = skip_Proj(bsf);
dbg_info *dbgi = get_irn_dbg_info(real);
ir_node *block = get_nodes_block(real);
- ir_node *flag, *set, *conv, *neg, *or;
+ ir_node *flag, *set, *conv, *neg, *orn;
/* bsf x */
if (get_irn_mode(real) != mode_T) {
neg = new_bd_ia32_Neg(dbgi, block, conv);
/* or */
- or = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
- set_ia32_commutative(or);
+ orn = new_bd_ia32_Or(dbgi, block, noreg_GP, noreg_GP, nomem, bsf, neg);
+ set_ia32_commutative(orn);
/* add 1 */
- return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, or, ia32_create_Immediate(NULL, 0, 1));
+ return new_bd_ia32_Add(dbgi, block, noreg_GP, noreg_GP, nomem, orn, ia32_create_Immediate(NULL, 0, 1));
}
/**
/* construct store address */
memset(&addr, 0, sizeof(addr));
- ia32_create_address_mode(&addr, ptr, 0);
+ ia32_create_address_mode(&addr, ptr, ia32_create_am_normal);
if (addr.base == NULL) {
addr.base = noreg_GP;
/* TODO arch_set_irn_register() only operates on Projs, need variant with index */
switch (proj) {
case pn_ia32_Call_stack:
- arch_set_irn_register(res, &ia32_gp_regs[REG_ESP]);
+ arch_set_irn_register(res, &ia32_registers[REG_ESP]);
break;
case pn_ia32_Call_fpcw:
- arch_set_irn_register(res, &ia32_fp_cw_regs[REG_FPCW]);
+ arch_set_irn_register(res, &ia32_registers[REG_FPCW]);
break;
}
}
case pn_Start_P_tls:
- return gen_Proj_tls(node);
+ return ia32_gen_Proj_tls(node);
}
break;
be_set_transform_function(op_Add, gen_Add);
be_set_transform_function(op_And, gen_And);
- be_set_transform_function(op_ASM, gen_ASM);
+ be_set_transform_function(op_ASM, ia32_gen_ASM);
be_set_transform_function(op_be_AddSP, gen_be_AddSP);
be_set_transform_function(op_be_Call, gen_be_Call);
be_set_transform_function(op_be_Copy, gen_be_Copy);
be_set_transform_function(op_Cond, gen_Cond);
be_set_transform_function(op_Const, gen_Const);
be_set_transform_function(op_Conv, gen_Conv);
- be_set_transform_function(op_CopyB, gen_CopyB);
+ be_set_transform_function(op_CopyB, ia32_gen_CopyB);
be_set_transform_function(op_Div, gen_Div);
be_set_transform_function(op_DivMod, gen_DivMod);
be_set_transform_function(op_Eor, gen_Eor);
be_set_transform_function(op_Store, gen_Store);
be_set_transform_function(op_Sub, gen_Sub);
be_set_transform_function(op_SymConst, gen_SymConst);
- be_set_transform_function(op_Unknown, gen_Unknown);
+ be_set_transform_function(op_Unknown, ia32_gen_Unknown);
}
/**
*/
static void ia32_pretransform_node(void)
{
- ia32_code_gen_t *cg = env_cg;
+ ir_graph *irg = current_ir_graph;
+ ia32_irg_data_t *irg_data = ia32_get_irg_data(current_ir_graph);
- cg->noreg_gp = be_pre_transform_node(cg->noreg_gp);
- cg->noreg_vfp = be_pre_transform_node(cg->noreg_vfp);
- cg->noreg_xmm = be_pre_transform_node(cg->noreg_xmm);
+ irg_data->noreg_gp = be_pre_transform_node(irg_data->noreg_gp);
+ irg_data->noreg_vfp = be_pre_transform_node(irg_data->noreg_vfp);
+ irg_data->noreg_xmm = be_pre_transform_node(irg_data->noreg_xmm);
- nomem = get_irg_no_mem(current_ir_graph);
- noreg_GP = ia32_new_NoReg_gp(cg);
+ nomem = get_irg_no_mem(irg);
+ noreg_GP = ia32_new_NoReg_gp(irg);
get_fpcw();
}
}
/* do the transformation */
-void ia32_transform_graph(ia32_code_gen_t *cg)
+void ia32_transform_graph(ir_graph *irg)
{
int cse_last;
register_transformers();
- env_cg = cg;
- initial_fpcw = NULL;
- no_pic_adjust = 0;
+ initial_fpcw = NULL;
+ ia32_no_pic_adjust = 0;
be_timer_push(T_HEIGHTS);
- heights = heights_new(cg->irg);
+ ia32_heights = heights_new(irg);
be_timer_pop(T_HEIGHTS);
- ia32_calculate_non_address_mode_nodes(cg->irg);
+ ia32_calculate_non_address_mode_nodes(irg);
/* the transform phase is not safe for CSE (yet) because several nodes get
* attributes set after their creation */
call_list = NEW_ARR_F(ir_node *, 0);
call_types = NEW_ARR_F(ir_type *, 0);
- be_transform_graph(cg->irg, ia32_pretransform_node);
+ be_transform_graph(irg, ia32_pretransform_node);
if (ia32_cg_config.use_sse2)
postprocess_fp_call_results();
set_opt_cse(cse_last);
ia32_free_non_address_mode_nodes();
- heights_free(heights);
- heights = NULL;
+ heights_free(ia32_heights);
+ ia32_heights = NULL;
}
void ia32_init_transform(void)
projects / libfirm / blobdiff