S3 => "${arch}_emit_source_register(env, node, 3);",
S4 => "${arch}_emit_source_register(env, node, 4);",
S5 => "${arch}_emit_source_register(env, node, 5);",
+ SB1 => "${arch}_emit_8bit_source_register(env, node, 1);",
+ SB2 => "${arch}_emit_8bit_source_register(env, node, 2);",
+ SW0 => "${arch}_emit_16bit_source_register(env, node, 0);",
+ SI0 => "${arch}_emit_source_register_or_immediate(env, node, 0);",
+ SI1 => "${arch}_emit_source_register_or_immediate(env, node, 1);",
+ SI2 => "${arch}_emit_source_register_or_immediate(env, node, 2);",
+ SI3 => "${arch}_emit_source_register_or_immediate(env, node, 3);",
D0 => "${arch}_emit_dest_register(env, node, 0);",
D1 => "${arch}_emit_dest_register(env, node, 1);",
D2 => "${arch}_emit_dest_register(env, node, 2);",
X0 => "${arch}_emit_x87_name(env, node, 0);",
X1 => "${arch}_emit_x87_name(env, node, 1);",
X2 => "${arch}_emit_x87_name(env, node, 2);",
- C => "${arch}_emit_immediate(env, node);",
SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
ia32_emit_mode_suffix(env, node);",
reg_req => { out => [ "gp_NOREG" ] },
attr => "ir_entity *symconst, int symconst_sign, long offset",
attr_type => "ia32_immediate_attr_t",
+ latency => 0,
mode => $mode_gp,
},
arity => "variable",
out_arity => "variable",
attr_type => "ia32_asm_attr_t",
+ latency => 100,
+},
+
+ProduceVal => {
+ op_flags => "c",
+ irn_flags => "R",
+ reg_req => { out => [ "gp" ] },
+ emit => "",
+ units => [ ],
+ latency => 0,
+ mode => $mode_gp,
+ cmp_attr => "return 1;",
},
#-----------------------------------------------------------------#
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
ins => [ "base", "index", "left", "right", "mem" ],
emit => '. add%M %binop',
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+AddMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ emit => ". add%M %SI2, %AM",
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Adc => {
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
emit => '. adc%M %binop',
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
emit => '
. movl %S0, %D0
. movl %S1, %D1
-. addl %S2, %D0
-. adcl %S3, %D1
+. addl %SI2, %D0
+. adcl %SI3, %D1
',
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
emit => '. mul%M %unop3',
outs => [ "EAX", "EDX", "M" ],
ins => [ "base", "index", "val_high", "val_low", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
latency => 10,
units => [ "GP" ],
modified_flags => $status_flags
IMul => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
emit => '. imul%M %binop',
+ init_attr => "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
latency => 5,
units => [ "GP" ],
mode => $mode_gp,
emit => '. imul%M %unop3',
outs => [ "EAX", "EDX", "M" ],
ins => [ "base", "index", "val_high", "val_low", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
latency => 5,
units => [ "GP" ],
modified_flags => $status_flags
},
l_IMul => {
+ # we should not rematrialize this node. It produces 2 results and has
+ # very strict constrains
op_flags => "C",
cmp_attr => "return 1;",
+ outs => [ "EAX", "EDX", "M" ],
arity => 2
},
And => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
emit => '. and%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+AndMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ emit => '. and%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Or => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
emit => '. or%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+OrMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ emit => '. or%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Xor => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
emit => '. xor%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+XorMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ emit => '. xor%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
l_Xor => {
op_flags => "C",
cmp_attr => "return 1;",
Sub => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
emit => '. sub%M %binop',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+SubMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ emit => '. sub%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => 'mode_M',
+ modified_flags => $status_flags
+},
+
Sbb => {
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Full, ia32_am_binary);",
emit => '. sbb%M %binop',
units => [ "GP" ],
mode => $mode_gp,
emit => '
. movl %S0, %D0
. movl %S1, %D1
-. subl %S2, %D0
-. sbbl %S3, %D1
+. subl %SI2, %D0
+. sbbl %SI3, %D1
',
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
IDiv => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ],
+ out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "left_low", "left_high", "right", "mem" ],
+ outs => [ "div_res", "mod_res", "M" ],
attr => "ia32_op_flavour_t dm_flav",
- init_attr => "attr->data.op_flav = dm_flav;",
+ init_attr =>
+ "attr->data.op_flav = dm_flav;".
+ "set_ia32_am_support(res, ia32_am_Full, ia32_am_ternary);",
emit => ". idiv%M %unop4",
- outs => [ "div_res", "mod_res", "M" ],
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Div => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
+ reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ],
+ out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "left_low", "left_high", "right", "mem" ],
+ outs => [ "div_res", "mod_res", "M" ],
attr => "ia32_op_flavour_t dm_flav",
- init_attr => "attr->data.op_flav = dm_flav;",
+ init_attr =>
+ "attr->data.op_flav = dm_flav;".
+ "set_ia32_am_support(res, ia32_am_Full, ia32_am_ternary);",
emit => ". div%M %unop4",
- outs => [ "div_res", "mod_res", "M" ],
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Shl => {
irn_flags => "R",
- # "in_r3" would be enough as out requirement, but the register allocator
- # does strange things then and doesn't respect the constraint for in4
- # if the same value is attached to in3 and in4 (if you have "i << i" in C)
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
- emit => '. shl%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "left", "right" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);",
+ emit => '. shl %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Shl => {
+ShlMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "count", "mem" ],
+ emit => '. shl%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+l_ShlDep => {
cmp_attr => "return 1;",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShlD => {
- irn_flags => "R",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
- # this Shift and the only value dying is the ShiftCount. Then there would be
- # a register missing, as result must not be ecx and all other registers are
- # occupied. What we should write is "!in_r4 !in_r5", but this is not
- # supported (and probably never will). So we create artificial interferences
- # of the result with all inputs, so the spiller can always assure a free
- # register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
- emit =>
-'
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shld%M %%cl, %S3, %AM
- } else {
- . shld%M %%cl, %S3, %S2
- }
-} else {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shld%M %C, %S3, %AM
- } else {
- . shld%M %C, %S3, %S2
- }
-}
-',
+ # this Shift and the only value dying is the ShiftCount. Then there would be a
+ # register missing, as result must not be ecx and all other registers are
+ # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+ # (and probably never will). So we create artificial interferences of the result
+ # with all inputs, so the spiller can always assure a free register.
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "in_r1 !in_r3" ] },
+ ins => [ "left_high", "left_low", "right" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);",
+ emit => '. shld%M %SB2, %S1, %S0',
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
Shr => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. shr%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);",
+ emit => '. shr %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Shr => {
+ShrMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "count", "mem" ],
+ emit => '. shr%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+l_ShrDep => {
cmp_attr => "return 1;",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShrD => {
- irn_flags => "R",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
- emit => '
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shrd%M %%cl, %S3, %AM
- } else {
- . shrd%M %%cl, %S3, %S2
- }
-} else {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shrd%M %C, %S3, %AM
- } else {
- . shrd%M %C, %S3, %S2
- }
-}
-',
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "in_r1 !in_r3" ] },
+ ins => [ "left_high", "left_low", "right" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);",
+ emit => '. shrd%M %SB2, %S1, %S0',
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
Sar => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. sar%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);",
+ emit => '. sar %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+SarMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "count", "mem" ],
+ emit => '. sar%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
l_Sar => {
cmp_attr => "return 1;",
+ # value, cnt
arity => 2
},
+l_SarDep => {
+ cmp_attr => "return 1;",
+ # value, cnt, dependency
+ arity => 3
+},
+
Ror => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. ror%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);",
+ emit => '. ror %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+RorMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "count", "mem" ],
+ emit => '. ror%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Rol => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. rol%M %binop',
+ reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ ins => [ "val", "count" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);",
+ emit => '. rol %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+RolMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "count", "mem" ],
+ emit => '. rol%M %SI2, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
# unary operations
Neg => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. neg%M %unop2',
- ins => [ "base", "index", "val", "mem" ],
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ emit => '. neg %S0',
+ ins => [ "val" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);",
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
},
+NegMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. neg%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Minus64Bit => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S0, %D1
-. subl %S1, %D0
-. sbbl %S2, %D1
-',
+ reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] },
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
modified_flags => $status_flags
Inc => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. inc%M %unop2',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);",
+ emit => '. inc %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
},
+IncMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. inc%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+},
+
Dec => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. dec%M %unop2',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);",
+ emit => '. dec %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
},
+DecMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. dec%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+},
+
Not => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- ins => [ "base", "index", "val", "mem" ],
- emit => '. not%M %unop2',
+ reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ ins => [ "val" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);",
+ emit => '. not %S0',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => []
},
+NotMem => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. not%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ modified_flags => [],
+},
+
# other operations
-CondJmp => {
+CmpJmp => {
state => "pinned",
op_flags => "L|X|Y",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
ins => [ "base", "index", "left", "right", "mem" ],
outs => [ "false", "true" ],
attr => "long pnc",
- init_attr => "attr->pn_code = pnc;",
+ init_attr =>
+ "attr->pn_code = pnc;".
+ "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
+ latency => 3,
+ units => [ "BRANCH" ],
+},
+
+CmpJmp8Bit => {
+ state => "pinned",
+ op_flags => "L|X|Y",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "eax ebx ecx edx",
+ "none" ],
+ out => [ "none", "none"] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ outs => [ "false", "true" ],
+ attr => "long pnc",
+ init_attr =>
+ "attr->pn_code = pnc;".
+ "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
latency => 3,
units => [ "BRANCH" ],
},
ins => [ "base", "index", "left", "right", "mem" ],
outs => [ "false", "true" ],
attr => "long pnc",
- init_attr => "attr->pn_code = pnc;",
+ init_attr =>
+ "attr->pn_code = pnc;".
+ "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
+ latency => 3,
+ units => [ "BRANCH" ],
+},
+
+TestJmp8Bit => {
+ state => "pinned",
+ op_flags => "L|X|Y",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "eax ebx ecx edx",
+ "none" ],
+ out => [ "none", "none" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
+ outs => [ "false", "true" ],
+ attr => "long pnc",
+ init_attr =>
+ "attr->pn_code = pnc;".
+ "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
latency => 3,
units => [ "BRANCH" ],
},
mode => "mode_T",
},
+IJmp => {
+ state => "pinned",
+ op_flags => "X",
+ reg_req => { in => [ "gp" ] },
+ emit => '. jmp *%S0',
+ units => [ "BRANCH" ],
+ mode => "mode_X",
+ modified_flags => []
+},
+
Const => {
op_flags => "c",
irn_flags => "R",
reg_req => { out => [ "gp" ] },
units => [ "GP" ],
+ attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr_type => "ia32_immediate_attr_t",
mode => $mode_gp,
},
op_flags => "L|F",
state => "pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
+ ins => [ "base", "index", "mem" ],
latency => 5,
emit => ". fldcw %AM",
mode => $mode_fpcw,
op_flags => "L|F",
state => "pinned",
reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "fpcw", "mem" ],
latency => 5,
emit => ". fnstcw %AM",
mode => "mode_M",
Cltd => {
# we should not rematrialize this node. It produces 2 results and has
# very strict constrains
- reg_req => { in => [ "eax" ], out => [ "edx" ] },
- ins => [ "val" ],
+ reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] },
+ ins => [ "val", "globbered" ],
emit => '. cltd',
mode => $mode_gp,
units => [ "GP" ],
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
ins => [ "base", "index", "val", "mem" ],
- emit => '. mov%M %binop',
+ emit => '. mov%M %SI2, %AM',
latency => 2,
units => [ "GP" ],
mode => "mode_M",
op_flags => "L|F",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
- emit => '. mov%M %binop',
+ emit => '. mov%M %SB2, %AM',
latency => 2,
units => [ "GP" ],
mode => "mode_M",
Lea => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ ins => [ "base", "index" ],
emit => '. leal %AM, %D0',
latency => 2,
units => [ "GP" ],
emit => '. push%M %unop2',
ins => [ "base", "index", "val", "stack", "mem" ],
outs => [ "stack:I|S", "M" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
latency => 2,
units => [ "GP" ],
modified_flags => [],
emit => '. pop%M %DAM1',
outs => [ "stack:I|S", "res", "M" ],
ins => [ "base", "index", "stack", "mem" ],
+ init_attr => "set_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);",
latency => 3, # Pop is more expensive than Push on Athlon
units => [ "GP" ],
modified_flags => [],
AddSP => {
irn_flags => "I",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ init_attr => "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
emit => '. addl %binop',
outs => [ "stack:S", "M" ],
units => [ "GP" ],
},
SubSP => {
- irn_flags => "I",
- reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
- emit => '. subl %binop',
- outs => [ "stack:S", "M" ],
+#irn_flags => "I",
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
+ init_attr => "set_ia32_am_support(res, ia32_am_Source, ia32_am_binary);",
+ emit => ". subl %binop\n".
+ ". movl %%esp, %D1",
+ outs => [ "stack:I|S", "addr", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
# the int instruction
int => {
- reg_req => { in => [ "none" ], out => [ "none" ] },
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
mode => "mode_M",
- attr => "tarval *tv",
- init_attr => "\tset_ia32_Immop_tarval(res, tv);",
- emit => '. int %C',
+ emit => '. int %SI0',
units => [ "GP" ],
cmp_attr => "return 1;",
},
# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#-----------------------------------------------------------------------------#
+xZero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. xorp%XSD %D1, %D1',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => "mode_E",
+},
+
# commutative operations
xAdd => {
mode => "mode_E",
},
-xCondJmp => {
+xCmpJmp => {
state => "pinned",
op_flags => "L|X|Y",
reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
units => [ "SSE" ],
},
-xConst => {
- op_flags => "c",
- irn_flags => "R",
- reg_req => { out => [ "xmm" ] },
- emit => '. mov%XXM %C, %D0',
- latency => 2,
- units => [ "SSE" ],
- mode => "mode_E",
-},
-
# Load / Store
xLoad => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
emit => '. mov%XXM %AM, %D0',
+ attr => "ir_mode *load_mode",
+ init_attr => "attr->ls_mode = load_mode;",
outs => [ "res", "M" ],
- latency => 2,
+ latency => 0,
units => [ "SSE" ],
},
op_flags => "L|F",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
- emit => '. mov%XXM %binop',
- latency => 2,
+ emit => '. mov%XXM %S2, %AM',
+ latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
ins => [ "base", "index", "val", "mem" ],
emit => '. mov%XXM %S2, %AM',
- latency => 2,
+ latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
arity => 3,
},
-GetST0 => {
- op_flags => "L|F",
- irn_flags => "I",
- state => "pinned",
- reg_req => { in => [ "gp", "gp", "none" ] },
- emit => '. fstp%XM %AM',
- latency => 4,
- units => [ "SSE" ],
- mode => "mode_M",
-},
-
-SetST0 => {
- op_flags => "L|F",
- irn_flags => "I",
- state => "pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] },
- ins => [ "base", "index", "mem" ],
- emit => '. fld%XM %AM',
- outs => [ "res", "M" ],
- latency => 2,
- units => [ "SSE" ],
-},
-
# CopyB
CopyB => {
# Conversions
Conv_I2I => {
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
- units => [ "GP" ],
- ins => [ "base", "index", "val", "mem" ],
- mode => $mode_gp,
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ units => [ "GP" ],
+ ins => [ "base", "index", "val", "mem" ],
+ attr => "ir_mode *smaller_mode",
+ init_attr => "attr->ls_mode = smaller_mode;",
+ mode => $mode_gp,
modified_flags => $status_flags
},
Conv_I2I8Bit => {
- reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
- ins => [ "base", "index", "val", "mem" ],
- units => [ "GP" ],
- mode => $mode_gp,
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ units => [ "GP" ],
+ attr => "ir_mode *smaller_mode",
+ init_attr => "attr->ls_mode = smaller_mode;",
+ mode => $mode_gp,
modified_flags => $status_flags
},
mode => $mode_gp,
},
-TestCMov => {
+CmpCMov8Bit => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
mode => $mode_gp,
},
+TestCMov => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 2,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+TestCMov8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 2,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
xCmpCMov => {
irn_flags => "R",
reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
vfCmpCMov => {
irn_flags => "R",
- reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
latency => 10,
- units => [ "VFP" ],
+ units => [ "VFP", "GP" ],
mode => $mode_gp,
attr_type => "ia32_x87_attr_t",
},
CmpSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 2,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+CmpSet8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "eax ebx ecx edx",
+ "none" ],
+ out => [ "eax ebx ecx edx" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
TestSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
+ latency => 2,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+TestSet8Bit => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "eax ebx ecx edx",
+ "none" ],
+ out => [ "eax ebx ecx edx" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
ins => [ "base", "index", "mem" ],
outs => [ "res", "M" ],
- attr => "ir_mode *store_mode",
- init_attr => "attr->attr.ls_mode = store_mode;",
+ attr => "ir_mode *load_mode",
+ init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
attr_type => "ia32_x87_attr_t",
},
-vfConst => {
- op_flags => "c",
- irn_flags => "R",
- reg_req => { out => [ "vfp" ] },
- latency => 3,
- units => [ "VFP" ],
- mode => "mode_E",
- attr_type => "ia32_x87_attr_t",
-},
-
# other
-vfCondJmp => {
+vfCmpJmp => {
state => "pinned",
op_flags => "L|X|Y",
reg_req => { in => [ "vfp", "vfp" ], out => [ "none", "none", "eax" ] },
op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fild%XM %AM',
+ emit => '. fild%M %AM',
attr_type => "ia32_x87_attr_t",
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fist%XM %AM',
+ emit => '. fist%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fistp%XM %AM',
+ emit => '. fistp%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
projects / libfirm / blobdiff