Remove ia32_Sub64Bit. Replace it by Sub and Sbb.

[libfirm] / ir / be / ia32 / ia32_spec.pl

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 1865057..dc0c49d 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -364,7 +364,7 @@ ProduceVal => {
 
 Add => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. add%M %binop',
        am        => "full,binary",
@@ -394,7 +394,7 @@ AddMem8Bit => {
 },
 
 Adc => {
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right", "eflags" ],
        emit      => '. adc%M %binop',
        am        => "full,binary",
@@ -438,7 +438,7 @@ l_Mul => {
 
 IMul => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. imul%M %binop',
        am        => "source,binary",
@@ -471,7 +471,7 @@ l_IMul => {
 
 And => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        am        => "full,binary",
        emit      => '. and%M %binop',
@@ -502,7 +502,7 @@ AndMem8Bit => {
 
 Or => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        am        => "full,binary",
        emit      => '. or%M %binop',
@@ -533,7 +533,7 @@ OrMem8Bit => {
 
 Xor => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        am        => "full,binary",
        emit      => '. xor%M %binop',
@@ -566,7 +566,7 @@ XorMem8Bit => {
 
 Sub => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        am        => "full,binary",
        emit      => '. sub%M %binop',
@@ -596,8 +596,8 @@ SubMem8Bit => {
 },
 
 Sbb => {
-       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 !in_r5" ] },
-       ins       => [ "base", "index", "mem", "left", "right" ],
+       reg_req   => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] },
+       ins       => [ "base", "index", "mem", "left", "right", "eflags" ],
        am        => "full,binary",
        emit      => '. sbb%M %binop',
        units     => [ "GP" ],
@@ -605,19 +605,14 @@ Sbb => {
        modified_flags => $status_flags
 },
 
-Sub64Bit => {
-       irn_flags => "R",
-       arity     => 4,
-       reg_req   => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
-       emit      => '
-. movl %S0, %D0
-. movl %S1, %D1
-. subl %SI2, %D0
-. sbbl %SI3, %D1
-',
-       outs      => [ "low_res", "high_res" ],
-       units     => [ "GP" ],
-       modified_flags => $status_flags
+l_Sub => {
+       reg_req   => { in => [ "none", "none" ], out => [ "none" ] },
+       ins       => [ "left", "right" ],
+},
+
+l_Sbb => {
+       reg_req   => { in => [ "none", "none", "none" ], out => [ "none" ] },
+       ins       => [ "left", "right", "eflags" ],
 },
 
 IDiv => {
@@ -1339,7 +1334,7 @@ xZero => {
 
 xAdd => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. add%XXM %binop',
        latency   => 4,
@@ -1349,7 +1344,7 @@ xAdd => {
 
 xMul => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. mul%XXM %binop',
        latency   => 4,
@@ -1359,7 +1354,7 @@ xMul => {
 
 xMax => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. max%XXM %binop',
        latency   => 2,
@@ -1369,7 +1364,7 @@ xMax => {
 
 xMin => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. min%XXM %binop',
        latency   => 2,
@@ -1379,7 +1374,7 @@ xMin => {
 
 xAnd => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. andp%XSD %binop',
        latency   => 3,
@@ -1389,7 +1384,7 @@ xAnd => {
 
 xOr => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. orp%XSD %binop',
        units     => [ "SSE" ],
@@ -1398,7 +1393,7 @@ xOr => {
 
 xXor => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
        ins       => [ "base", "index", "mem", "left", "right" ],
        emit      => '. xorp%XSD %binop',
        latency   => 3,