# %nodes = (
#
# <op-name> => {
-# "op_flags" => "N|L|C|X|I|F|Y|H|c",
-# "arity" => "0|1|2|3|variable|dynamic|all",
-# "state" => "floats|pinned",
-# "args" => [
-# { "type" => "type 1", "name" => "name 1" },
-# { "type" => "type 2", "name" => "name 2" },
-# ...
-# ],
-# "comment" => "any comment for constructor",
+# "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
+# "irn_flags" => "R|N|I"
+# "arity" => "0|1|2|3 ... |variable|dynamic|any",
+# "state" => "floats|pinned|mem_pinned|exc_pinned",
+# "args" => [
+# { "type" => "type 1", "name" => "name 1" },
+# { "type" => "type 2", "name" => "name 2" },
+# ...
+# ],
+# "comment" => "any comment for constructor",
+# "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
+# "cmp_attr" => "c source code for comparing node attributes",
+# "emit" => "emit code with templates",
# "rd_constructor" => "c source code which constructs an ir_node"
# },
#
#
# ); # close the %nodes initializer
+# op_flags: flags for the operation, OPTIONAL (default is "N")
# the op_flags correspond to the firm irop_flags:
# N irop_flag_none
# L irop_flag_labeled
# Y irop_flag_forking
# H irop_flag_highlevel
# c irop_flag_constlike
+# K irop_flag_keep
#
-# op_flags: flags for the operation, OPTIONAL (default is "N")
+# irn_flags: special node flags, OPTIONAL (default is 0)
+# following irn_flags are supported:
+# R rematerializeable
+# N not spillable
+# I ignore for register allocation
#
-# state: state of the operation, OPTIONAL (default is "pinned")
+# state: state of the operation, OPTIONAL (default is "floats")
#
# arity: arity of the operation, MUST NOT BE OMITTED
#
#
# NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
+# register types:
+# 0 - no special type
+# 1 - caller save (register must be saved by the caller of a function)
+# 2 - callee save (register must be saved by the called function)
+# 4 - ignore (do not assign this register)
+# NOTE: Last entry of each class is the largest Firm-Mode a register can hold
%reg_classes = (
- "general_purpose" => [
- { "name" => "eax", "type" => 0 },
- { "name" => "ebx", "type" => 0 },
- { "name" => "ecx", "type" => 0 },
- { "name" => "edx", "type" => 0 },
- { "name" => "edi", "type" => 0 },
- { "name" => "esi", "type" => 0 },
- { "name" => "ebp", "type" => 0 }
- ],
- "floating_point" => [
- { "name" => "xmm0", "type" => 0 },
- { "name" => "xmm1", "type" => 0 },
- { "name" => "xmm2", "type" => 0 },
- { "name" => "xmm3", "type" => 0 },
- { "name" => "xmm4", "type" => 0 },
- { "name" => "xmm5", "type" => 0 },
- { "name" => "xmm6", "type" => 0 },
- { "name" => "xmm7", "type" => 0 },
- ]
+ "gp" => [
+ { "name" => "eax", "type" => 1 },
+ { "name" => "edx", "type" => 1 },
+ { "name" => "ebx", "type" => 2 },
+ { "name" => "ecx", "type" => 1 },
+ { "name" => "esi", "type" => 2 },
+ { "name" => "edi", "type" => 2 },
+ { "name" => "ebp", "type" => 2 },
+ { "name" => "esp", "type" => 6 },
+ { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
+ { "mode" => "mode_P" }
+ ],
+ "fp" => [
+ { "name" => "xmm0", "type" => 1 },
+ { "name" => "xmm1", "type" => 1 },
+ { "name" => "xmm2", "type" => 1 },
+ { "name" => "xmm3", "type" => 1 },
+ { "name" => "xmm4", "type" => 1 },
+ { "name" => "xmm5", "type" => 1 },
+ { "name" => "xmm6", "type" => 1 },
+ { "name" => "xmm7", "type" => 1 },
+ { "name" => "xxxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
+ { "mode" => "mode_D" }
+ ]
); # %reg_classes
#--------------------------------------------------#
# commutative operations
-"Add" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. addl %S2, %D1\t\t\t/* Add(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
+# NOTE:
+# All nodes supporting Addressmode have 5 INs:
+# 1 - base r1 == NoReg in case of no AM or no base
+# 2 - index r2 == NoReg in case of no AM or no index
+# 3 - op1 r3 == always present
+# 4 - op2 r4 == NoReg in case of immediate operation
+# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
-"Add_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. addl %C, %D1\t\t\t/* Add(%C, %S1) -> %D1, (%A1, const) */'
+"Add" => {
+ "irn_flags" => "R",
+ "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. add %ia32_emit_binop\t\t\t/* Add(%A1, %A2) -> %D1 */'
},
"Mul" => {
- "op_flags" => "C",
- "arity" => 2,
- "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
- "reg_req" => { "in" => [ "out_d1", "general_purpose" ], "out" => [ "eax" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %S2\t\t\t/* signed Mul(%S1, %S2) -> %D1, (%A1, %A2) */
- }
- else {
-4. mull %S2\t\t\t/* unsigned Mul(%S1, %S2) -> %D1, (%A1, %A2) */
- }
-'
-},
-
-"Mul_i" => {
- "state" => "pinned",
- "arity" => 1,
- "comment" => "construct Mul: Mul(a, const) = Mul(const, a) = a * const",
- "reg_req" => { "in" => [ "out_d1" ], "out" => [ "eax" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %C\t\t\t/* signed Mul(%C, %S1) -> %D1, (%A1, const) */
- }
- else {
-4. mull %C\t\t\t/* unsigned Mul(%C, %S1) -> %D1, (%A1, const) */
- }
-'
+ "irn_flags" => "A",
+ "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. imul %ia32_emit_binop\t\t\t/* Mul(%A1, %A2) -> %D1 */'
},
+# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
"Mulh" => {
- "op_flags" => "C",
- "arity" => 2,
- "comment" => "construct Mulh: Mulh(a, b) = Mulh(b, a) = get_32_highest_bits(a * b)",
- "reg_req" => { "in" => [ "out_d1", "general_purpose" ], "out" => [ "edx" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %S2\t\t\t/* signed Mulh(%S1, %S2) -> %D1, (%A1, %A2) */
- }
- else {
-4. mull %S2\t\t\t/* unsigned Mulh(%S1, %S2) -> %D1, (%A1, %A2) */
- }
-'
-},
-
-"Mulh_i" => {
- "state" => "pinned",
- "arity" => 1,
- "comment" => "construct Mulh: Mulh(a, const) = Mulh(const, a) = get_32_highest_bits(a * const)",
- "reg_req" => { "in" => [ "out_d1" ], "out" => [ "edx" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %C\t\t\t/* signed Mulh(%C, %S1) -> %D1, (%A1, const) */
- }
- else {
-4. mull %C\t\t\t/* unsigned Mulh(%C, %S1) -> %D1, (%A1, const) */
- }
-'
+ "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r2" ] },
+ "emit" => '. imul %ia32_emit_unop\t\t\t/* Mulh(%A1, %A2) -> %D1 */ '
},
"And" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. andl %S2, %D1\t\t\t/* And(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"And_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct And: And(a, const) = And(const, a) = a AND const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. andl %C, %D1\t\t\t/* And(%C, %S1) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. and %ia32_emit_binop\t\t\t/* And(%A1, %A2) -> %D1 */'
},
"Or" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. orl %S2, %D1\t\t\t/* Or(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Or_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. orl %C, %D1\t\t\t/* Or(%C, %S1) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. or %ia32_emit_binop\t\t\t/* Or(%A1, %A2) -> %D1 */'
},
"Eor" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. xorl %S2, %D1\t\t\t/* Xor(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Eor_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. xorl %C, %D1\t\t\t/* Xor(%C, %S1) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. xor %ia32_emit_binop\t\t\t/* Xor(%A1, %A2) -> %D1 */'
},
"Max" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" =>
-'2. cmpl %S2, %S1\t\t\t/* prepare Max (%S1 should be %D1), (%A1, %A2) */
+ "irn_flags" => "R",
+ "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
+ "emit" =>
+'2. cmp %S1, %S2\t\t\t/* prepare Max (%S1 - %S2), (%A1, %A2) */
if (mode_is_signed(get_irn_mode(n))) {
-4. cmovl %S2, %D1\t\t\t/* %S1 is less %S2 */
+4. cmovl %D1, %S2\t\t\t/* %S1 is less %S2 */
}
else {
-4. cmovb %S2, %D1\t\t\t/* %S1 is below %S2 */
+4. cmovb %D1, %S2\t\t\t/* %S1 is below %S2 */
}
'
},
"Min" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" =>
-'2. cmpl %S2, %S1\t\t\t/* prepare Min (%S1 should be %D1), (%A1, %A2) */
+ "irn_flags" => "R",
+ "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
+ "emit" =>
+'2. cmp %S1, %S2\t\t\t/* prepare Min (%S1 - %S2), (%A1, %A2) */
if (mode_is_signed(get_irn_mode(n))) {
-2. cmovg %S2, %D1\t\t\t/* %S1 is greater %S2 */
+2. cmovg %D1, %S2\t\t\t/* %S1 is greater %S2 */
}
else {
-2. cmova %S2, %D1\t\t\t/* %S1 is above %S2 */
+2. cmova %D1, %S2, %D1\t\t\t/* %S1 is above %S2 */
}
'
},
+"CMov" => {
+ "irn_flags" => "R",
+ "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
+ "emit" =>
+'. cmp %S1, 0\t\t\t/* compare Sel for CMov (%A2, %A3) */
+. cmovne %D1, %S3\t\t\t/* sel == true -> return %S3 */
+'
+},
+
# not commutative operations
"Sub" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Sub: Sub(a, b) = a - b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. subl %S2, %D1\t\t\t/* Sub(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Sub_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Sub: Sub(a, const) = a - const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. subl %C, %D1\t\t\t/* Sub(%S1, %C) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct Sub: Sub(a, b) = a - b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. sub %ia32_emit_binop\t\t\t/* Sub(%A1, %A2) -> %D1 */'
},
"DivMod" => {
- "op_flags" => "F|L",
- "state" => "exc_pinned",
- "arity" => 4,
- "comment" => "construct DivMod: DivMod(a,b) = (a / b, a % b)",
- "emit" =>
+ "op_flags" => "F|L",
+ "state" => "exc_pinned",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
+ "emit" =>
' if (mode_is_signed(get_irn_mode(n))) {
-4. idivl %S2\t\t\t/* signed Mod(%S1, %S2) -> %D1, (%A2, %A3, %4) */
+4. idiv %S2\t\t\t/* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
else {
-4. divl %S2\t\t\t/* unsigned Mod(%S1, %S2) -> %D1, (%A2, %A3, %A4) */
+4. div %S2\t\t\t/* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
-',
- "args" => [
- { "type" => "ir_node *", "name" => "dividend" },
- { "type" => "ir_node *", "name" => "divisor" },
- { "type" => "ir_node *", "name" => "mem" },
- { "type" => "divmod_flavour_t", "name" => "dm_flav" }, # flavours (flavour_Div, flavour_Mod, flavour_DivMod)
- { "type" => "ir_mode *", "name" => "mode" },
- ],
- "rd_constructor" =>
-" ir_node *res;
- ir_node *in[4];
- asmop_attr *attr;
-
- if (!op_ia32_DivMod) assert(0);
-
- in[1] = divisor;
- in[3] = mem;
-
- if (mode_is_signed(mode)) {
- ir_node *cltd;
- /* in signed mode , we need to sign extend the dividend */
- cltd = new_rd_ia32_Cltd(db, current_ir_graph, block, divisor, mode_T);
- in[0] = new_rd_Proj(db, current_ir_graph, block, cltd, mode_Is, pn_EAX);
- in[2] = new_rd_Proj(db, current_ir_graph, block, cltd, mode_Is, pn_EDX);
- }
- else {
- in[0] = dividend;
- in[2] = new_rd_ia32_Const(db, current_ir_graph, block, mode_Iu);
- set_ia32_Const_type(in[2], asmop_Const);
- set_ia32_Immop_tarval(in[2], get_tarval_null(mode_Iu));
- }
-
- res = new_ir_node(db, irg, block, op_ia32_DivMod, mode, 4, in);
-
- set_ia32_DivMod_flavour(res, dm_flav);
- set_ia32_n_res(res, 2);
-
- attr = get_ia32_attr(res);
-
- attr->in_req = calloc(4, sizeof(arch_register_req_t *));
- attr->in_req[0] = &ia32_default_req_ia32_general_purpose_eax;
- attr->in_req[1] = &ia32_default_req_ia32_general_purpose;
- attr->in_req[2] = &ia32_default_req_ia32_general_purpose_edx;
- attr->in_req[3] = &ia32_default_req_none;
-
- attr->out_req = calloc(2, sizeof(arch_register_req_t *));
- attr->out_req[0] = &ia32_default_req_ia32_general_purpose_eax;
- attr->out_req[1] = &ia32_default_req_ia32_general_purpose_edx;
-
- attr->slots = calloc(2, sizeof(arch_register_t *));
-
- return res;
-"
+'
},
"Shl" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Shl: Shl(a, b) = a << b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shll %S2, %D1\t\t\t/* Shl(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Shl_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Shl: Shl(a, const) = a << const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shll %C, %D1\t\t\t/* Shl(%S1, %C) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct Shl: Shl(a, b) = a << b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. shl %ia32_emit_binop\t\t\t/* Shl(%A1, %A2) -> %D1 */'
},
"Shr" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Shr: Shr(a, b) = a >> b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shrl %S2, %D1\t\t\t/* Shr(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Shr_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Shr: Shr(a, const) = a >> const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shrl %C, %D1\t\t\t/* Shr(%S1, %C) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct Shr: Shr(a, b) = a >> b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. shr %ia32_emit_binop\t\t\t/* Shr(%A1, %A2) -> %D1 */'
},
"Shrs" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Shrs: Shrs(a, b) = a >> b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. sarl %S2, %D1\t\t\t/* Shrs(%S1, %S2) -> %D1, (%A1, %A2) */'
-},
-
-"Shrs_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Shrs: Shrs(a, const) = a >> const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. sarl %C, %D1\t\t\t/* Shrs(%S1, %C) -> %D1, (%A1, const) */'
+ "irn_flags" => "R",
+ "comment" => "construct Shrs: Shrs(a, b) = a >> b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. sar %ia32_emit_binop\t\t\t/* Shrs(%A1, %A2) -> %D1 */'
},
"RotR" => {
- "arity" => 2,
- "remat" => 1,
+ "irn_flags" => "R",
"comment" => "construct RotR: RotR(a, b) = a ROTR b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. rorl %S2, %D1\t\t\t/* RotR(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. ror %ia32_emit_binop\t\t\t/* RotR(%A1, %A2) -> %D1 */'
},
"RotL" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct RotL: RotL(a, b) = a ROTL b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. roll %S2, %D1\t\t\t/* RotL(%S1, %S2) -> %D1, (%A1, %A2) */'
+ "irn_flags" => "R",
+ "comment" => "construct RotL: RotL(a, b) = a ROTL b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. rol %ia32_emit_binop\t\t\t/* RotL(%A1, %A2) -> %D1 */'
},
-"RotL_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct RotL: RotL(a, const) = a ROTL const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. roll %C, %D1\t\t\t/* RotL(%S1, %C) -> %D1, (%A1, const) */'
-},
+# unary operations
"Minus" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Minus: Minus(a) = -a",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. negl %D1\t\t\t/* Neg(%S1) -> %D1, (%A1) */'
+ "irn_flags" => "R",
+ "comment" => "construct Minus: Minus(a) = -a",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. neg %ia32_emit_unop\t\t\t/* Neg(%A1) -> %D1, (%A1) */'
},
"Inc" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Increment: Inc(a) = a++",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. incl %D1\t\t\t/* Inc(%S1) -> %D1, (%A1) */'
+ "irn_flags" => "R",
+ "comment" => "construct Increment: Inc(a) = a++",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. inc %ia32_emit_unop\t\t\t/* Inc(%S1) -> %D1, (%A1) */'
},
"Dec" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Decrement: Dec(a) = a--",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. decl %D1\t\t\t/* Dec(%S1) -> %D1, (%A1) */'
+ "irn_flags" => "R",
+ "comment" => "construct Decrement: Dec(a) = a--",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. dec %ia32_emit_unop\t\t\t/* Dec(%S1) -> %D1, (%A1) */'
},
"Not" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Not: Not(a) = !a",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. notl %D1\t\t\t/* Not(%S1) -> %D1, (%A1) */'
+ "irn_flags" => "R",
+ "comment" => "construct Not: Not(a) = !a",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. not %ia32_emit_unop\t\t\t/* Not(%S1) -> %D1, (%A1) */'
},
# other operations
"Conv" => {
- "arity" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
+ "reg_req" => { "in" => [ "gp" ], "out" => [ "in_r1" ] },
"comment" => "construct Conv: Conv(a) = (conv)a"
},
"CondJmp" => {
- "op_flags" => "C|L|X|Y",
- "arity" => 2,
- "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "none", "none" ] },
-},
-
-"CondJmp_i" => {
- "op_flags" => "L|X|Y",
- "arity" => 1,
- "comment" => "construct conditional jump: CMP A, const && JMPxx LABEL",
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "none", "none" ] },
+ "op_flags" => "L|X|Y",
+ "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
},
"SwitchJmp" => {
- "op_flags" => "L|X|Y",
- "arity" => 1,
- "comment" => "construct switch",
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "none" ] },
+ "op_flags" => "L|X|Y",
+ "comment" => "construct switch",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "none" ] },
},
"Const" => {
- "op_flags" => "c",
- "arity" => "0",
- "remat" => 1,
- "comment" => "represents an integer constant",
- "reg_req" => { "out" => [ "general_purpose" ] },
- "emit" => '. movl %C, %D1\t\t\t/* Mov Const into register */',
- "cmp_attr" =>
+ "op_flags" => "c",
+ "irn_flags" => "R",
+ "comment" => "represents an integer constant",
+ "reg_req" => { "out" => [ "gp" ] },
+ "emit" => '. mov %D1, %C\t\t\t/* Mov Const into register */',
+ "cmp_attr" =>
'
- if (attr_a->tp == attr_b->tp) {
- if (attr_a->tp == asmop_SymConst) {
- if (attr_a->old_ir == NULL || attr_b->old_ir == NULL)
+ if (attr_a->data.tp == attr_b->data.tp) {
+ if (attr_a->data.tp == ia32_SymConst) {
+ if (attr_a->sc == NULL || attr_b->sc == NULL)
return 1;
else
- return strcmp(get_sc_name(attr_a->old_ir), get_sc_name(attr_b->old_ir));
+ return strcmp(attr_a->sc, attr_b->sc);
}
else {
- if (attr_a->old_ir == NULL || attr_b->old_ir == NULL)
+ if (attr_a->tv == NULL || attr_b->tv == NULL)
return 1;
if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
'
},
-"Cltd" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Cltd: sign extend EAX -> EDX:EAX",
- "reg_req" => { "in" => [ "out_d1" ], "out" => [ "eax", "edx" ] },
- "emit" => '. cltd\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */'
+"Cdq" => {
+ "irn_flags" => "R",
+ "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
+ "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
+ "emit" => '. cdq\t\t\t/* sign extend EAX -> EDX:EAX, (%A1) */'
},
# Load / Store
"Load" => {
- "op_flags" => "L|F",
- "state" => "exc_pinned",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
- "reg_req" => { "in" => [ "general_purpose", "none" ], "out" => [ "general_purpose" ] },
- "emit" => '. movl (%S1), %D1\t\t\t/* Load((%S1)) -> %D1, (%A1) */'
+ "op_flags" => "L|F",
+ "irn_flags" => "R",
+ "state" => "exc_pinned",
+ "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
+ "emit" => '. mov %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
},
"Store" => {
- "op_flags" => "L|F",
- "state" => "exc_pinned",
- "arity" => 3,
- "remat" => 1,
- "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose", "none" ] },
- "emit" => '. movl %S2, (%S1)\t\t\t/* Store(%S2) -> (%S1), (%A1, %A2) */'
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
+ "emit" => '. mov %ia32_emit_am, %S3\t\t\t/* Store(%A2) -> (%A1) */'
},
"Lea" => {
- "arity" => 2,
- "comment" => "construct Lea: Lea(a,b) = lea offs(a,b,const) | res = a + b * const + offs with const = 0,1,2,4,8",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
- "emit" => '. leal %O(%S1, %S2, %C), %D1\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */'
-},
-
-"Lea_i" => {
- "arity" => 1,
- "comment" => "construct Lea: Lea(a) = lea offs(a) | res = a + offs",
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
- "emit" => '. leal %C(%S1), %D1\t\t\t/* %D1 = %S1 + %C, (%A1)*/'
-},
-
-"RegParam" => {
- "arity" => 1,
- "comment" => "constructs a Register Parameter to cover parameters passed in register",
- "reg_req" => { "in" => [ "none" ], "out" => [ "none" ] },
- "cmp_attr" =>
-'
- return (attr_a->pn_code != attr_b->pn_code);
-'
-},
-
-"StackParam" => {
- "arity" => 1,
- "comment" => "constructs a Stack Parameter to retrieve a parameter from Stack",
- "reg_req" => { "in" => [ "none" ], "out" => [ "general_purpose" ] },
- "cmp_attr" =>
-'
- return (attr_a->pn_code != attr_b->pn_code);
-'
-},
-
-"StackArg" => {
- "arity" => 2,
- "comment" => "constructs a Stack Argument to pass an argument on Stack",
- "reg_req" => { "in" => [ "none", "general_purpose" ], "out" => [ "none" ] },
- "cmp_attr" =>
-'
- return (attr_a->pn_code != attr_b->pn_code);
-'
+ "irn_flags" => "R",
+ "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+ "emit" => '. lea %D1, %ia32_emit_am\t\t/* %D1 = %S1 + %S2 << %C + %O, (%A1, %A2) */'
},
#--------------------------------------------------------#
# commutative operations
"fAdd" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "check_inout" => 1,
- "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
- "reg_req" => { "in" => [ "floating_point", "floating_point" ], "out" => [ "in_s1" ] },
- "emit" => '. add%M %S2, %D1\t\t\t/* SSE Add(%S1, %S2) -> %D1 */'
+ "irn_flags" => "R",
+ "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. adds%M %ia32_emit_binop\t\t\t/* SSE Add(%A1, %A2) -> %D1 */'
},
"fMul" => {
- "op_flags" => "C",
- "arity" => 2,
- "check_inout" => 1,
- "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
- "reg_req" => { "in" => [ "floating_point", "floating_point" ], "out" => [ "in_s1" ] },
- "emit" =>'. muls%M %S2, %D1\t\t\t/* SSE Mul(%S1, %S2) -> %D1 */'
+ "irn_flags" => "R",
+ "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. muls%M %ia32_emit_binop\t\t\t/* SSE Mul(%A1, %A2) -> %D1 */'
},
"fMax" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "check_inout" => 1,
- "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
- "reg_req" => { "in" => [ "floating_point", "floating_point" ], "out" => [ "in_s1" ] },
- "emit" =>'. maxs%M %S2, %D1\t\t\t/* SSE Max(%S1, %S2) -> %D1 */'
+ "irn_flags" => "R",
+ "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. maxs%M %ia32_emit_binop\t\t\t/* SSE Max(%A1, %A2) -> %D1 */'
},
"fMin" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "check_inout" => 1,
- "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
- "reg_req" => { "in" => [ "floating_point", "floating_point" ], "out" => [ "in_s1" ] },
- "emit" =>'. mins%M %S2, %D1\t\t\t/* SSE Min(%S1, %S2) -> %D1 */'
+ "irn_flags" => "R",
+ "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. mins%M %ia32_emit_binop\t\t\t/* SSE Min(%A1, %A2) -> %D1 */'
+},
+
+"fAnd" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE And: And(a, b) = a AND b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. andp%M %ia32_emit_binop\t\t\t/* SSE And(%A3, %A4) -> %D1 */'
+},
+
+"fOr" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Or: Or(a, b) = a OR b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. orp%M %ia32_emit_binop\t\t\t/* SSE Or(%A3, %A4) -> %D1 */'
+},
+
+"fEor" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. xorp%M %ia32_emit_binop\t\t\t/* SSE Xor(%A3, %A4) -> %D1 */'
},
# not commutative operations
"fSub" => {
- "arity" => 2,
- "remat" => 1,
- "check_inout" => 1,
- "comment" => "construct SSE Sub: Sub(a, b) = a - b",
- "reg_req" => { "in" => [ "floating_point", "floating_point" ], "out" => [ "in_s1" ] },
- "emit" => '. subs%M %S2, %D1\t\t\t/* SSE Sub(%S1, %S2) -> %D1 */'
+ "irn_flags" => "R",
+ "comment" => "construct SSE Sub: Sub(a, b) = a - b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. subs%M %ia32_emit_binop\t\t\t/* SSE Sub(%A1, %A2) -> %D1 */'
},
"fDiv" => {
- "arity" => 2,
- "remat" => 1,
- "check_inout" => 1,
- "comment" => "construct SSE Div: Div(a, b) = a / b",
- "reg_req" => { "in" => [ "floating_point", "floating_point" ], "out" => [ "in_s1" ] },
- "emit" => '. divs%M %S2, %D1\t\t\t/* SSE Div(%S1, %S2) -> %D1 */'
-},
-
-"fMinus" => {
- "arity" => 1,
- "remat" => 1,
- "check_inout" => 1,
- "comment" => "construct SSE Minus: Minus(a) = -a",
- "reg_req" => { "in" => [ "floating_point" ], "out" => [ "in_s1" ] },
- "emit" => '. xorp%M c %D1\t\t\t/* SSE Minus(%S1) -> %D1 */'
+ "irn_flags" => "R",
+ "comment" => "construct SSE Div: Div(a, b) = a / b",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r1" ] },
+ "emit" => '. divs%M %ia32_emit_binop\t\t\t/* SSE Div(%A1, %A2) -> %D1 */'
},
# other operations
"fConv" => {
- "arity" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
+ "reg_req" => { "in" => [ "fp" ], "out" => [ "gp" ] },
"comment" => "construct Conv: Conv(a) = (conv)a"
},
"fCondJmp" => {
- "op_flags" => "C|L|X|Y",
- "arity" => 2,
- "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "none", "none" ] },
+ "op_flags" => "L|X|Y",
+ "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
},
"fConst" => {
- "op_flags" => "c",
- "arity" => "0",
- "remat" => 1,
- "comment" => "represents a SSE constant",
- "reg_req" => { "out" => [ "floating_point" ] },
- "emit" => '. mov%M %C, %D1\t\t\t/* Mov fConst into register */',
- "cmp_attr" =>
+ "op_flags" => "c",
+ "irn_flags" => "R",
+ "comment" => "represents a SSE constant",
+ "reg_req" => { "out" => [ "fp" ] },
+ "emit" => '. mov%M %D1, %C\t\t\t/* Load fConst into register */',
+ "cmp_attr" =>
'
- if (attr_a->tp == attr_b->tp) {
- if (attr_a->tp == asmop_SymConst) {
- if (attr_a->old_ir == NULL || attr_b->old_ir == NULL)
+ if (attr_a->data.tp == attr_b->data.tp) {
+ if (attr_a->data.tp == ia32_SymConst) {
+ if (attr_a->sc == NULL || attr_b->sc == NULL)
return 1;
else
- return strcmp(get_sc_name(attr_a->old_ir), get_sc_name(attr_b->old_ir));
+ return strcmp(attr_a->sc, attr_b->sc);
}
else {
- if (attr_a->old_ir == NULL || attr_b->old_ir == NULL)
+ if (attr_a->tv == NULL || attr_b->tv == NULL)
return 1;
if (tarval_cmp(attr_a->tv, attr_b->tv) == pn_Cmp_Eq)
# Load / Store
"fLoad" => {
- "op_flags" => "L|F",
- "state" => "exc_pinned",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
- "reg_req" => { "in" => [ "general_purpose", "none" ], "out" => [ "floating_point" ] },
- "emit" => '. movl (%S1), %D1\t\t\t/* Load((%S1)) -> %D1 */'
+ "op_flags" => "L|F",
+ "irn_flags" => "R",
+ "state" => "exc_pinned",
+ "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
+ "emit" => '. movs%M %D1, %ia32_emit_am\t\t\t/* Load((%A1)) -> %D1 */'
},
"fStore" => {
"op_flags" => "L|F",
"state" => "exc_pinned",
- "arity" => 3,
- "remat" => 1,
"comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
- "reg_req" => { "in" => [ "general_purpose", "floating_point", "none" ] },
- "emit" => '. movl %S2, (%S1)\t\t\t/* Store(%S2) -> (%S1), (%A1, %A2) */'
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
+ "emit" => '. movs%M %ia32_emit_am, %S3\t\t\t/* Store(%S3) -> (%A1) */'
},
-"fStackParam" => {
- "arity" => 1,
- "comment" => "constructs a Stack Parameter to retrieve a SSE parameter from Stack",
- "reg_req" => { "in" => [ "none" ], "out" => [ "floating_point" ] },
- "cmp_attr" =>
-'
- return (attr_a->pn_code != attr_b->pn_code);
-'
+# CopyB
+
+"CopyB" => {
+ "op_flags" => "F|H",
+ "state" => "pinned",
+ "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
+ "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
},
-"fStackArg" => {
- "arity" => 2,
- "comment" => "constructs a Stack Argument to pass an argument on Stack",
- "reg_req" => { "in" => [ "none", "floating_point" ], "out" => [ "none" ] },
- "cmp_attr" =>
-'
- return (attr_a->pn_code != attr_b->pn_code);
-'
+"CopyB_i" => {
+ "op_flags" => "F|H",
+ "state" => "pinned",
+ "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
+ "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
},
# Call
"op_flags" => "L|F",
"state" => "mem_pinned",
"arity" => "variable",
- "spill" => 0,
"comment" => "construct Call: Call(...)",
"args" => [
{ "type" => "int", "name" => "n" },
" if (!op_ia32_Call) assert(0);
return new_ir_node(db, irg, block, op_ia32_Call, mode_T, n, in);
"
-}
+},
); # end of %nodes
projects / libfirm / blobdiff