# init_attr => "emit attribute initialization template"
# rd_constructor => "c source code which constructs an ir_node"
# latency => "latency of this operation (can be float)"
+# attr_type => "name of the attribute struct",
# },
#
# ... # (all nodes you need to describe)
S3 => "${arch}_emit_source_register(env, node, 3);",
S4 => "${arch}_emit_source_register(env, node, 4);",
S5 => "${arch}_emit_source_register(env, node, 5);",
+ SB0 => "${arch}_emit_8bit_source_register(env, node, 0);",
+ SW0 => "${arch}_emit_16bit_source_register(env, node, 0);",
D0 => "${arch}_emit_dest_register(env, node, 0);",
D1 => "${arch}_emit_dest_register(env, node, 1);",
D2 => "${arch}_emit_dest_register(env, node, 2);",
XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
AM => "${arch}_emit_am(env, node);",
- unop => "${arch}_emit_unop(env, node);",
+ unop0 => "${arch}_emit_unop(env, node, 0);",
+ unop1 => "${arch}_emit_unop(env, node, 1);",
+ unop2 => "${arch}_emit_unop(env, node, 2);",
+ unop3 => "${arch}_emit_unop(env, node, 3);",
+ unop4 => "${arch}_emit_unop(env, node, 4);",
+ DAM0 => "${arch}_emit_am_or_dest_register(env, node, 0);",
+ DAM1 => "${arch}_emit_am_or_dest_register(env, node, 0);",
binop => "${arch}_emit_binop(env, node);",
x87_binop => "${arch}_emit_x87_binop(env, node);",
);
# |_| #
#--------------------------------------------------#
-$default_cmp_attr = "return ia32_compare_attr(attr_a, attr_b);";
$default_attr_type = "ia32_attr_t";
+$default_copy_attr = "ia32_copy_attr";
%init_attr = (
ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);",
ia32_asm_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
"\tinit_ia32_x87_attributes(res);".
- "\tinit_ia32_asm_attributes(res);"
+ "\tinit_ia32_asm_attributes(res);",
+ ia32_immediate_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
+ "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);"
);
%compare_attr = (
- ia32_attr_t => "return ia32_compare_attr(attr_a, attr_b);",
- ia32_x87_attr_t => "return ia32_compare_x87_attr(attr_a, attr_b);",
- ia32_asm_attr_t => "return ia32_compare_asm_attr(attr_a, attr_b);"
+ ia32_attr_t => "ia32_compare_nodes_attr",
+ ia32_x87_attr_t => "ia32_compare_x87_attr",
+ ia32_asm_attr_t => "ia32_compare_asm_attr",
+ ia32_immediate_attr_t => "ia32_compare_immediate_attr",
);
%operands = (
op_flags => "c",
irn_flags => "I",
reg_req => { out => [ "gp_NOREG" ] },
+ attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr_type => "ia32_immediate_attr_t",
+ latency => 0,
mode => $mode_gp,
},
arity => "variable",
out_arity => "variable",
attr_type => "ia32_asm_attr_t",
+ latency => 100,
+},
+
+ProduceVal => {
+ op_flags => "c",
+ irn_flags => "R",
+ reg_req => { out => [ "gp" ] },
+ emit => "",
+ units => [ ],
+ latency => 0,
+ mode => $mode_gp,
+ cmp_attr => "return 1;",
},
#-----------------------------------------------------------------#
# we should not rematrialize this node. It produces 2 results and has
# very strict constrains
reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- emit => '. mul%M %unop',
+ emit => '. mul%M %unop3',
outs => [ "EAX", "EDX", "M" ],
+ ins => [ "base", "index", "val_high", "val_low", "mem" ],
latency => 10,
units => [ "GP" ],
modified_flags => $status_flags
IMul1OP => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- emit => '. imul%M %unop',
+ emit => '. imul%M %unop3',
outs => [ "EAX", "EDX", "M" ],
+ ins => [ "base", "index", "val_high", "val_low", "mem" ],
latency => 5,
units => [ "GP" ],
modified_flags => $status_flags
reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
attr => "ia32_op_flavour_t dm_flav",
init_attr => "attr->data.op_flav = dm_flav;",
- emit => ". idiv%M %unop",
+ emit => ". idiv%M %unop4",
outs => [ "div_res", "mod_res", "M" ],
latency => 25,
units => [ "GP" ],
reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
attr => "ia32_op_flavour_t dm_flav",
init_attr => "attr->data.op_flav = dm_flav;",
- emit => ". div%M %unop",
+ emit => ". div%M %unop4",
outs => [ "div_res", "mod_res", "M" ],
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
},
-l_Shl => {
+l_ShlDep => {
cmp_attr => "return 1;",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShlD => {
- irn_flags => "R",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
- # this Shift and the only value dying is the ShiftCount. Then there would be
- # a register missing, as result must not be ecx and all other registers are
- # occupied. What we should write is "!in_r4 !in_r5", but this is not
- # supported (and probably never will). So we create artificial interferences
- # of the result with all inputs, so the spiller can always assure a free
- # register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+ # this Shift and the only value dying is the ShiftCount. Then there would be a
+ # register missing, as result must not be ecx and all other registers are
+ # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+ # (and probably never will). So we create artificial interferences of the result
+ # with all inputs, so the spiller can always assure a free register.
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
emit =>
'
if (get_ia32_immop_type(node) == ia32_ImmNone) {
modified_flags => $status_flags
},
-l_Shr => {
+l_ShrDep => {
cmp_attr => "return 1;",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShrD => {
- irn_flags => "R",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
emit => '
if (get_ia32_immop_type(node) == ia32_ImmNone) {
if (get_ia32_op_type(node) == ia32_AddrModeD) {
l_Sar => {
cmp_attr => "return 1;",
+ # value, cnt
arity => 2
},
+l_SarDep => {
+ cmp_attr => "return 1;",
+ # value, cnt, dependency
+ arity => 3
+},
+
Ror => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
Neg => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. neg%M %unop',
+ emit => '. neg%M %unop2',
+ ins => [ "base", "index", "val", "mem" ],
units => [ "GP" ],
mode => $mode_gp,
modified_flags => $status_flags
Inc => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. inc%M %unop',
+ emit => '. inc%M %unop2',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
Dec => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. dec%M %unop',
+ emit => '. dec%M %unop2',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
Not => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. not%M %unop',
+ ins => [ "base", "index", "val", "mem" ],
+ emit => '. not%M %unop2',
units => [ "GP" ],
mode => $mode_gp,
modified_flags => []
CondJmp => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none"] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "none", "none"] },
+ ins => [ "base", "index", "left", "right", "mem" ],
outs => [ "false", "true" ],
+ attr => "long pnc",
+ init_attr => "attr->pn_code = pnc;",
latency => 3,
units => [ "BRANCH" ],
},
TestJmp => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp" ], out => [ "none", "none" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "none", "none" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
outs => [ "false", "true" ],
+ attr => "long pnc",
+ init_attr => "attr->pn_code = pnc;",
latency => 3,
units => [ "BRANCH" ],
},
-CJmpAM => {
- state => "pinned",
- op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "none", "none" ] },
- outs => [ "false", "true" ],
- units => [ "BRANCH" ],
-},
-
-CJmp => {
+SwitchJmp => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp" ] },
+ reg_req => { in => [ "gp" ], out => [ "none" ] },
+ latency => 3,
units => [ "BRANCH" ],
+ mode => "mode_T",
},
-SwitchJmp => {
+IJmp => {
state => "pinned",
- op_flags => "L|X|Y",
- reg_req => { in => [ "gp" ], out => [ "none" ] },
- latency => 3,
+ op_flags => "X",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ emit => '. jmp *%unop2',
units => [ "BRANCH" ],
+ mode => "mode_X",
+ modified_flags => []
},
Const => {
FldCW => {
op_flags => "L|F",
- state => "exc_pinned",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
latency => 5,
emit => ". fldcw %AM",
FnstCW => {
op_flags => "L|F",
- state => "exc_pinned",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
latency => 5,
emit => ". fnstcw %AM",
Cltd => {
# we should not rematrialize this node. It produces 2 results and has
# very strict constrains
- reg_req => { in => [ "gp" ], out => [ "eax in_r1", "edx" ] },
+ reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] },
+ ins => [ "val", "globbered" ],
emit => '. cltd',
- outs => [ "EAX", "EDX" ],
+ mode => $mode_gp,
units => [ "GP" ],
},
# Load / Store
+#
+# Note that we add additional latency values depending on address mode, so a
+# lateny of 0 for load is correct
Load => {
op_flags => "L|F",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
- latency => 3,
- emit => ". mov%SE%ME%.l %AM, %D0",
+ ins => [ "base", "index", "mem" ],
outs => [ "res", "M" ],
+ latency => 0,
+ emit => ". mov%SE%ME%.l %AM, %D0",
units => [ "GP" ],
},
op_flags => "L|F",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
emit => '. mov%M %binop',
- latency => 3,
+ latency => 2,
units => [ "GP" ],
mode => "mode_M",
},
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
emit => '. mov%M %binop',
- latency => 3,
+ latency => 2,
units => [ "GP" ],
mode => "mode_M",
},
Lea => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
emit => '. leal %AM, %D0',
latency => 2,
units => [ "GP" ],
Push => {
reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
- emit => '. push%M %unop',
+ emit => '. push%M %unop2',
+ ins => [ "base", "index", "val", "stack", "mem" ],
outs => [ "stack:I|S", "M" ],
- latency => 3,
+ latency => 2,
units => [ "GP" ],
modified_flags => [],
},
Pop => {
reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
- emit => '. pop%M %unop',
+ emit => '. pop%M %DAM1',
outs => [ "stack:I|S", "res", "M" ],
- latency => 4,
+ ins => [ "base", "index", "stack", "mem" ],
+ latency => 3, # Pop is more expensive than Push on Athlon
units => [ "GP" ],
modified_flags => [],
},
AddSP => {
irn_flags => "I",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
emit => '. addl %binop',
outs => [ "stack:S", "M" ],
},
SubSP => {
- irn_flags => "I",
- reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
- emit => '. subl %binop',
- outs => [ "stack:S", "M" ],
+#irn_flags => "I",
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
+ emit => ". subl %binop\n".
+ ". movl %%esp, %D1",
+ outs => [ "stack:I|S", "addr", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
state => "pinned",
op_flags => "L|X|Y",
reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
+ ins => [ "base", "index", "left", "right", "mem" ],
outs => [ "false", "true" ],
+ attr => "long pnc",
+ init_attr => "attr->pn_code = pnc;",
latency => 5,
units => [ "SSE" ],
},
CvtSI2SD => {
op_flags => "L|F",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
- emit => '. cvtsi2sd %unop',
+ emit => '. cvtsi2sd %unop2',
latency => 2,
units => [ "SSE" ],
mode => $mode_xmm
arity => 3,
},
-GetST0 => {
- op_flags => "L|F",
- irn_flags => "I",
- state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ] },
- emit => '. fstp%XM %AM',
- latency => 4,
- units => [ "SSE" ],
- mode => "mode_M",
-},
-
-SetST0 => {
- op_flags => "L|F",
- irn_flags => "I",
- state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vf0", "none" ] },
- ins => [ "base", "index", "mem" ],
- emit => '. fld%XM %AM',
- outs => [ "res", "M" ],
- latency => 2,
- units => [ "SSE" ],
-},
-
# CopyB
CopyB => {
# Conversions
Conv_I2I => {
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
- units => [ "GP" ],
- mode => $mode_gp,
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ units => [ "GP" ],
+ ins => [ "base", "index", "val", "mem" ],
+ attr => "ir_mode *smaller_mode",
+ init_attr => "attr->ls_mode = smaller_mode;",
+ mode => $mode_gp,
modified_flags => $status_flags
},
Conv_I2I8Bit => {
- reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
- units => [ "GP" ],
- mode => $mode_gp,
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ units => [ "GP" ],
+ attr => "ir_mode *smaller_mode",
+ init_attr => "attr->ls_mode = smaller_mode;",
+ mode => $mode_gp,
modified_flags => $status_flags
},
CmpCMov => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
latency => 2,
units => [ "GP" ],
mode => $mode_gp,
},
-PsiCondCMov => {
+TestCMov => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp" ], out => [ "in_r3" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
latency => 2,
units => [ "GP" ],
mode => $mode_gp,
vfCmpCMov => {
irn_flags => "R",
- reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
latency => 10,
- units => [ "VFP" ],
+ units => [ "VFP", "GP" ],
mode => $mode_gp,
attr_type => "ia32_x87_attr_t",
},
CmpSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
latency => 2,
units => [ "GP" ],
mode => $mode_gp,
},
-PsiCondSet => {
+TestSet => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
+ attr => "pn_Cmp pn_code",
+ init_attr => "attr->pn_code = pn_code;",
latency => 2,
units => [ "GP" ],
mode => $mode_gp,
vfadd => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfmul => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfsub => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
},
vfdiv => {
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
outs => [ "res", "M" ],
latency => 20,
units => [ "VFP" ],
},
vfprem => {
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
latency => 20,
units => [ "VFP" ],
mode => "mode_E",
vfabs => {
irn_flags => "R",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ ins => [ "value" ],
latency => 2,
units => [ "VFP" ],
mode => "mode_E",
vfchs => {
irn_flags => "R",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
+ ins => [ "value" ],
latency => 2,
units => [ "VFP" ],
mode => "mode_E",
attr_type => "ia32_x87_attr_t",
},
-vfsin => {
- irn_flags => "R",
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
- latency => 150,
- units => [ "VFP" ],
- mode => "mode_E",
- attr_type => "ia32_x87_attr_t",
-},
-
-vfcos => {
- irn_flags => "R",
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
- latency => 150,
- units => [ "VFP" ],
- mode => "mode_E",
- attr_type => "ia32_x87_attr_t",
-},
-
-vfsqrt => {
- irn_flags => "R",
- reg_req => { in => [ "vfp"], out => [ "vfp" ] },
- latency => 30,
- units => [ "VFP" ],
- mode => "mode_E",
- attr_type => "ia32_x87_attr_t",
-},
-
# virtual Load and Store
vfld => {
op_flags => "L|F",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "mem" ],
outs => [ "res", "M" ],
+ attr => "ir_mode *store_mode",
+ init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
op_flags => "L|F",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
+ ins => [ "base", "index", "val", "mem" ],
+ attr => "ir_mode *store_mode",
+ init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
units => [ "VFP" ],
mode => "mode_M",
# Conversions
vfild => {
+ state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
outs => [ "res", "M" ],
+ ins => [ "base", "index", "mem" ],
latency => 4,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
vfist => {
+ state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
+ ins => [ "base", "index", "val", "fpcw", "mem" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_M",
l_vfist => {
cmp_attr => "return 1;",
+ state => "exc_pinned",
arity => 3,
mode => "mode_M",
},
vfCondJmp => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "none", "none", "eax" ] },
+ reg_req => { in => [ "vfp", "vfp" ], out => [ "none", "none", "eax" ] },
+ ins => [ "left", "right" ],
outs => [ "false", "true", "temp_reg_eax" ],
+ attr => "long pnc",
+ init_attr => "attr->attr.pn_code = pnc;",
latency => 10,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. faddp %x87_binop',
+ emit => '. faddp%XM %x87_binop',
attr_type => "ia32_x87_attr_t",
},
op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fmulp %x87_binop',,
+ emit => '. fmulp%XM %x87_binop',,
attr_type => "ia32_x87_attr_t",
},
rd_constructor => "NONE",
reg_req => { },
# see note about gas bugs
- emit => '. fsubrp %x87_binop',
+ emit => '. fsubrp%XM %x87_binop',
attr_type => "ia32_x87_attr_t",
},
irn_flags => "R",
reg_req => { },
# see note about gas bugs
- emit => '. fsubp %x87_binop',
+ emit => '. fsubp%XM %x87_binop',
attr_type => "ia32_x87_attr_t",
},
rd_constructor => "NONE",
reg_req => { },
# see note about gas bugs
- emit => '. fdivrp %x87_binop',
+ emit => '. fdivrp%XM %x87_binop',
attr_type => "ia32_x87_attr_t",
},
rd_constructor => "NONE",
reg_req => { },
# see note about gas bugs
- emit => '. fdivp %x87_binop',
+ emit => '. fdivp%XM %x87_binop',
attr_type => "ia32_x87_attr_t",
},
attr_type => "ia32_x87_attr_t",
},
-fsin => {
- op_flags => "R",
- rd_constructor => "NONE",
- reg_req => { },
- emit => '. fsin',
- attr_type => "ia32_x87_attr_t",
-},
-
-fcos => {
- op_flags => "R",
- rd_constructor => "NONE",
- reg_req => { },
- emit => '. fcos',
- attr_type => "ia32_x87_attr_t",
-},
-
-fsqrt => {
- op_flags => "R",
- rd_constructor => "NONE",
- reg_req => { },
- emit => '. fsqrt $',
- attr_type => "ia32_x87_attr_t",
-},
-
# x87 Load and Store
fld => {
op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fild%XM %AM',
+ emit => '. fild%M %AM',
attr_type => "ia32_x87_attr_t",
},
fist => {
op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fist%XM %AM',
+ emit => '. fist%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
fistp => {
op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fistp%XM %AM',
+ emit => '. fistp%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
projects / libfirm / blobdiff