modified_flags => $status_flags
},
-l_Shl => {
+l_ShlDep => {
cmp_attr => "return 1;",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShlD => {
- irn_flags => "R",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
- # this Shift and the only value dying is the ShiftCount. Then there would be
- # a register missing, as result must not be ecx and all other registers are
- # occupied. What we should write is "!in_r4 !in_r5", but this is not
- # supported (and probably never will). So we create artificial interferences
- # of the result with all inputs, so the spiller can always assure a free
- # register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+ # this Shift and the only value dying is the ShiftCount. Then there would be a
+ # register missing, as result must not be ecx and all other registers are
+ # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+ # (and probably never will). So we create artificial interferences of the result
+ # with all inputs, so the spiller can always assure a free register.
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
emit =>
'
if (get_ia32_immop_type(node) == ia32_ImmNone) {
modified_flags => $status_flags
},
-l_Shr => {
+l_ShrDep => {
cmp_attr => "return 1;",
- arity => 2
+ # value, cnt, dependency
+ arity => 3
},
ShrD => {
- irn_flags => "R",
+ # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
+ #
# Out requirements is: different from all in
# This is because, out must be different from LowPart and ShiftCount.
# We could say "!ecx !in_r4" but it can occur, that all values live through
# occupied. What we should write is "!in_r4 !in_r5", but this is not supported
# (and probably never will). So we create artificial interferences of the result
# with all inputs, so the spiller can always assure a free register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+ # reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
emit => '
if (get_ia32_immop_type(node) == ia32_ImmNone) {
if (get_ia32_op_type(node) == ia32_AddrModeD) {
l_Sar => {
cmp_attr => "return 1;",
+ # value, cnt
arity => 2
},
+l_SarDep => {
+ cmp_attr => "return 1;",
+ # value, cnt, dependency
+ arity => 3
+},
+
Ror => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
AddSP => {
irn_flags => "I",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
emit => '. addl %binop',
outs => [ "stack:S", "M" ],
SubSP => {
#irn_flags => "I",
+ state => "pinned",
reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
emit => ". subl %binop\n".
". movl %%esp, %D1",
# Conversions
Conv_I2I => {
+ state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
units => [ "GP" ],
ins => [ "base", "index", "val", "mem" ],
},
Conv_I2I8Bit => {
+ state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
ins => [ "base", "index", "val", "mem" ],
units => [ "GP" ],
TestCMov => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
- ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
latency => 2,
vfCmpCMov => {
irn_flags => "R",
- reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+ reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "gp", "gp" ],
+ out => [ "in_r7" ] },
+ ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+ "val_false" ],
latency => 10,
- units => [ "VFP" ],
+ units => [ "VFP", "GP" ],
mode => $mode_gp,
attr_type => "ia32_x87_attr_t",
},
CmpSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
TestSet => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+ reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
+ out => [ "eax ebx ecx edx" ] },
ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
attr => "pn_Cmp pn_code",
init_attr => "attr->pn_code = pn_code;",
op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fild%XM %AM',
+ emit => '. fild%M %AM',
attr_type => "ia32_x87_attr_t",
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fist%XM %AM',
+ emit => '. fist%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fistp%XM %AM',
+ emit => '. fistp%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},