fix sse/x87 fixup code added at wrong places

[libfirm] / ir / be / ia32 / ia32_spec.pl

diff --git a/ir/be/ia32/ia32_spec.pl b/ir/be/ia32/ia32_spec.pl
index 198b14e..bc6669e 100644 (file)
--- a/ir/be/ia32/ia32_spec.pl
+++ b/ir/be/ia32/ia32_spec.pl
@@ -594,23 +594,27 @@ Shl => {
        modified_flags => $status_flags
 },
 
-l_Shl => {
+l_ShlDep => {
        cmp_attr  => "return 1;",
-       arity     => 2
+       # value, cnt, dependency
+       arity     => 3
 },
 
 ShlD => {
-       irn_flags => "R",
+       # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shl
+       #
        # Out requirements is: different from all in
        # This is because, out must be different from LowPart and ShiftCount.
        # We could say "!ecx !in_r4" but it can occur, that all values live through
-       # this Shift and the only value dying is the ShiftCount. Then there would be
-       # a register missing, as result must not be ecx and all other registers are
-       # occupied. What we should write is "!in_r4 !in_r5", but this is not
-       # supported (and probably never will). So we create artificial interferences
-       # of the result with all inputs, so the spiller can always assure a free
-       # register.
-       reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+       # this Shift and the only value dying is the ShiftCount. Then there would be a
+       # register missing, as result must not be ecx and all other registers are
+       # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
+       # (and probably never will). So we create artificial interferences of the result
+       # with all inputs, so the spiller can always assure a free register.
+       # reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+       irn_flags => "R",
+       reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
        emit      =>
 '
 if (get_ia32_immop_type(node) == ia32_ImmNone) {
@@ -647,13 +651,15 @@ Shr => {
        modified_flags => $status_flags
 },
 
-l_Shr => {
+l_ShrDep => {
        cmp_attr  => "return 1;",
-       arity     => 2
+       # value, cnt, dependency
+       arity     => 3
 },
 
 ShrD => {
-       irn_flags => "R",
+       # FIXME: WHY? the right requirement is in_r3 !in_r5, especially this is the same as in Shr
+       #
        # Out requirements is: different from all in
        # This is because, out must be different from LowPart and ShiftCount.
        # We could say "!ecx !in_r4" but it can occur, that all values live through
@@ -662,7 +668,10 @@ ShrD => {
        # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
        # (and probably never will). So we create artificial interferences of the result
        # with all inputs, so the spiller can always assure a free register.
-       reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+       # reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
+
+       irn_flags => "R",
+       reg_req   => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r5" ] },
        emit      => '
 if (get_ia32_immop_type(node) == ia32_ImmNone) {
        if (get_ia32_op_type(node) == ia32_AddrModeD) {
@@ -700,9 +709,16 @@ Sar => {
 
 l_Sar => {
        cmp_attr  => "return 1;",
+       # value, cnt
        arity     => 2
 },
 
+l_SarDep => {
+       cmp_attr  => "return 1;",
+       # value, cnt, dependency
+       arity     => 3
+},
+
 Ror => {
        irn_flags => "R",
        reg_req   => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
@@ -1041,6 +1057,7 @@ Leave => {
 
 AddSP => {
        irn_flags => "I",
+       state     => "pinned",
        reg_req   => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
        emit      => '. addl %binop',
        outs      => [ "stack:S", "M" ],
@@ -1050,6 +1067,7 @@ AddSP => {
 
 SubSP => {
 #irn_flags => "I",
+       state     => "pinned",
        reg_req   => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
        emit      => ". subl %binop\n".
                     ". movl %%esp, %D1",
@@ -1352,8 +1370,10 @@ CmpCMov => {
 
 TestCMov => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
-       ins       => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
+       reg_req   => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ],
+                      out => [ "in_r7" ] },
+       ins       => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+                      "val_false" ],
        attr      => "pn_Cmp pn_code",
        init_attr => "attr->pn_code = pn_code;",
        latency   => 2,
@@ -1371,16 +1391,20 @@ xCmpCMov => {
 
 vfCmpCMov => {
        irn_flags => "R",
-       reg_req   => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+       reg_req   => { in => [ "gp", "gp", "vfp", "vfp", "none", "gp", "gp" ],
+                      out => [ "in_r7" ] },
+       ins       => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true",
+                      "val_false" ],
        latency   => 10,
-       units     => [ "VFP" ],
+       units     => [ "VFP", "GP" ],
        mode      => $mode_gp,
        attr_type => "ia32_x87_attr_t",
 },
 
 CmpSet => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+       reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ],
+                      out => [ "eax ebx ecx edx" ] },
        ins       => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
        attr      => "pn_Cmp pn_code",
        init_attr => "attr->pn_code = pn_code;",
@@ -1391,7 +1415,8 @@ CmpSet => {
 
 TestSet => {
        irn_flags => "R",
-       reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
+       reg_req   => { in => [ "gp", "gp", "gp", "gp", "none" ],
+                      out => [ "eax ebx ecx edx" ] },
        ins       => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
        attr      => "pn_Cmp pn_code",
        init_attr => "attr->pn_code = pn_code;",
@@ -1868,7 +1893,7 @@ fild => {
        op_flags  => "R",
        rd_constructor => "NONE",
        reg_req   => { },
-       emit      => '. fild%XM %AM',
+       emit      => '. fild%M %AM',
        attr_type => "ia32_x87_attr_t",
 },
 
@@ -1877,7 +1902,7 @@ fist => {
        state     => "exc_pinned",
        rd_constructor => "NONE",
        reg_req   => { },
-       emit      => '. fist%XM %AM',
+       emit      => '. fist%M %AM',
        mode      => "mode_M",
        attr_type => "ia32_x87_attr_t",
 },
@@ -1887,7 +1912,7 @@ fistp => {
        state     => "exc_pinned",
        rd_constructor => "NONE",
        reg_req   => { },
-       emit      => '. fistp%XM %AM',
+       emit      => '. fistp%M %AM',
        mode      => "mode_M",
        attr_type => "ia32_x87_attr_t",
 },