"l_Add" => {
"op_flags" => "C",
"irn_flags" => "R",
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Add: Add(a, b) = Add(b, a) = a + b",
"arity" => 2,
},
"l_AddC" => {
"op_flags" => "C",
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Add with Carry: AddC(a, b) = Add(b, a) = a + b + carry",
"arity" => 2,
},
"MulS" => {
"comment" => "construct MulS: MulS(a, b) = MulS(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
- "emit" => '. mul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */',
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx" ] },
+ "emit" => '. mul %ia32_emit_unop /* Mul(%A1, %A2) -> %D1 */',
"outs" => [ "EAX", "EDX", "M" ],
},
"l_MulS" => {
"op_flags" => "C",
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered MulS: MulS(a, b) = MulS(b, a) = a * b",
"outs" => [ "EAX", "EDX", "M" ],
"arity" => 2
"l_Mul" => {
"op_flags" => "C",
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Mul: Mul(a, b) = Mul(b, a) = a * b",
"arity" => 2
},
"Mulh" => {
"comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
- "emit" => '. imul %ia32_emit_binop /* Mulh(%A1, %A2) -> %D1 */',
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx" ] },
+ "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */',
"outs" => [ "EAX", "EDX", "M" ],
},
"outs" => [ "res", "M" ],
},
+"l_Eor" => {
+ "op_flags" => "C",
+ "cmp_attr" => " return 1;\n",
+ "comment" => "construct lowered Eor: Eor(a, b) = Eor(b, a) = a EOR b",
+ "arity" => 2
+},
+
"Max" => {
"irn_flags" => "R",
"comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
"l_Sub" => {
"irn_flags" => "R",
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Sub: Sub(a, b) = a - b",
"arity" => 2,
},
"l_SubC" => {
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Sub with Carry: SubC(a, b) = a - b - carry",
"arity" => 2,
},
"init_attr" => " attr->data.op_flav = dm_flav;",
"cmp_attr" => " return attr_a->data.op_flav != attr_b->data.op_flav;\n",
"emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
+' if (mode_is_signed(get_ia32_res_mode(n))) {
4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
else {
},
"l_Shl" => {
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Shl: Shl(a, b) = a << b",
"arity" => 2
},
},
"l_ShlD" => {
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered ShlD: ShlD(a, b, c) = a, b << count (shift left count bits from b into a)",
"arity" => 3
},
},
"l_Shr" => {
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Shr: Shr(a, b) = a << b",
"arity" => 2
},
},
"l_ShrD" => {
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered ShrD: ShrD(a, b, c) = a, b >> count (shift rigth count bits from a into b)",
"arity" => 3
},
},
"l_Shrs" => {
+ "cmp_attr" => " return 1;\n",
"comment" => "construct lowered Shrs: Shrs(a, b) = a << b",
"arity" => 2
},
"outs" => [ "res", "M" ],
},
+"l_Minus" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "construct lowered Minus: Minus(a) = -a",
+ "arity" => 1,
+},
+
"Inc" => {
"irn_flags" => "R",
"comment" => "construct Increment: Inc(a) = a++",
"outs" => [ "res", "M" ],
},
+"l_Load" => {
+ "op_flags" => "L|F",
+ "cmp_attr" => " return 1;\n",
+ "comment" => "construct lowered Load: Load(ptr, mem) = LD ptr -> reg",
+ "outs" => [ "res", "M" ],
+ "arity" => 2,
+},
+
+"l_Store" => {
+ "op_flags" => "L|F",
+ "cmp_attr" => " return 1;\n",
+ "state" => "exc_pinned",
+ "comment" => "construct lowered Store: Store(ptr, val, mem) = ST ptr,val",
+ "arity" => 3,
+ "outs" => [ "M" ],
+},
+
"Store" => {
"op_flags" => "L|F",
"state" => "exc_pinned",
"outs" => [ "M" ],
},
+"l_X87toSSE" => {
+ "op_flags" => "L|F",
+ "comment" => "construct: transfer a value from x87 FPU into a SSE register",
+ "cmp_attr" => " return 1;\n",
+ "arity" => 3,
+},
+
+"l_SSEtoX87" => {
+ "op_flags" => "L|F",
+ "comment" => "construct: transfer a value from SSE register to x87 FPU",
+ "cmp_attr" => " return 1;\n",
+ "arity" => 3,
+},
+
# CopyB
"CopyB" => {
"op_flags" => "F|H",
"state" => "pinned",
"comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
- "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "edi in_r1", "esi in_r2", "ecx in_r3", "none" ] },
+ "outs" => [ "DST", "SRC", "CNT", "M" ],
},
"CopyB_i" => {
"state" => "pinned",
"comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
- "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "edi in_r1", "esi in_r2", "none" ] },
+ "outs" => [ "DST", "SRC", "M" ],
},
# Conversions
"vfmul" => {
"irn_flags" => "R",
- "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a + b",
+ "comment" => "virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"reg_req" => { "in" => [ "gp", "gp", "vfp", "vfp", "none" ], "out" => [ "vfp" ] },
"outs" => [ "res", "M" ],
},
+"l_vfmul" => {
+ "op_flags" => "C",
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "arity" => 2,
+},
+
"vfsub" => {
"irn_flags" => "R",
"comment" => "virtual fp Sub: Sub(a, b) = a - b",
"outs" => [ "res", "M" ],
},
+"l_vfsub" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Sub: Sub(a, b) = a - b",
+ "arity" => 2,
+},
+
"vfdiv" => {
"comment" => "virtual fp Div: Div(a, b) = a / b",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"outs" => [ "res", "M" ],
},
+"l_vfdiv" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp Div: Div(a, b) = a / b",
+ "arity" => 2,
+},
+
"vfabs" => {
"irn_flags" => "R",
"comment" => "virtual fp Abs: Abs(a) = |a|",
"outs" => [ "res", "M" ],
},
+"l_vfild" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp integer Load: Load(ptr, mem) = iLD ptr -> reg",
+ "outs" => [ "res", "M" ],
+ "arity" => 2,
+},
+
"vfist" => {
"comment" => "virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
"cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
"outs" => [ "M" ],
},
+"l_vfist" => {
+ "cmp_attr" => " return 1;\n",
+ "comment" => "lowered virtual fp integer Store: Store(ptr, val, mem) = iST ptr,val",
+ "outs" => [ "M" ],
+ "arity" => 3,
+},
+
+
# constants
"vfldz" => {