#
# <op-name> => {
# op_flags => "N|L|C|X|I|F|Y|H|c|K",
-# irn_flags => "R|N|I|S"
+# irn_flags => "R|N"
# arity => "0|1|2|3 ... |variable|dynamic|any",
# state => "floats|pinned|mem_pinned|exc_pinned",
# args => [
# comment => "any comment for constructor",
# reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
# cmp_attr => "c source code for comparing node attributes",
+# outs => { "out1", "out2" } # optional, creates pn_op_out1, ... consts
+# ins => { "in1", "in2" } # optional, creates n_op_in1, ... consts
+# mode => "mode_Iu" # optional, predefines the mode
# emit => "emit code with templates",
-# attr => "attitional attribute arguments for constructor"
-# init_attr => "emit attribute initialization template"
-# rd_constructor => "c source code which constructs an ir_node"
+# attr => "additional attribute arguments for constructor",
+# init_attr => "emit attribute initialization template",
+# rd_constructor => "c source code which constructs an ir_node",
+# hash_func => "name of the hash function for this operation",
+# latency => "latency of this operation (can be float)"
# attr_type => "name of the attribute struct",
+# modified_flags => [ "CF", ... ] # optional, list of modified flags
# },
#
# ... # (all nodes you need to describe)
# H irop_flag_highlevel
# c irop_flag_constlike
# K irop_flag_keep
+# NB irop_flag_dump_noblock
+# NI irop_flag_dump_noinput
#
# irn_flags: special node flags, OPTIONAL (default is 0)
# following irn_flags are supported:
# R rematerializeable
# N not spillable
-# I ignore for register allocation
-# S modifies stack pointer
#
# state: state of the operation, OPTIONAL (default is "floats")
#
#
# outs: if a node defines more than one output, the names of the projections
# nodes having outs having automatically the mode mode_T
-# One can also annotate some flags for each out, additional to irn_flags.
-# They are separated from name with a colon ':', and concatenated by pipe '|'
-# Only I and S are available at the moment (same meaning as in irn_flags).
-# example: [ "frame:I", "stack:I|S", "M" ]
+# example: [ "frame", "stack", "M" ]
#
# comment: OPTIONAL comment for the node constructor
#
{ mode => "mode_E" }
],
vfp => [
- { name => "vf0", type => 1 | 16 },
- { name => "vf1", type => 1 | 16 },
- { name => "vf2", type => 1 | 16 },
- { name => "vf3", type => 1 | 16 },
- { name => "vf4", type => 1 | 16 },
- { name => "vf5", type => 1 | 16 },
- { name => "vf6", type => 1 | 16 },
- { name => "vf7", type => 1 | 16 },
+ { name => "vf0", type => 1 },
+ { name => "vf1", type => 1 },
+ { name => "vf2", type => 1 },
+ { name => "vf3", type => 1 },
+ { name => "vf4", type => 1 },
+ { name => "vf5", type => 1 },
+ { name => "vf6", type => 1 },
+ { name => "vf7", type => 1 },
{ name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
{ mode => "mode_E" }
SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+ SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
D0 => "${arch}_emit_dest_register(node, 0);",
D1 => "${arch}_emit_dest_register(node, 1);",
XXM => "${arch}_emit_xmm_mode_suffix(node);",
XSD => "${arch}_emit_xmm_mode_suffix_s(node);",
AM => "${arch}_emit_am(node);",
- unop3 => "${arch}_emit_unop(node, 3);",
- unop4 => "${arch}_emit_unop(node, 4);",
- unop5 => "${arch}_emit_unop(node, 5);",
- DAM0 => "${arch}_emit_am_or_dest_register(node, 0);",
+ unop3 => "${arch}_emit_unop(node, n_ia32_unary_op);",
+ unop4 => "${arch}_emit_unop(node, n_ia32_binary_right);",
binop => "${arch}_emit_binop(node);",
x87_binop => "${arch}_emit_x87_binop(node);",
CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);",
+ CMP3 => "${arch}_emit_cmp_suffix_node(node, 3);",
);
#--------------------------------------------------#
my $res = "";
if(defined($node->{modified_flags})) {
- $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n";
+ $res .= "\tarch_irn_add_flags(res, arch_irn_flags_modify_flags);\n";
}
if(defined($node->{am})) {
my $am = $node->{am};
- if($am eq "full,binary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_binary);";
- } elsif($am eq "full,unary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Full, ia32_am_unary);";
- } elsif($am eq "source,unary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_unary);";
+ if($am eq "source,unary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_unary);";
} elsif($am eq "source,binary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);";
- } elsif($am eq "dest,unary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_unary);";
- } elsif($am eq "dest,binary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_binary);";
- } elsif($am eq "dest,ternary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Dest, ia32_am_ternary);";
- } elsif($am eq "source,ternary") {
- $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);";
+ $res .= "\tset_ia32_am_support(res, ia32_am_binary);";
} elsif($am eq "none") {
# nothing to do
} else {
$custom_init_attr_func = \&ia32_custom_init_attr;
%init_attr = (
- ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
- ia32_x87_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_x87_attributes(res);",
ia32_asm_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
"\tinit_ia32_x87_attributes(res);".
"\tinit_ia32_asm_attributes(res);",
- ia32_immediate_attr_t =>
+ ia32_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
+ ia32_call_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);",
+ "\tinit_ia32_call_attributes(res, pop, call_tp);",
+ ia32_condcode_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_condcode_attributes(res, pnc);",
ia32_copyb_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
"\tinit_ia32_copyb_attributes(res, size);",
- ia32_condcode_attr_t =>
+ ia32_immediate_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
- "\tinit_ia32_condcode_attributes(res, pnc);",
+ "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);",
+ ia32_x87_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_x87_attributes(res);",
+ ia32_climbframe_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_climbframe_attributes(res, count);",
);
%compare_attr = (
- ia32_attr_t => "ia32_compare_nodes_attr",
- ia32_x87_attr_t => "ia32_compare_x87_attr",
ia32_asm_attr_t => "ia32_compare_asm_attr",
- ia32_immediate_attr_t => "ia32_compare_immediate_attr",
- ia32_copyb_attr_t => "ia32_compare_copyb_attr",
- ia32_condcode_attr_t => "ia32_compare_condcode_attr",
+ ia32_attr_t => "ia32_compare_nodes_attr",
+ ia32_call_attr_t => "ia32_compare_call_attr",
+ ia32_condcode_attr_t => "ia32_compare_condcode_attr",
+ ia32_copyb_attr_t => "ia32_compare_copyb_attr",
+ ia32_immediate_attr_t => "ia32_compare_immediate_attr",
+ ia32_x87_attr_t => "ia32_compare_x87_attr",
+ ia32_climbframe_attr_t => "ia32_compare_climbframe_attr",
);
%operands = (
);
-$mode_xmm = "mode_E";
-$mode_gp = "mode_Iu";
-$mode_flags = "mode_Iu";
-$mode_fpcw = "mode_fpcw";
-$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
-$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
- "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
+$mode_xmm = "mode_E";
+$mode_gp = "mode_Iu";
+$mode_flags = "mode_Iu";
+$mode_fpcw = "mode_fpcw";
+$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
+$status_flags_wo_cf = [ "PF", "AF", "ZF", "SF", "OF" ];
+$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
+ "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
%nodes = (
Immediate => {
state => "pinned",
op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "gp_NOREG" ] },
+ reg_req => { out => [ "gp_NOREG:I" ] },
attr => "ir_entity *symconst, int symconst_sign, long offset",
attr_type => "ia32_immediate_attr_t",
+ hash_func => "ia32_hash_Immediate",
latency => 0,
mode => $mode_gp,
},
init_attr => "attr->asm_text = asm_text;\n".
"\tattr->register_map = register_map;\n",
latency => 10,
- modified_flags => 1,
+ modified_flags => $status_flags,
},
+# "allocates" a free register
ProduceVal => {
op_flags => "c",
irn_flags => "R",
Add => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5", "none", "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
emit => '. add%M %binop',
- am => "full,binary",
+ am => "source,binary",
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
Adc => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right", "eflags" ],
+ outs => [ "res", "flags", "M" ],
emit => '. adc%M %binop',
- am => "full,binary",
+ am => "source,binary",
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
Mul => {
# we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
+ # very strict constraints
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
- ins => [ "base", "index", "mem", "val_high", "val_low" ],
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
+ out => [ "eax", "flags", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. mul%M %unop4',
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "res_low", "flags", "res_high", "M" ],
am => "source,binary",
latency => 10,
units => [ "GP" ],
l_Mul => {
# we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
+ # very strict constraints
op_flags => "C",
cmp_attr => "return 1;",
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "EAX", "flags", "EDX", "M" ],
arity => 2
},
IMul => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ # TODO: adjust out requirements for the 3 operand form
+ # (no need for should_be_same then)
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- emit => '. imul%M %binop',
+ outs => [ "res", "flags", "M" ],
am => "source,binary",
latency => 5,
units => [ "GP" ],
IMul1OP => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ], out => [ "eax", "edx", "none" ] },
- ins => [ "base", "index", "mem", "val_high", "val_low" ],
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
+ out => [ "eax", "flags", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
emit => '. imul%M %unop4',
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "res_low", "flags", "res_high", "M" ],
am => "source,binary",
latency => 5,
units => [ "GP" ],
},
l_IMul => {
- # we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
op_flags => "C",
cmp_attr => "return 1;",
- outs => [ "EAX", "EDX", "M" ],
+ outs => [ "res_low", "res_high", "M" ],
arity => 2
},
And => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
op_modes => "commutative | am | immediate | mode_neutral",
- am => "full,binary",
+ am => "source,binary",
emit => '. and%M %binop',
units => [ "GP" ],
latency => 1,
Or => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- am => "full,binary",
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. or%M %binop',
units => [ "GP" ],
latency => 1,
Xor => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4 in_r5" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- am => "full,binary",
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. xor%M %binop',
units => [ "GP" ],
latency => 1,
modified_flags => $status_flags
},
+Xor0 => {
+ op_flags => "c",
+ irn_flags => "R",
+ reg_req => { out => [ "gp", "flags" ] },
+ outs => [ "res", "flags" ],
+ emit => ". xor%M %D0, %D0",
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
XorMem => {
irn_flags => "R",
state => "exc_pinned",
Sub => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ], out => [ "in_r4", "none", "flags" ] },
- ins => [ "base", "index", "mem", "left", "right" ],
- am => "full,binary",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. sub%M %binop',
units => [ "GP" ],
latency => 1,
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
- ins => [ "base", "index", "mem", "val" ],
+ ins => [ "base", "index", "mem", "subtrahend" ],
emit => '. sub%M %SI3, %AM',
units => [ "GP" ],
latency => 1,
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
- ins => [ "base", "index", "mem", "val" ],
+ ins => [ "base", "index", "mem", "subtrahend" ],
emit => '. sub%M %SB3, %AM',
units => [ "GP" ],
latency => 1,
Sbb => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ], out => [ "in_r4 !in_r5" ] },
- ins => [ "base", "index", "mem", "left", "right", "eflags" ],
- am => "full,binary",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
+ out => [ "in_r4 !in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "minuend", "subtrahend", "eflags" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. sbb%M %binop',
units => [ "GP" ],
latency => 1,
modified_flags => $status_flags
},
+Sbb0 => {
+ irn_flags => "R",
+ reg_req => { in => [ "flags" ], out => [ "gp", "flags" ] },
+ outs => [ "res", "flags" ],
+ emit => ". sbb%M %D0, %D0",
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
l_Sub => {
reg_req => { in => [ "none", "none" ], out => [ "none" ] },
- ins => [ "left", "right" ],
+ ins => [ "minuend", "subtrahend" ],
},
l_Sbb => {
reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
- ins => [ "left", "right", "eflags" ],
+ ins => [ "minuend", "subtrahend", "eflags" ],
},
IDiv => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "none", "none", "edx" ] },
- ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
- outs => [ "div_res", "M", "unused", "mod_res" ],
- am => "source,ternary",
- emit => ". idiv%M %unop5",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
+ out => [ "eax", "flags", "none", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
+ outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
+ am => "source,unary",
+ emit => ". idiv%M %unop3",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Div => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax", "edx", "gp" ], out => [ "eax", "none", "none", "edx" ] },
- ins => [ "base", "index", "mem", "left_low", "left_high", "right" ],
- outs => [ "div_res", "M", "unused", "mod_res" ],
- am => "source,ternary",
- emit => ". div%M %unop5",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
+ out => [ "eax", "flags", "none", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
+ outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
+ am => "source,unary",
+ emit => ". div%M %unop3",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Shl => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
- ins => [ "left", "right" ],
- emit => '. shl %SB1, %S0',
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
+ emit => '. shl%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
},
l_ShlDep => {
- cmp_attr => "return 1;",
- ins => [ "left", "right", "dep" ],
- # value, cnt, dependency
- arity => 3
+ cmp_attr => "return 1;",
+ ins => [ "val", "count", "dep" ],
+ arity => 3
},
ShlD => {
irn_flags => "R",
- # see ShrD about the strange out constraint
- reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] },
- ins => [ "left_high", "left_low", "right" ],
- emit => ". shld%M %SB2, %S1, %S0\n".
- ". movl %S0, %D0",
+ reg_req => { in => [ "gp", "gp", "ecx" ],
+ out => [ "in_r1 !in_r2 !in_r3", "flags" ] },
+ ins => [ "val_high", "val_low", "count" ],
+ outs => [ "res", "flags" ],
+ emit => ". shld%M %SB2, %S1, %D0",
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShlD => {
cmp_attr => "return 1;",
- ins => [ "high", "low", "count" ],
+ ins => [ "val_high", "val_low", "count" ],
arity => 3,
},
Shr => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
- emit => '. shr %SB1, %S0',
+ outs => [ "res", "flags" ],
+ emit => '. shr%M %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
latency => 1,
l_ShrDep => {
cmp_attr => "return 1;",
- ins => [ "left", "right", "dep" ],
- # value, cnt, dependency
+ ins => [ "val", "count", "dep" ],
arity => 3
},
ShrD => {
- # What's going on with the out constraint here? We would like to write
- # "in_r2" and be done. However in firm we only support should_be_same
- # constraints at the moment. Which means they could be non-fullfilled in
- # some cases. Now when all values happen to live through the node, out
- # is ecx and in_r2 not ecx, then we're screwed. Because in this case we
- # need a 4th Register.
- #
- # The best solution for this is extending the register allocator to support
- # must_be_same constraints which create a copy when the in_r2 value
- # lives through (this ensures that we have the 4th register in the cases
- # when we need it and can always fix the situation).
- #
- # For now I'm doing this ultra ugly !in hack which allocates 4 registers
- # and creates an extra mov
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "ecx" ], out => [ "!in" ] },
- ins => [ "left_high", "left_low", "right" ],
- emit => ". shrd%M %SB2, %S1, %S0\n".
- ". movl %S0, %D0",
+ irn_flags => "R",
+ reg_req => { in => [ "gp", "gp", "ecx" ],
+ out => [ "in_r1 !in_r2 !in_r3", "flags" ] },
+ ins => [ "val_high", "val_low", "count" ],
+ outs => [ "res", "flags" ],
+ emit => ". shrd%M %SB2, %S1, %D0",
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShrD => {
cmp_attr => "return 1;",
arity => 3,
- ins => [ "high", "low", "count" ],
+ ins => [ "val_high", "val_low", "count" ],
},
Sar => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
- emit => '. sar %SB1, %S0',
+ outs => [ "res", "flags" ],
+ emit => '. sar%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
l_SarDep => {
cmp_attr => "return 1;",
- ins => [ "left", "right", "dep" ],
- # value, cnt, dependency
+ ins => [ "val", "count", "dep" ],
arity => 3
},
Ror => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
- emit => '. ror %SB1, %S0',
+ outs => [ "res", "flags" ],
+ emit => '. ror%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
Rol => {
irn_flags => "R",
- reg_req => { in => [ "gp", "ecx" ], out => [ "in_r1 !in_r2" ] },
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
- emit => '. rol %SB1, %S0',
+ outs => [ "res", "flags" ],
+ emit => '. rol%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
Neg => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
- emit => '. neg %S0',
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ emit => '. neg%M %S0',
ins => [ "val" ],
+ outs => [ "res", "flags" ],
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
Minus64Bit => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "gp" ] },
+ reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "in_r2" ] },
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
latency => 3,
Inc => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
- emit => '. inc %S0',
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
+ outs => [ "res", "flags" ],
+ emit => '. inc%M %S0',
units => [ "GP" ],
mode => $mode_gp,
latency => 1,
- modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+ modified_flags => $status_flags_wo_cf
},
IncMem => {
units => [ "GP" ],
mode => "mode_M",
latency => 1,
- modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+ modified_flags => $status_flags_wo_cf
},
Dec => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
- emit => '. dec %S0',
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
+ outs => [ "res", "flags" ],
+ emit => '. dec%M %S0',
units => [ "GP" ],
mode => $mode_gp,
latency => 1,
- modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+ modified_flags => $status_flags_wo_cf
},
DecMem => {
units => [ "GP" ],
mode => "mode_M",
latency => 1,
- modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+ modified_flags => $status_flags_wo_cf
},
Not => {
irn_flags => "R",
- reg_req => { in => [ "gp" ], out => [ "in_r1" ] },
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
ins => [ "val" ],
- emit => '. not %S0',
+ outs => [ "res", "flags" ],
+ emit => '. not%M %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
+ # no flags modified
},
NotMem => {
units => [ "GP" ],
latency => 1,
mode => "mode_M",
+ # no flags modified
+},
+
+Cmc => {
+ reg_req => { in => [ "flags" ], out => [ "flags" ] },
+ emit => '.cmc',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Stc => {
+ reg_req => { out => [ "flags" ] },
+ emit => '.stc',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags
},
# other operations
Cmp => {
irn_flags => "R",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "flags", "none", "none" ] },
ins => [ "base", "index", "mem", "left", "right" ],
- outs => [ "eflags" ],
+ outs => [ "eflags", "unused", "M" ],
am => "source,binary",
emit => '. cmp%M %binop',
attr => "int ins_permuted, int cmp_unsigned",
mode => $mode_gp,
},
+SetMem => {
+ #irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eflags" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem","eflags" ],
+ attr_type => "ia32_condcode_attr_t",
+ attr => "pn_Cmp pnc, int ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n".
+ "\tset_ia32_ls_mode(res, mode_Bu);\n",
+ emit => '. set%CMP3 %AM',
+ latency => 1,
+ units => [ "GP" ],
+ mode => 'mode_M',
+},
+
CMov => {
#irn_flags => "R",
# (note: leave the false,true order intact to make it compatible with other
reg_req => { in => [ "gp" ], out => [ "none" ] },
mode => "mode_T",
attr_type => "ia32_condcode_attr_t",
- attr => "pn_Cmp pnc",
+ attr => "long pnc",
latency => 3,
units => [ "BRANCH" ],
modified_flags => $status_flags,
mode => $mode_gp,
},
+GetEIP => {
+ op_flags => "c",
+ reg_req => { out => [ "gp" ] },
+ units => [ "GP" ],
+ latency => 5,
+ mode => $mode_gp,
+ modified_flags => $status_flags,
+},
+
Unknown_GP => {
state => "pinned",
- op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "gp_UKNWN" ] },
+ op_flags => "c|NB",
+ reg_req => { out => [ "gp_UKNWN:I" ] },
units => [],
emit => "",
latency => 0,
Unknown_VFP => {
state => "pinned",
- op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "vfp_UKNWN" ] },
+ op_flags => "c|NB",
+ reg_req => { out => [ "vfp_UKNWN:I" ] },
units => [],
emit => "",
mode => "mode_E",
Unknown_XMM => {
state => "pinned",
- op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "xmm_UKNWN" ] },
+ op_flags => "c|NB",
+ reg_req => { out => [ "xmm_UKNWN:I" ] },
units => [],
emit => "",
latency => 0,
- mode => "mode_E"
+ mode => $mode_xmm
},
NoReg_GP => {
state => "pinned",
- op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "gp_NOREG" ] },
+ op_flags => "c|NB|NI",
+ reg_req => { out => [ "gp_NOREG:I" ] },
units => [],
emit => "",
latency => 0,
NoReg_VFP => {
state => "pinned",
- op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "vfp_NOREG" ] },
+ op_flags => "c|NB|NI",
+ reg_req => { out => [ "vfp_NOREG:I" ] },
units => [],
emit => "",
mode => "mode_E",
NoReg_XMM => {
state => "pinned",
- op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "xmm_NOREG" ] },
+ op_flags => "c|NB|NI",
+ reg_req => { out => [ "xmm_NOREG:I" ] },
units => [],
emit => "",
latency => 0,
ChangeCW => {
state => "pinned",
op_flags => "c",
- irn_flags => "I",
- reg_req => { out => [ "fp_cw" ] },
+ reg_req => { out => [ "fpcw:I" ] },
mode => $mode_fpcw,
latency => 3,
units => [ "GP" ],
FldCW => {
op_flags => "L|F",
state => "pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "fpcw:I" ] },
ins => [ "base", "index", "mem" ],
latency => 5,
emit => ". fldcw %AM",
units => [ "GP" ],
},
+FnstCWNOP => {
+ op_flags => "L|F",
+ state => "pinned",
+ reg_req => { in => [ "fp_cw" ], out => [ "none" ] },
+ ins => [ "fpcw" ],
+ latency => 0,
+ emit => "",
+ mode => "mode_M",
+},
+
Cltd => {
# we should not rematrialize this node. It has very strict constraints.
reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] },
- ins => [ "val", "globbered" ],
+ ins => [ "val", "clobbered" ],
emit => '. cltd',
latency => 1,
mode => $mode_gp,
Load => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M" ],
+ outs => [ "res", "M", "X_exc" ],
latency => 0,
emit => ". mov%SE%ME%.l %AM, %D0",
units => [ "GP" ],
},
-l_Load => {
- op_flags => "L|F",
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
-l_Store => {
- op_flags => "L|F",
- cmp_attr => "return 1;",
- state => "exc_pinned",
- arity => 3,
- mode => "mode_M",
-},
-
Store => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
emit => '. mov%M %SI3, %AM',
latency => 2,
units => [ "GP" ],
Store8Bit => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
emit => '. mov%M %SB3, %AM',
latency => 2,
units => [ "GP" ],
Push => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp:I|S", "none" ] },
ins => [ "base", "index", "mem", "val", "stack" ],
- emit => '. push%M %unop4',
- outs => [ "stack:I|S", "M" ],
- am => "source,binary",
+ emit => '. push%M %unop3',
+ outs => [ "stack", "M" ],
+ am => "source,unary",
latency => 2,
units => [ "GP" ],
},
Pop => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "gp", "none", "none", "esp" ] },
- emit => '. pop%M %DAM0',
- outs => [ "res", "M", "unused", "stack:I|S" ],
+ reg_req => { in => [ "none", "esp" ], out => [ "gp", "none", "none", "esp:I|S" ] },
+ ins => [ "mem", "stack" ],
+ outs => [ "res", "M", "unused", "stack" ],
+ emit => '. pop%M %D0',
+ latency => 3, # Pop is more expensive than Push on Athlon
+ units => [ "GP" ],
+},
+
+PopEbp => {
+ state => "exc_pinned",
+ reg_req => { in => [ "none", "esp" ], out => [ "ebp:I", "none", "none", "esp:I|S" ] },
+ ins => [ "mem", "stack" ],
+ outs => [ "res", "M", "unused", "stack" ],
+ emit => '. pop%M %D0',
+ latency => 3, # Pop is more expensive than Push on Athlon
+ units => [ "GP" ],
+},
+
+PopMem => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "none", "none", "none", "esp:I|S" ] },
ins => [ "base", "index", "mem", "stack" ],
- am => "dest,unary",
+ outs => [ "unused0", "M", "unused1", "stack" ],
+ emit => '. pop%M %AM',
latency => 3, # Pop is more expensive than Push on Athlon
units => [ "GP" ],
},
Enter => {
- reg_req => { in => [ "esp" ], out => [ "ebp", "esp", "none" ] },
+ reg_req => { in => [ "esp" ], out => [ "ebp", "esp:I|S", "none" ] },
emit => '. enter',
- outs => [ "frame:I", "stack:I|S", "M" ],
+ outs => [ "frame", "stack", "M" ],
latency => 15,
units => [ "GP" ],
},
Leave => {
- reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
+ reg_req => { in => [ "ebp" ], out => [ "ebp:I", "esp:I|S" ] },
emit => '. leave',
- outs => [ "frame:I", "stack:I|S" ],
+ outs => [ "frame", "stack" ],
latency => 3,
units => [ "GP" ],
},
AddSP => {
- irn_flags => "I",
state => "pinned",
- reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp:I|S", "none" ] },
ins => [ "base", "index", "mem", "stack", "size" ],
am => "source,binary",
emit => '. addl %binop',
latency => 1,
- outs => [ "stack:S", "M" ],
+ outs => [ "stack", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
SubSP => {
-#irn_flags => "I",
state => "pinned",
- reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "gp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "esp:I|S", "gp", "none" ] },
ins => [ "base", "index", "mem", "stack", "size" ],
am => "source,binary",
emit => ". subl %binop\n".
". movl %%esp, %D1",
latency => 2,
- outs => [ "stack:I|S", "addr", "M" ],
+ outs => [ "stack", "addr", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
+RepPrefix => {
+ op_flags => "K",
+ state => "pinned",
+ mode => "mode_M",
+ emit => ". rep",
+ latency => 0,
+},
+
LdTls => {
irn_flags => "R",
reg_req => { out => [ "gp" ] },
latency => 1,
},
+Bt => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp" ], out => [ "flags" ] },
+ ins => [ "left", "right" ],
+ emit => '. bt%M %S1, %S0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags # only CF is set, but the other flags are undefined
+},
+
+Call => {
+ state => "exc_pinned",
+ reg_req => {
+ in => [ "gp", "gp", "none", "gp", "esp", "fpcw", "eax", "ecx", "edx" ],
+ out => [ "esp:I|S", "fpcw:I", "none", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ]
+ },
+ ins => [ "base", "index", "mem", "addr", "stack", "fpcw", "eax", "ecx", "edx" ],
+ outs => [ "stack", "fpcw", "M", "eax", "ecx", "edx", "vf0", "vf1", "vf2", "vf3", "vf4", "vf5", "vf6", "vf7", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7" ],
+ attr_type => "ia32_call_attr_t",
+ attr => "unsigned pop, ir_type *call_tp",
+ am => "source,unary",
+ units => [ "BRANCH" ],
+ latency => 4, # random number
+ modified_flags => $status_flags
+},
+
+#
+# a Helper node for frame-climbing, needed for __builtin_(frame|return)_address
+#
+# PS: try gcc __builtin_frame_address(100000) :-)
+#
+ClimbFrame => {
+ reg_req => { in => [ "gp", "gp", "gp"], out => [ "in_r3" ] },
+ ins => [ "frame", "cnt", "tmp" ],
+ outs => [ "res" ],
+ latency => 4, # random number
+ attr_type => "ia32_climbframe_attr_t",
+ attr => "unsigned count",
+ units => [ "GP" ],
+ mode => $mode_gp
+},
+
+#
+# Intel style prefetching
+#
+Prefetch0 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetch0 %AM",
+ units => [ "GP" ],
+},
+
+Prefetch1 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetch1 %AM",
+ units => [ "GP" ],
+},
+
+Prefetch2 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetch2 %AM",
+ units => [ "GP" ],
+},
+
+PrefetchNTA => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetchnta %AM",
+ units => [ "GP" ],
+},
+
+#
+# 3DNow! prefetch instructions
+#
+Prefetch => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetch %AM",
+ units => [ "GP" ],
+},
+
+PrefetchW => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetchw %AM",
+ units => [ "GP" ],
+},
#-----------------------------------------------------------------------------#
# _____ _____ ______ __ _ _ _ #
# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#-----------------------------------------------------------------------------#
+# produces a 0/+0.0
xZero => {
irn_flags => "R",
reg_req => { out => [ "xmm" ] },
emit => '. xorp%XSD %D0, %D0',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
+},
+
+xPzero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pxor %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# produces all 1 bits
+xAllOnes => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pcmpeqb %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, dword
+xPslld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. pslld %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, qword
+xPsllq => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psllq %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift right, dword
+xPsrld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psrld %SI1, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# mov from integer to SSE register
+xMovd => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp" ], out => [ "xmm" ] },
+ emit => '. movd %S0, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
},
# commutative operations
emit => '. add%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMul => {
emit => '. mul%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMax => {
emit => '. max%XXM %binop',
latency => 2,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMin => {
emit => '. min%XXM %binop',
latency => 2,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xAnd => {
emit => '. andp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xOr => {
emit => '. orp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xXor => {
emit => '. xorp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
# not commutative operations
emit => '. andnp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xSub => {
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
- ins => [ "base", "index", "mem", "left", "right" ],
+ ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
am => "source,binary",
emit => '. sub%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xDiv => {
irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
- ins => [ "base", "index", "mem", "left", "right" ],
+ ins => [ "base", "index", "mem", "dividend", "divisor" ],
am => "source,binary",
outs => [ "res", "M" ],
emit => '. div%XXM %binop',
xLoad => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] },
ins => [ "base", "index", "mem" ],
+ outs => [ "res", "M", "X_exc" ],
emit => '. mov%XXM %AM, %D0',
attr => "ir_mode *load_mode",
init_attr => "attr->ls_mode = load_mode;",
- outs => [ "res", "M" ],
latency => 0,
units => [ "SSE" ],
},
xStore => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
emit => '. mov%XXM %S3, %AM',
latency => 0,
units => [ "SSE" ],
},
-l_X87toSSE => {
+l_LLtoFloat => {
op_flags => "L|F",
cmp_attr => "return 1;",
- arity => 3,
+ ins => [ "val_high", "val_low" ],
},
-l_SSEtoX87 => {
+l_FloattoLL => {
op_flags => "L|F",
cmp_attr => "return 1;",
- arity => 3,
+ ins => [ "val" ],
+ outs => [ "res_high", "res_low" ],
},
# CopyB
# Conversions
+Cwtl => {
+ state => "exc_pinned",
+ reg_req => { in => [ "eax" ], out => [ "eax" ] },
+ ins => [ "val" ],
+ outs => [ "res" ],
+ emit => '. cwtl',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+},
+
Conv_I2I => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "res", "M" ],
am => "source,unary",
units => [ "GP" ],
latency => 1,
am => "source,unary",
latency => 10,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm,
},
Conv_FP2I => {
am => "source,unary",
latency => 8,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm,
},
#----------------------------------------------------------#
# irn_flags => "R",
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
- ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
+ ins => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ],
am => "source,binary",
latency => 4,
units => [ "VFP" ],
vfdiv => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] },
- ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
+ ins => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ],
am => "source,binary",
outs => [ "res", "M" ],
latency => 20,
irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M" ],
+ outs => [ "res", "M", "X_exc" ],
attr => "ir_mode *load_mode",
init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none", "vfp" ] },
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] },
ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
attr => "ir_mode *store_mode",
init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
attr_type => "ia32_x87_attr_t",
},
-l_vfild => {
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
vfist => {
state => "exc_pinned",
reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] },
attr_type => "ia32_x87_attr_t",
},
-l_vfist => {
- cmp_attr => "return 1;",
+# SSE3 fisttp instruction
+vfisttp => {
state => "exc_pinned",
- arity => 3,
- mode => "mode_M",
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "in_r4", "none" ]},
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "res", "M" ],
+ latency => 4,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
},
vfldz => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfld1 => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfldpi => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfldln2 => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfldlg2 => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfldl2t => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
vfldl2e => {
irn_flags => "R",
reg_req => { out => [ "vfp" ] },
+ outs => [ "res" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fild%M %AM',
+ emit => '. fild%XM %AM',
attr_type => "ia32_x87_attr_t",
latency => 2,
},
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fist%M %AM',
+ emit => '. fist%XM %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
latency => 2,
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fistp%M %AM',
+ emit => '. fistp%XM %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+ latency => 2,
+},
+
+# SSE3 firsttp instruction
+fisttp => {
+ state => "exc_pinned",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fisttp%XM %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
latency => 2,
FucomFnstsw => {
reg_req => { },
emit => ". fucom %X1\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
FucompFnstsw => {
reg_req => { },
emit => ". fucomp %X1\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
FucomppFnstsw => {
reg_req => { },
emit => ". fucompp\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
FtstFnstsw => {
reg_req => { },
emit => ". ftst\n".
- ". fnstsw",
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
latency => 2,
},
$node->{op_attr_init} = $op_attr_init;
}
-print "ok";
+print "";
projects / libfirm / blobdiff