$arch = "ia32";
+# this string marks the beginning of a comment in emit
+$comment_string = "/*";
+
# The node description is done as a perl hash initializer with the
# following structure:
#
# %nodes = (
#
# <op-name> => {
-# "op_flags" => "N|L|C|X|I|F|Y|H|c",
-# "arity" => "0|1|2|3|variable|dynamic|all",
-# "state" => "floats|pinned",
-# "args" => [
-# { "type" => "type 1", "name" => "name 1" },
-# { "type" => "type 2", "name" => "name 2" },
-# ...
-# ],
-# "comment" => "any comment for constructor",
+# "op_flags" => "N|L|C|X|I|F|Y|H|c|K",
+# "irn_flags" => "R|N|I"
+# "arity" => "0|1|2|3 ... |variable|dynamic|any",
+# "state" => "floats|pinned|mem_pinned|exc_pinned",
+# "args" => [
+# { "type" => "type 1", "name" => "name 1" },
+# { "type" => "type 2", "name" => "name 2" },
+# ...
+# ],
+# "comment" => "any comment for constructor",
+# "reg_req" => { "in" => [ "reg_class|register" ], "out" => [ "reg_class|register|in_rX" ] },
+# "cmp_attr" => "c source code for comparing node attributes",
+# "emit" => "emit code with templates",
# "rd_constructor" => "c source code which constructs an ir_node"
# },
#
#
# ); # close the %nodes initializer
+# op_flags: flags for the operation, OPTIONAL (default is "N")
# the op_flags correspond to the firm irop_flags:
# N irop_flag_none
# L irop_flag_labeled
# Y irop_flag_forking
# H irop_flag_highlevel
# c irop_flag_constlike
+# K irop_flag_keep
#
-# op_flags: flags for the operation, OPTIONAL (default is "N")
+# irn_flags: special node flags, OPTIONAL (default is 0)
+# following irn_flags are supported:
+# R rematerializeable
+# N not spillable
+# I ignore for register allocation
#
-# state: state of the operation, OPTIONAL (default is "pinned")
+# state: state of the operation, OPTIONAL (default is "floats")
#
# arity: arity of the operation, MUST NOT BE OMITTED
#
# set in[i] = op_i
# done
# res = new_ir_node(db, irg, block, op_<arch>_<op-name>, mode, arity, in)
-# res = optimize_node(res)
-# IRN_VRFY_IRG(res, irg)
# return res
#
# NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
+# register types:
+# 0 - no special type
+# 1 - caller save (register must be saved by the caller of a function)
+# 2 - callee save (register must be saved by the called function)
+# 4 - ignore (do not assign this register)
+# NOTE: Last entry of each class is the largest Firm-Mode a register can hold
%reg_classes = (
- "general_purpose" => [
- { "name" => "eax", "type" => 0 },
- { "name" => "ebx", "type" => 0 },
- { "name" => "ecx", "type" => 0 },
- { "name" => "edx", "type" => 0 },
- { "name" => "edi", "type" => 0 },
- { "name" => "esi", "type" => 0 },
- { "name" => "ebp", "type" => 0 }
- ],
- "floating_point" => [
- { "name" => "xmm0", "type" => 0 },
- { "name" => "xmm1", "type" => 0 },
- { "name" => "xmm2", "type" => 0 },
- { "name" => "xmm3", "type" => 0 },
- { "name" => "xmm4", "type" => 0 },
- { "name" => "xmm5", "type" => 0 },
- { "name" => "xmm6", "type" => 0 },
- { "name" => "xmm7", "type" => 0 },
- ],
- "flag_register" => [
- { "name" => "eflags", "type" => 0 }
- ]
+ "gp" => [
+ { "name" => "eax", "type" => 1 },
+ { "name" => "edx", "type" => 1 },
+ { "name" => "ebx", "type" => 2 },
+ { "name" => "ecx", "type" => 1 },
+ { "name" => "esi", "type" => 2 },
+ { "name" => "edi", "type" => 2 },
+ { "name" => "ebp", "type" => 2 },
+ { "name" => "esp", "type" => 4 },
+ { "name" => "xxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
+ { "mode" => "mode_P" }
+ ],
+ "fp" => [
+ { "name" => "xmm0", "type" => 1 },
+ { "name" => "xmm1", "type" => 1 },
+ { "name" => "xmm2", "type" => 1 },
+ { "name" => "xmm3", "type" => 1 },
+ { "name" => "xmm4", "type" => 1 },
+ { "name" => "xmm5", "type" => 1 },
+ { "name" => "xmm6", "type" => 1 },
+ { "name" => "xmm7", "type" => 1 },
+ { "name" => "xxxx", "type" => 6 }, # we need a dummy register for NoReg and Unknown nodes
+ { "mode" => "mode_D" }
+ ]
); # %reg_classes
#--------------------------------------------------#
%nodes = (
-# arithmetic operations
+#-----------------------------------------------------------------#
+# _ _ _ #
+# (_) | | | | #
+# _ _ __ | |_ ___ __ _ ___ _ __ _ __ ___ __| | ___ ___ #
+# | | '_ \| __/ _ \/ _` |/ _ \ '__| | '_ \ / _ \ / _` |/ _ \/ __| #
+# | | | | | || __/ (_| | __/ | | | | | (_) | (_| | __/\__ \ #
+# |_|_| |_|\__\___|\__, |\___|_| |_| |_|\___/ \__,_|\___||___/ #
+# __/ | #
+# |___/ #
+#-----------------------------------------------------------------#
# commutative operations
-"Add" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. addl %s2, %d1\t\t\t/* Add(%s1, %s2) -> %d1 */'
-},
+# NOTE:
+# All nodes supporting Addressmode have 5 INs:
+# 1 - base r1 == NoReg in case of no AM or no base
+# 2 - index r2 == NoReg in case of no AM or no index
+# 3 - op1 r3 == always present
+# 4 - op2 r4 == NoReg in case of immediate operation
+# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
-"Add_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Add: Add(a, const) = Add(const, a) = a + const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. addl %c, %d1\t\t\t/* Add(%c, %s1) -> %d1 */'
+"Add" => {
+ "irn_flags" => "R",
+ "comment" => "construct Add: Add(a, b) = Add(b, a) = a + b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. add %ia32_emit_binop /* Add(%A1, %A2) -> %D1 */'
},
"Mul" => {
- "op_flags" => "C",
- "arity" => 2,
- "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
- "reg_req" => { "in" => [ "eax", "general_purpose" ], "out" => [ "eax" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %s2\t\t\t/* signed Mul(%s1, %s2) -> %d1 */
- }
- else {
-4. mull %s2\t\t\t/* unsigned Mul(%s1, %s2) -> %d1 */
- }
-'
-},
-
-"Mul_i" => {
- "state" => "pinned",
- "arity" => 1,
- "comment" => "construct Mul: Mul(a, const) = Mul(const, a) = a * const",
-# "reg_req" => { "in" => [ "eax" ], "out" => [ "eax" ] },
- "reg_req" => { "in" => [ "!eax" ], "out" => [ "eax" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %c\t\t\t/* signed Mul(%c, %s1) -> %d1 */
- }
- else {
-4. mull %c\t\t\t/* unsigned Mul(%c, %s1) -> %d1 */
- }
-'
+ "irn_flags" => "A",
+ "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. imul %ia32_emit_binop /* Mul(%A1, %A2) -> %D1 */'
},
+# Mulh is an exception from the 4 INs with AM because the target is always EAX:EDX
"Mulh" => {
- "op_flags" => "C",
- "arity" => 2,
- "comment" => "construct Mulh: Mulh(a, b) = Mulh(b, a) = get_32_highest_bits(a * b)",
- "reg_req" => { "in" => [ "eax", "general_purpose" ], "out" => [ "edx" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %s2\t\t\t/* signed Mulh(%s1, %s2) -> %d1 */
- }
- else {
-4. mull %s2\t\t\t/* unsigned Mulh(%s1, %s2) -> %d1 */
- }
-'
-},
-
-"Mulh_i" => {
- "state" => "pinned",
- "arity" => 1,
- "comment" => "construct Mulh: Mulh(a, const) = Mulh(const, a) = get_32_highest_bits(a * const)",
- "reg_req" => { "in" => [ "eax" ], "out" => [ "edx" ] },
- "emit" =>
-' if (mode_is_signed(get_irn_mode(n))) {
-4. imull %c\t\t\t/* signed Mulh(%c, %s1) -> %d1 */
- }
- else {
-4. mull %c\t\t\t/* unsigned Mulh(%c, %s1) -> %d1 */
- }
-'
+ "comment" => "construct Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "eax in_r3", "edx in_r4" ] },
+ "emit" => '. imul %ia32_emit_unop /* Mulh(%A1, %A2) -> %D1 */'
},
"And" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. andl %s2, %d1\t\t\t/* And(%s1, %s2) -> %d1 */'
-},
-
-"And_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct And: And(a, const) = And(const, a) = a AND const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. andl %c, %d1\t\t\t/* And(%c, %s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct And: And(a, b) = And(b, a) = a AND b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. and %ia32_emit_binop /* And(%A1, %A2) -> %D1 */'
},
"Or" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. orl %s2, %d1\t\t\t/* Or(%s1, %s2) -> %d1 */'
-},
-
-"Or_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Or: Or(a, const) = Or(const, a) = a OR const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. orl %c, %d1\t\t\t/* Or(%c, %s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Or: Or(a, b) = Or(b, a) = a OR b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. or %ia32_emit_binop /* Or(%A1, %A2) -> %D1 */'
},
"Eor" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. xorl %s2, %d1\t\t\t/* Xor(%s1, %s2) -> %d1 */'
-},
-
-"Eor_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Eor: Eor(a, const) = Eor(const, a) = a EOR const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. xorl %c, %d1\t\t\t/* Xor(%c, %s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Eor: Eor(a, b) = Eor(b, a) = a EOR b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. xor %ia32_emit_binop /* Xor(%A1, %A2) -> %D1 */'
},
"Max" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" =>
-'2. cmpl %s2, %s1\t\t\t/* prepare Max (%s1 should be %d1) */
+ "irn_flags" => "R",
+ "comment" => "construct Max: Max(a, b) = Max(b, a) = a > b ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
+ "emit" =>
+'2. cmp %S1, %S2 /* prepare Max (%S1 - %S2), (%A1, %A2) */
if (mode_is_signed(get_irn_mode(n))) {
-4. cmovl %s2, %d1\t\t\t/* %s1 is less %s2 */
+4. cmovl %D1, %S2 /* %S1 is less %S2 */
}
else {
-4. cmovb %s2, %d1\t\t\t/* %s1 is below %s2 */
+4. cmovb %D1, %S2 /* %S1 is below %S2 */
}
'
},
"Min" => {
- "op_flags" => "C",
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" =>
-'2. cmpl %s2, %s1\t\t\t/* prepare Min (%s1 should be %d1) */
+ "irn_flags" => "R",
+ "comment" => "construct Min: Min(a, b) = Min(b, a) = a < b ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "in_r1" ] },
+ "emit" =>
+'2. cmp %S1, %S2 /* prepare Min (%S1 - %S2), (%A1, %A2) */
if (mode_is_signed(get_irn_mode(n))) {
-2. cmovg %s2, %d1\t\t\t/* %s1 is greater %s2 */
+2. cmovg %D1, %S2 /* %S1 is greater %S2 */
}
else {
-2. cmova %s2, %d1\t\t\t/* %s1 is above %s2 */
+2. cmova %D1, %S2, %D1 /* %S1 is above %S2 */
}
'
},
+"CMov" => {
+ "irn_flags" => "R",
+ "comment" => "construct Mux: Mux(sel, a, b) == sel ? a : b",
+ "reg_req" => { "in" => [ "gp", "gp", "gp" ], "out" => [ "in_r2" ] },
+ "emit" =>
+'. cmp %S1, 0 /* compare Sel for CMov (%A2, %A3) */
+. cmovne %D1, %S3 /* sel == true -> return %S3 */
+'
+},
+
# not commutative operations
"Sub" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Sub: Sub(a, b) = a - b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. subl %s2, %d1\t\t\t/* Sub(%s1, %s2) -> %d1 */'
-},
-
-"Sub_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Sub: Sub(a, const) = a - const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. subl %c, %d1\t\t\t/* Sub(%s1, %c) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Sub: Sub(a, b) = a - b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. sub %ia32_emit_binop /* Sub(%A1, %A2) -> %D1 */'
},
"DivMod" => {
- "arity" => 4,
- "comment" => "construct DivMod: DivMod(a,b) = (a / b, a % b)",
- "reg_req" => { "in" => [ "eax", "general_purpose", "edx" ], "out" => [ "eax", "edx" ] },
- "emit" =>
+ "op_flags" => "F|L",
+ "state" => "exc_pinned",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "eax in_r1", "edx in_r3" ] },
+ "emit" =>
' if (mode_is_signed(get_irn_mode(n))) {
-4. idivl %s2\t\t\t/* signed Mod(%s1, %s2) -> %d1 */
- }
- else {
-4. divl %s2\t\t\t/* unsigned Mod(%s1, %s2) -> %d1 */
- }
-',
- "args" => [
- { "type" => "ir_node *", "name" => "mem" },
- { "type" => "ir_node *", "name" => "divisor" },
- { "type" => "ir_node *", "name" => "dividend" },
- { "type" => "divmod_flavour_t", "name" => "dm_flav" }, # flavours (flavour_Div, flavour_Mod, flavour_DivMod)
- { "type" => "ir_mode *", "name" => "mode" },
- ],
- "rd_constructor" =>
-" ir_node *res;
- ir_node *in[4];
-
- if (!op_ia32_DivMod) assert(0);
-
- in[0] = mem;
- in[2] = dividend;
-
- if (mode_is_signed(mode)) {
- ir_node *cltd;
- /* in signed mode , we need to sign extend the divisor */
- cltd = new_rd_ia32_Cltd(db, current_ir_graph, block, divisor, mode_T);
- in[1] = new_rd_Proj(db, current_ir_graph, block, cltd, mode, pn_EAX);
- in[3] = new_rd_Proj(db, current_ir_graph, block, cltd, mode, pn_EDX);
+4. idiv %S2 /* signed DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
else {
- in[1] = divisor;
- in[3] = new_rd_ia32_Const(db, current_ir_graph, block, mode);
- set_ia32_Const_type(in[2], asmop_Const);
- set_ia32_Immop_tarval(in[2], get_tarval_null(mode_Iu));
+4. div %S2 /* unsigned DivMod(%S1, %S2) -> %D1, (%A1, %A2, %A3) */
}
-
- res = new_ir_node(db, irg, block, op_ia32_DivMod, mode, 4, in);
- res = optimize_node(res);
- irn_vrfy_irg(res, irg);
-
- set_ia32_DivMod_flavour(res, dm_flav);
- set_ia32_n_res(res, 2);
-
- return res;
-"
+'
},
"Shl" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Shl: Shl(a, b) = a << b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shll %s2, %d1\t\t\t/* Shl(%s1, %s2) -> %d1 */'
-},
-
-"Shl_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Shl: Shl(a, const) = a << const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shll %c, %d1\t\t\t/* Shl(%s1, %c) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Shl: Shl(a, b) = a << b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "emit" => '. shl %ia32_emit_binop /* Shl(%A1, %A2) -> %D1 */'
},
"Shr" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Shr: Shr(a, b) = a >> b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shrl %s2, %d1\t\t\t/* Shr(%s1, %s2) -> %d1 */'
-},
-
-"Shr_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Shr: Shr(a, const) = a >> const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. shrl %c, %d1\t\t\t/* Shr(%s1, %c) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Shr: Shr(a, b) = a >> b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "emit" => '. shr %ia32_emit_binop /* Shr(%A1, %A2) -> %D1 */'
},
"Shrs" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Shrs: Shrs(a, b) = a >> b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. sarl %s2, %d1\t\t\t/* Shrs(%s1, %s2) -> %d1 */'
-},
-
-"Shrs_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Shrs: Shrs(a, const) = a >> const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. sarl %c, %d1\t\t\t/* Shrs(%s1, %c) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Shrs: Shrs(a, b) = a >> b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "emit" => '. sar %ia32_emit_binop /* Shrs(%A1, %A2) -> %D1 */'
},
"RotR" => {
- "arity" => 2,
- "remat" => 1,
+ "irn_flags" => "R",
"comment" => "construct RotR: RotR(a, b) = a ROTR b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. rorl %s2, %d1\t\t\t/* RotR(%s1, %s2) -> %d1 */'
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "emit" => '. ror %ia32_emit_binop /* RotR(%A1, %A2) -> %D1 */'
},
"RotL" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct RotL: RotL(a, b) = a ROTL b",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. roll %s2, %d1\t\t\t/* RotL(%s1, %s2) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct RotL: RotL(a, b) = a ROTL b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "ecx", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "emit" => '. rol %ia32_emit_binop /* RotL(%A1, %A2) -> %D1 */'
},
-"RotL_i" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct RotL: RotL(a, const) = a ROTL const",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. roll %c, %d1\t\t\t/* RotL(%s1, %c) -> %d1 */'
-},
+# unary operations
"Minus" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Minus: Minus(a) = -a",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. negl %d1\t\t\t/* Neg(%s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Minus: Minus(a) = -a",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. neg %ia32_emit_unop /* Neg(%A1) -> %D1, (%A1) */'
},
"Inc" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Increment: Inc(a) = a++",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. incl %d1\t\t\t/* Inc(%s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Increment: Inc(a) = a++",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. inc %ia32_emit_unop /* Inc(%S1) -> %D1, (%A1) */'
},
"Dec" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Decrement: Dec(a) = a--",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. decl %d1\t\t\t/* Dec(%s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Decrement: Dec(a) = a--",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. dec %ia32_emit_unop /* Dec(%S1) -> %D1, (%A1) */'
},
"Not" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Not: Not(a) = !a",
- "check_inout" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "emit" => '. notl %d1\t\t\t/* Not(%s1) -> %d1 */'
+ "irn_flags" => "R",
+ "comment" => "construct Not: Not(a) = !a",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. not %ia32_emit_unop /* Not(%S1) -> %D1, (%A1) */'
},
# other operations
-"Conv" => {
- "arity" => 1,
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "in_s1" ] },
- "comment" => "construct Conv: Conv(a) = (conv)a"
-},
-
-"Cmp" => {
- "op_flags" => "C",
- "arity" => 2,
- "comment" => "construct Cmp: Cmp(a, b) = a CMP b",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "flag_register" ] },
- "emit" => '. cmpl %s2, %s1\t\t\t/* Cmp(%s1, %s2) -> flags */'
+"CondJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "construct conditional jump: CMP A, B && JMPxx LABEL",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "gp", "none" ], "out" => [ "none", "none" ] },
},
-"Cmp_i" => {
- "arity" => 1,
- "comment" => "construct Cmp: Cmp(a, const) = Cmp(const, a) = a CMP const",
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "flag_register" ] },
- "emit" => '. cmpl %c, %s1\t\t\t/* Cmp(%s1, %c) -> flags */'
+"TestJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "construct conditional jump: TEST A, B && JMPxx LABEL",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "none" ] },
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
},
-"Cond" => {
- "arity" => 1,
- "comment" => "construct Cond: evaluate Cmp node",
- "reg_req" => { "in" => [ "flag_register" ] }
+"SwitchJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "construct switch",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp" ], "out" => [ "none" ] },
},
"Const" => {
- "arity" => "0",
- "remat" => 1,
- "comment" => "represents an integer constant",
- "reg_req" => { "out" => [ "general_purpose" ] }
+ "op_flags" => "c",
+ "irn_flags" => "R",
+ "comment" => "represents an integer constant",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "out" => [ "gp" ] },
+ "emit" =>
+' if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
+4. sub %D1, %D1 /* optimized mov 0 to register */
+ }
+ else {
+4. mov %D1, %C /* Mov Const into register */
+ }
+',
},
-"Cltd" => {
- "arity" => 1,
- "remat" => 1,
- "comment" => "construct Cltd: sign extend EAX -> EDX:EAX",
- "reg_req" => { "in" => [ "eax" ], "out" => [ "eax", "edx" ] },
- "emit" => '. cltd\t\t\t/* sign extend EAX -> EDX:EAX */'
+"Cdq" => {
+ "irn_flags" => "R",
+ "comment" => "construct CDQ: sign extend EAX -> EDX:EAX",
+ "reg_req" => { "in" => [ "gp" ], "out" => [ "eax in_r1", "edx" ] },
+ "emit" => '. cdq /* sign extend EAX -> EDX:EAX, (%A1) */'
},
# Load / Store
"Load" => {
- "arity" => 2,
- "remat" => 1,
- "comment" => "construct Load: Load(mem-edge, ptr) = LD ptr",
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
- "emit" => '. movl (%s1), %d1\t\t\t/* Load((%s1)) -> %d1 */'
+ "op_flags" => "L|F",
+ "irn_flags" => "R",
+ "state" => "exc_pinned",
+ "comment" => "construct Load: Load(ptr, mem) = LD ptr -> reg",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "gp" ] },
+ "emit" =>
+' if (get_mode_size_bits(get_ia32_ls_mode(n)) < 32) {
+4. mov%Mx %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
+ }
+ else {
+4. mov %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */
+ }
+'
},
"Store" => {
- "arity" => 3,
- "remat" => 1,
- "comment" => "construct Store: Store(mem-edge, ptr, val) = ST ptr,val",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
- "emit" => '. movl %s1, (%d1)\t\t\t/* Store(%s1) -> (%d1) */'
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ] },
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
+},
+
+"Store8Bit" => {
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "construct 8Bit Store: Store(ptr, val, mem) = ST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "eax ebx ecx edx", "none" ] },
+ "emit" => '. mov %ia32_emit_binop /* Store(%A3) -> (%A1) */'
},
"Lea" => {
- "arity" => 2,
- "comment" => "construct Lea: Lea(a,b) = lea offs(a,b,const) | res = a + b * const + offs with const = 0,1,2,4,8",
- "reg_req" => { "in" => [ "general_purpose", "general_purpose" ], "out" => [ "general_purpose" ] },
- "emit" => '. leal %o(%s1, %s2, %c), %d1\t\t\t/* %d1 = %s1 + %s2 << %c + %o */'
+ "irn_flags" => "R",
+ "comment" => "construct Lea: Lea(a,b) = lea [a+b*const+offs] | res = a + b * const + offs with const = 0,1,2,4,8",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp" ], "out" => [ "gp" ] },
+ "emit" => '. lea %D1, %ia32_emit_am /* LEA(%A1, %A2) */'
+},
+
+#--------------------------------------------------------#
+# __ _ _ _ #
+# / _| | | | | | #
+# | |_| | ___ __ _| |_ _ __ ___ __| | ___ ___ #
+# | _| |/ _ \ / _` | __| | '_ \ / _ \ / _` |/ _ \/ __| #
+# | | | | (_) | (_| | |_ | | | | (_) | (_| | __/\__ \ #
+# |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
+#--------------------------------------------------------#
+
+# commutative operations
+
+"fAdd" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Add: Add(a, b) = Add(b, a) = a + b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. adds%M %ia32_emit_binop /* SSE Add(%A3, %A4) -> %D1 */'
},
-"Lea_i" => {
- "arity" => 1,
- "comment" => "construct Lea: Lea(a) = lea offs(a) | res = a + offs",
- "reg_req" => { "in" => [ "general_purpose" ], "out" => [ "general_purpose" ] },
- "emit" => '. leal %c(%s1), %d1\t\t\t/* %d1 = %s1 + %c */'
+"fMul" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Mul: Mul(a, b) = Mul(b, a) = a * b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. muls%M %ia32_emit_binop /* SSE Mul(%A3, %A4) -> %D1 */'
},
-"Jmp" => {
- "arity" => 0,
- "comment" => "construct Jump: Jmp(Label)",
- "emit" => '. jmp %l /* jump to label %l */'
+"fMax" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Max: Max(a, b) = Max(b, a) = a > b ? a : b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. maxs%M %ia32_emit_binop /* SSE Max(%A3, %A4) -> %D1 */'
},
-# Call
+"fMin" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Min: Min(a, b) = Min(b, a) = a < b ? a : b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. mins%M %ia32_emit_binop /* SSE Min(%A3, %A4) -> %D1 */'
+},
-"Call" => {
- "arity" => 1,
- "spill" => 0,
- "comment" => "construct Call: Call(...)",
- "args" => [ { "type" => "ir_node *", "name" => "old_call" } ],
- "rd_constructor" =>
-" ir_node *res;
- ir_node *in[1];
- asmop_attr *attr;
+"fAnd" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE And: And(a, b) = a AND b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. andp%M %ia32_emit_binop /* SSE And(%A3, %A4) -> %D1 */'
+},
- if (!op_ia32_Call) assert(0);
+"fOr" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Or: Or(a, b) = a OR b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. orp%M %ia32_emit_binop /* SSE Or(%A3, %A4) -> %D1 */'
+},
- in[0] = get_Call_mem(old_call);
+"fEor" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Eor: Eor(a, b) = a XOR b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. xorp%M %ia32_emit_binop /* SSE Xor(%A3, %A4) -> %D1 */'
+},
- res = new_ir_node(db, irg, block, op_ia32_Call, mode_T, 1, in);
- res = optimize_node(res);
- irn_vrfy_irg(res, irg);
+# not commutative operations
- attr = get_ia32_attr(res);
- attr->old_ir = old_call;
- attr->n_res = 1;
+"fSub" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Sub: Sub(a, b) = a - b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3" ] },
+ "emit" => '. subs%M %ia32_emit_binop /* SSE Sub(%A1, %A2) -> %D1 */'
+},
- return res;
-"
-}
+"fDiv" => {
+ "irn_flags" => "R",
+ "comment" => "construct SSE Div: Div(a, b) = a / b",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "in_r3 !in_r4" ] },
+ "emit" => '. divs%M %ia32_emit_binop /* SSE Div(%A1, %A2) -> %D1 */'
+},
+
+# other operations
+
+"fCondJmp" => {
+ "op_flags" => "L|X|Y",
+ "comment" => "construct conditional jump: UCOMIS A, B && JMPxx LABEL",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "fp", "none" ], "out" => [ "none", "none" ] },
+},
+
+"fConst" => {
+ "op_flags" => "c",
+ "irn_flags" => "R",
+ "comment" => "represents a SSE constant",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "out" => [ "fp" ] },
+ "emit" => '. mov%M %D1, %C /* Load fConst into register */',
+},
+
+# Load / Store
+
+"fLoad" => {
+ "op_flags" => "L|F",
+ "irn_flags" => "R",
+ "state" => "exc_pinned",
+ "comment" => "construct SSE Load: Load(ptr, mem) = LD ptr",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "none" ], "out" => [ "fp" ] },
+ "emit" => '. movs%M %D1, %ia32_emit_am /* Load((%A1)) -> %D1 */'
+},
+
+"fStore" => {
+ "op_flags" => "L|F",
+ "state" => "exc_pinned",
+ "comment" => "construct Store: Store(ptr, val, mem) = ST ptr,val",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ] },
+ "emit" => '. movs%M %ia32_emit_am, %S3 /* Store(%S3) -> (%A1) */'
+},
+
+# CopyB
+
+"CopyB" => {
+ "op_flags" => "F|H",
+ "state" => "pinned",
+ "comment" => "implements a memcopy: CopyB(dst, src, size, mem) == memcpy(dst, src, size)",
+ "reg_req" => { "in" => [ "edi", "esi", "ecx", "none" ], "out" => [ "none" ] },
+},
+
+"CopyB_i" => {
+ "op_flags" => "F|H",
+ "state" => "pinned",
+ "comment" => "implements a memcopy: CopyB(dst, src, mem) == memcpy(dst, src, attr(size))",
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "reg_req" => { "in" => [ "edi", "esi", "none" ], "out" => [ "none" ] },
+},
+
+# Conversions
+
+"Conv_I2FP" => {
+ "reg_req" => { "in" => [ "gp", "gp", "gp", "none" ], "out" => [ "fp", "none" ] },
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Int -> Floating Point"
+},
+
+"Conv_FP2I" => {
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "gp", "none" ] },
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Floating Point -> Int"
+},
+
+"Conv_FP2FP" => {
+ "reg_req" => { "in" => [ "gp", "gp", "fp", "none" ], "out" => [ "fp", "none" ] },
+ "cmp_attr" => " return ia32_compare_immop_attr(attr_a, attr_b);\n",
+ "comment" => "construct Conv Floating Point -> Floating Point",
+},
); # end of %nodes
projects / libfirm / blobdiff