# comment => "any comment for constructor",
# reg_req => { in => [ "reg_class|register" ], out => [ "reg_class|register|in_rX" ] },
# cmp_attr => "c source code for comparing node attributes",
+# outs => { "out1", "out2" } # optional, creates pn_op_out1, ... consts
+# ins => { "in1", "in2" } # optional, creates n_op_in1, ... consts
+# mode => "mode_Iu" # optional, predefines the mode
# emit => "emit code with templates",
-# attr => "attitional attribute arguments for constructor"
-# init_attr => "emit attribute initialization template"
-# rd_constructor => "c source code which constructs an ir_node"
+# attr => "attitional attribute arguments for constructor",
+# init_attr => "emit attribute initialization template",
+# rd_constructor => "c source code which constructs an ir_node",
+# hash_func => "name of the hash function for this operation",
# latency => "latency of this operation (can be float)"
# attr_type => "name of the attribute struct",
# },
# H irop_flag_highlevel
# c irop_flag_constlike
# K irop_flag_keep
+# NB irop_flag_dump_noblock
+# NI irop_flag_dump_noinput
#
# irn_flags: special node flags, OPTIONAL (default is 0)
# following irn_flags are supported:
#
# NOTE: rd_constructor and args are only optional if and only if arity is 0,1,2 or 3
#
-# latency: the latency of the operation, default is 1
-#
# register types:
# 0 - no special type
# NOTE: Last entry of each class is the largest Firm-Mode a register can hold
%reg_classes = (
gp => [
- { name => "eax", type => 1 },
{ name => "edx", type => 1 },
- { name => "ebx", type => 2 },
{ name => "ecx", type => 1 },
+ { name => "eax", type => 1 },
+ { name => "ebx", type => 2 },
{ name => "esi", type => 2 },
{ name => "edi", type => 2 },
{ name => "ebp", type => 2 },
{ name => "mm5", type => 4 },
{ name => "mm6", type => 4 },
{ name => "mm7", type => 4 },
- { mode => "mode_E" }
+ { mode => "mode_E", flags => "manual_ra" }
],
xmm => [
{ name => "xmm0", type => 1 },
{ mode => "mode_E" }
],
vfp => [
- { name => "vf0", type => 1 | 16 },
- { name => "vf1", type => 1 | 16 },
- { name => "vf2", type => 1 | 16 },
- { name => "vf3", type => 1 | 16 },
- { name => "vf4", type => 1 | 16 },
- { name => "vf5", type => 1 | 16 },
- { name => "vf6", type => 1 | 16 },
- { name => "vf7", type => 1 | 16 },
+ { name => "vf0", type => 1 },
+ { name => "vf1", type => 1 },
+ { name => "vf2", type => 1 },
+ { name => "vf3", type => 1 },
+ { name => "vf4", type => 1 },
+ { name => "vf5", type => 1 },
+ { name => "vf6", type => 1 },
+ { name => "vf7", type => 1 },
{ name => "vfp_NOREG", type => 4 | 8 | 16 }, # we need a dummy register for NoReg nodes
{ name => "vfp_UKNWN", type => 4 | 8 | 16 }, # we need a dummy register for Unknown nodes
{ mode => "mode_E" }
{ name => "st5", realname => "st(5)", type => 4 },
{ name => "st6", realname => "st(6)", type => 4 },
{ name => "st7", realname => "st(7)", type => 4 },
- { mode => "mode_E" }
+ { mode => "mode_E", flags => "manual_ra" }
],
fp_cw => [ # the floating point control word
- { name => "fpcw", type => 4 | 32},
- { mode => "mode_fpcw" }
+ { name => "fpcw", type => 4|32 },
+ { mode => "mode_fpcw", flags => "manual_ra|state" }
],
flags => [
- { name => "eflags", type => 4 },
- { mode => "mode_Iu" }
- ],
- fp_sw => [
- { name => "fpsw", type => 4 },
- { mode => "mode_Hu" }
+ { name => "eflags", type => 0 },
+ { mode => "mode_Iu", flags => "manual_ra" }
],
); # %reg_classes
-%flags = (
- CF => { reg => "eflags", bit => 0 },
- PF => { reg => "eflags", bit => 2 },
- AF => { reg => "eflags", bit => 4 },
- ZF => { reg => "eflags", bit => 6 },
- SF => { reg => "eflags", bit => 7 },
- TF => { reg => "eflags", bit => 8 },
- IF => { reg => "eflags", bit => 9 },
- DF => { reg => "eflags", bit => 10 },
- OF => { reg => "eflags", bit => 11 },
- IOPL0 => { reg => "eflags", bit => 12 },
- IOPL1 => { reg => "eflags", bit => 13 },
- NT => { reg => "eflags", bit => 14 },
- RF => { reg => "eflags", bit => 16 },
- VM => { reg => "eflags", bit => 17 },
- AC => { reg => "eflags", bit => 18 },
- VIF => { reg => "eflags", bit => 19 },
- VIP => { reg => "eflags", bit => 20 },
- ID => { reg => "eflags", bit => 21 },
-
- FP_IE => { reg => "fpsw", bit => 0 },
- FP_DE => { reg => "fpsw", bit => 1 },
- FP_ZE => { reg => "fpsw", bit => 2 },
- FP_OE => { reg => "fpsw", bit => 3 },
- FP_UE => { reg => "fpsw", bit => 4 },
- FP_PE => { reg => "fpsw", bit => 5 },
- FP_SF => { reg => "fpsw", bit => 6 },
- FP_ES => { reg => "fpsw", bit => 7 },
- FP_C0 => { reg => "fpsw", bit => 8 },
- FP_C1 => { reg => "fpsw", bit => 9 },
- FP_C2 => { reg => "fpsw", bit => 10 },
- FP_TOP0 => { reg => "fpsw", bit => 11 },
- FP_TOP1 => { reg => "fpsw", bit => 12 },
- FP_TOP2 => { reg => "fpsw", bit => 13 },
- FP_C3 => { reg => "fpsw", bit => 14 },
- FP_B => { reg => "fpsw", bit => 15 },
-
- FP_IM => { reg => "fpcw", bit => 0 },
- FP_DM => { reg => "fpcw", bit => 1 },
- FP_ZM => { reg => "fpcw", bit => 2 },
- FP_OM => { reg => "fpcw", bit => 3 },
- FP_UM => { reg => "fpcw", bit => 4 },
- FP_PM => { reg => "fpcw", bit => 5 },
- FP_PC0 => { reg => "fpcw", bit => 8 },
- FP_PC1 => { reg => "fpcw", bit => 9 },
- FP_RC0 => { reg => "fpcw", bit => 10 },
- FP_RC1 => { reg => "fpcw", bit => 11 },
- FP_X => { reg => "fpcw", bit => 12 }
-); # %flags
-
%cpu = (
GP => [ 1, "GP_EAX", "GP_EBX", "GP_ECX", "GP_EDX", "GP_ESI", "GP_EDI", "GP_EBP" ],
SSE => [ 1, "SSE_XMM0", "SSE_XMM1", "SSE_XMM2", "SSE_XMM3", "SSE_XMM4", "SSE_XMM5", "SSE_XMM6", "SSE_XMM7" ],
); # vliw
%emit_templates = (
- S0 => "${arch}_emit_source_register(env, node, 0);",
- S1 => "${arch}_emit_source_register(env, node, 1);",
- S2 => "${arch}_emit_source_register(env, node, 2);",
- S3 => "${arch}_emit_source_register(env, node, 3);",
- S4 => "${arch}_emit_source_register(env, node, 4);",
- S5 => "${arch}_emit_source_register(env, node, 5);",
- SB0 => "${arch}_emit_8bit_source_register(env, node, 0);",
- SW0 => "${arch}_emit_16bit_source_register(env, node, 0);",
- D0 => "${arch}_emit_dest_register(env, node, 0);",
- D1 => "${arch}_emit_dest_register(env, node, 1);",
- D2 => "${arch}_emit_dest_register(env, node, 2);",
- D3 => "${arch}_emit_dest_register(env, node, 3);",
- D4 => "${arch}_emit_dest_register(env, node, 4);",
- D5 => "${arch}_emit_dest_register(env, node, 5);",
- X0 => "${arch}_emit_x87_name(env, node, 0);",
- X1 => "${arch}_emit_x87_name(env, node, 1);",
- X2 => "${arch}_emit_x87_name(env, node, 2);",
- C => "${arch}_emit_immediate(env, node);",
- SE => "${arch}_emit_extend_suffix(env, get_ia32_ls_mode(node));",
+ S0 => "${arch}_emit_source_register(node, 0);",
+ S1 => "${arch}_emit_source_register(node, 1);",
+ S2 => "${arch}_emit_source_register(node, 2);",
+ S3 => "${arch}_emit_source_register(node, 3);",
+ SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
+ SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
+ SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+ SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
+ SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
+ D0 => "${arch}_emit_dest_register(node, 0);",
+ D1 => "${arch}_emit_dest_register(node, 1);",
+ DB0 => "${arch}_emit_8bit_dest_register(node, 0);",
+ X0 => "${arch}_emit_x87_register(node, 0);",
+ X1 => "${arch}_emit_x87_register(node, 1);",
+ SE => "${arch}_emit_extend_suffix(get_ia32_ls_mode(node));",
ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
- ia32_emit_mode_suffix(env, node);",
- M => "${arch}_emit_mode_suffix(env, node);",
- XM => "${arch}_emit_x87_mode_suffix(env, node);",
- XXM => "${arch}_emit_xmm_mode_suffix(env, node);",
- XSD => "${arch}_emit_xmm_mode_suffix_s(env, node);",
- AM => "${arch}_emit_am(env, node);",
- unop0 => "${arch}_emit_unop(env, node, 0);",
- unop1 => "${arch}_emit_unop(env, node, 1);",
- unop2 => "${arch}_emit_unop(env, node, 2);",
- unop3 => "${arch}_emit_unop(env, node, 3);",
- unop4 => "${arch}_emit_unop(env, node, 4);",
- DAM0 => "${arch}_emit_am_or_dest_register(env, node, 0);",
- DAM1 => "${arch}_emit_am_or_dest_register(env, node, 0);",
- binop => "${arch}_emit_binop(env, node);",
- x87_binop => "${arch}_emit_x87_binop(env, node);",
+ ia32_emit_mode_suffix(node);",
+ M => "${arch}_emit_mode_suffix(node);",
+ XM => "${arch}_emit_x87_mode_suffix(node);",
+ XXM => "${arch}_emit_xmm_mode_suffix(node);",
+ XSD => "${arch}_emit_xmm_mode_suffix_s(node);",
+ AM => "${arch}_emit_am(node);",
+ unop3 => "${arch}_emit_unop(node, n_ia32_unary_op);",
+ unop4 => "${arch}_emit_unop(node, n_ia32_binary_right);",
+ binop => "${arch}_emit_binop(node);",
+ x87_binop => "${arch}_emit_x87_binop(node);",
+ CMP0 => "${arch}_emit_cmp_suffix_node(node, 0);",
+ CMP3 => "${arch}_emit_cmp_suffix_node(node, 3);",
);
#--------------------------------------------------#
# |_| #
#--------------------------------------------------#
-$default_attr_type = "ia32_attr_t";
-$default_copy_attr = "ia32_copy_attr";
+$default_op_attr_type = "ia32_op_attr_t";
+$default_attr_type = "ia32_attr_t";
+$default_copy_attr = "ia32_copy_attr";
+
+sub ia32_custom_init_attr {
+ my $node = shift;
+ my $name = shift;
+ my $res = "";
+
+ if(defined($node->{modified_flags})) {
+ $res .= "\tset_ia32_flags(res, get_ia32_flags(res) | arch_irn_flags_modify_flags);\n";
+ }
+ if(defined($node->{am})) {
+ my $am = $node->{am};
+ if($am eq "source,unary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_unary);";
+ } elsif($am eq "source,binary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_binary);";
+ } elsif($am eq "source,ternary") {
+ $res .= "\tset_ia32_am_support(res, ia32_am_Source, ia32_am_ternary);";
+ } elsif($am eq "none") {
+ # nothing to do
+ } else {
+ die("Invalid address mode '$am' specified on op $name");
+ }
+ if($am ne "none") {
+ if($node->{state} ne "exc_pinned"
+ and $node->{state} ne "pinned") {
+ die("AM nodes must have pinned or AM pinned state ($name)");
+ }
+ }
+ }
+ return $res;
+}
+$custom_init_attr_func = \&ia32_custom_init_attr;
%init_attr = (
- ia32_attr_t => "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);",
- ia32_x87_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
- "\tinit_ia32_x87_attributes(res);",
ia32_asm_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
"\tinit_ia32_x87_attributes(res);".
"\tinit_ia32_asm_attributes(res);",
+ ia32_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);",
+ ia32_condcode_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_condcode_attributes(res, pnc);",
+ ia32_copyb_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_copyb_attributes(res, size);",
ia32_immediate_attr_t =>
- "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res, latency);\n".
- "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);"
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_immediate_attributes(res, symconst, symconst_sign, offset);",
+ ia32_x87_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_x87_attributes(res);",
);
%compare_attr = (
- ia32_attr_t => "ia32_compare_nodes_attr",
- ia32_x87_attr_t => "ia32_compare_x87_attr",
ia32_asm_attr_t => "ia32_compare_asm_attr",
+ ia32_attr_t => "ia32_compare_nodes_attr",
+ ia32_condcode_attr_t => "ia32_compare_condcode_attr",
+ ia32_copyb_attr_t => "ia32_compare_copyb_attr",
ia32_immediate_attr_t => "ia32_compare_immediate_attr",
+ ia32_x87_attr_t => "ia32_compare_x87_attr",
);
%operands = (
);
-$mode_xmm = "mode_E";
-$mode_gp = "mode_Iu";
-$mode_fpcw = "mode_fpcw";
-$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
-$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
- "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
+$mode_xmm = "mode_E";
+$mode_gp = "mode_Iu";
+$mode_flags = "mode_Iu";
+$mode_fpcw = "mode_fpcw";
+$status_flags = [ "CF", "PF", "AF", "ZF", "SF", "OF" ];
+$status_flags_wo_cf = [ "PF", "AF", "ZF", "SF", "OF" ];
+$fpcw_flags = [ "FP_IM", "FP_DM", "FP_ZM", "FP_OM", "FP_UM", "FP_PM",
+ "FP_PC0", "FP_PC1", "FP_RC0", "FP_RC1", "FP_X" ];
%nodes = (
reg_req => { out => [ "gp_NOREG" ] },
attr => "ir_entity *symconst, int symconst_sign, long offset",
attr_type => "ia32_immediate_attr_t",
+ hash_func => "ia32_hash_Immediate",
latency => 0,
mode => $mode_gp,
},
arity => "variable",
out_arity => "variable",
attr_type => "ia32_asm_attr_t",
- latency => 100,
+ attr => "ident *asm_text, const ia32_asm_reg_t *register_map",
+ init_attr => "attr->asm_text = asm_text;\n".
+ "\tattr->register_map = register_map;\n",
+ latency => 10,
+ modified_flags => 1,
},
+# "allocates" a free register
ProduceVal => {
op_flags => "c",
irn_flags => "R",
# commutative operations
-# NOTE:
-# All nodes supporting Addressmode have 5 INs:
-# 1 - base r1 == NoReg in case of no AM or no base
-# 2 - index r2 == NoReg in case of no AM or no index
-# 3 - op1 r3 == always present
-# 4 - op2 r4 == NoReg in case of immediate operation
-# 5 - mem NoMem in case of no AM otherwise it takes the mem from the Load
-
Add => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
emit => '. add%M %binop',
+ am => "source,binary",
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
-Adc => {
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. adc%M %binop',
+AddMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => ". add%M %SI3, %AM",
units => [ "GP" ],
- mode => $mode_gp,
+ latency => 1,
+ mode => "mode_M",
modified_flags => $status_flags
},
-Add64Bit => {
+AddMem8Bit => {
irn_flags => "R",
- arity => 4,
- reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S1, %D1
-. addl %S2, %D0
-. adcl %S3, %D1
-',
- outs => [ "low_res", "high_res" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => ". add%M %SB3, %AM",
units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+Adc => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right", "eflags" ],
+ outs => [ "res", "flags", "M" ],
+ emit => '. adc%M %binop',
+ am => "source,binary",
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
modified_flags => $status_flags
},
l_Add => {
op_flags => "C",
- irn_flags => "R",
- cmp_attr => "return 1;",
- arity => 2,
+ reg_req => { in => [ "none", "none" ], out => [ "none" ] },
+ ins => [ "left", "right" ],
},
l_Adc => {
- op_flags => "C",
- cmp_attr => "return 1;",
- arity => 2,
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
+ ins => [ "left", "right", "eflags" ],
},
Mul => {
# we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
- reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- emit => '. mul%M %unop3',
- outs => [ "EAX", "EDX", "M" ],
- ins => [ "base", "index", "val_high", "val_low", "mem" ],
+ # very strict constraints
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
+ out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ emit => '. mul%M %unop4',
+ outs => [ "res_low", "res_high", "M" ],
+ am => "source,binary",
latency => 10,
units => [ "GP" ],
modified_flags => $status_flags
l_Mul => {
# we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
+ # very strict constraints
op_flags => "C",
cmp_attr => "return 1;",
outs => [ "EAX", "EDX", "M" ],
IMul => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. imul%M %binop',
+ state => "exc_pinned",
+ # TODO: adjust out requirements for the 3 operand form
+ # (no need for should_be_same then)
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
latency => 5,
units => [ "GP" ],
mode => $mode_gp,
IMul1OP => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "eax", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- emit => '. imul%M %unop3',
- outs => [ "EAX", "EDX", "M" ],
- ins => [ "base", "index", "val_high", "val_low", "mem" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax", "gp" ],
+ out => [ "eax", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ emit => '. imul%M %unop4',
+ outs => [ "res_low", "res_high", "M" ],
+ am => "source,binary",
latency => 5,
units => [ "GP" ],
modified_flags => $status_flags
l_IMul => {
op_flags => "C",
cmp_attr => "return 1;",
+ outs => [ "res_low", "res_high", "M" ],
arity => 2
},
And => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
+ op_modes => "commutative | am | immediate | mode_neutral",
+ am => "source,binary",
emit => '. and%M %binop',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
+AndMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. and%M %SI3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+AndMem8Bit => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. and%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Or => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. or%M %binop',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
+OrMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. or%M %SI3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+OrMem8Bit => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. or%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Xor => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4 in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. xor%M %binop',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Xor => {
- op_flags => "C",
- cmp_attr => "return 1;",
- arity => 2,
+XorMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. xor%M %SI3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+XorMem8Bit => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. xor%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
modified_flags => $status_flags
},
Sub => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "in_r4", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
emit => '. sub%M %binop',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
-Sbb => {
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. sbb%M %binop',
+SubMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "subtrahend" ],
+ emit => '. sub%M %SI3, %AM',
units => [ "GP" ],
- mode => $mode_gp,
+ latency => 1,
+ mode => 'mode_M',
modified_flags => $status_flags
},
-Sub64Bit => {
+SubMem8Bit => {
irn_flags => "R",
- arity => 4,
- reg_req => { in => [ "gp", "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S1, %D1
-. subl %S2, %D0
-. sbbl %S3, %D1
-',
- outs => [ "low_res", "high_res" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "subtrahend" ],
+ emit => '. sub%M %SB3, %AM',
units => [ "GP" ],
+ latency => 1,
+ mode => 'mode_M',
+ modified_flags => $status_flags
+},
+
+Sbb => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "flags" ],
+ out => [ "in_r4 !in_r5", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "minuend", "subtrahend", "eflags" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
+ emit => '. sbb%M %binop',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
modified_flags => $status_flags
},
l_Sub => {
- irn_flags => "R",
- cmp_attr => "return 1;",
- arity => 2,
+ reg_req => { in => [ "none", "none" ], out => [ "none" ] },
+ ins => [ "minuend", "subtrahend" ],
},
l_Sbb => {
- cmp_attr => "return 1;",
- arity => 2,
+ reg_req => { in => [ "none", "none", "none" ], out => [ "none" ] },
+ ins => [ "minuend", "subtrahend", "eflags" ],
},
IDiv => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- attr => "ia32_op_flavour_t dm_flav",
- init_attr => "attr->data.op_flav = dm_flav;",
- emit => ". idiv%M %unop4",
- outs => [ "div_res", "mod_res", "M" ],
+ reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
+ out => [ "eax", "flags", "none", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
+ outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
+ am => "source,ternary",
+ emit => ". idiv%M %unop3",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Div => {
op_flags => "F|L",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax", "edx", "gp", "none" ], out => [ "eax", "edx", "none" ] },
- attr => "ia32_op_flavour_t dm_flav",
- init_attr => "attr->data.op_flav = dm_flav;",
- emit => ". div%M %unop4",
- outs => [ "div_res", "mod_res", "M" ],
+ reg_req => { in => [ "gp", "gp", "none", "gp", "eax", "edx" ],
+ out => [ "eax", "flags", "none", "edx", "none" ] },
+ ins => [ "base", "index", "mem", "divisor", "dividend_low", "dividend_high" ],
+ outs => [ "div_res", "flags", "M", "mod_res", "X_exc" ],
+ am => "source,ternary",
+ emit => ". div%M %unop3",
latency => 25,
units => [ "GP" ],
modified_flags => $status_flags
Shl => {
irn_flags => "R",
- # "in_r3" would be enough as out requirement, but the register allocator
- # does strange things then and doesn't respect the constraint for in4
- # if the same value is attached to in3 and in4 (if you have "i << i" in C)
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
- emit => '. shl%M %binop',
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
+ emit => '. shl %SB1, %S0',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Shl => {
- cmp_attr => "return 1;",
- arity => 2
+ShlMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. shl%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+l_ShlDep => {
+ cmp_attr => "return 1;",
+ ins => [ "val", "count", "dep" ],
+ arity => 3
},
ShlD => {
irn_flags => "R",
- # Out requirements is: different from all in
- # This is because, out must be different from LowPart and ShiftCount.
- # We could say "!ecx !in_r4" but it can occur, that all values live through
- # this Shift and the only value dying is the ShiftCount. Then there would be
- # a register missing, as result must not be ecx and all other registers are
- # occupied. What we should write is "!in_r4 !in_r5", but this is not
- # supported (and probably never will). So we create artificial interferences
- # of the result with all inputs, so the spiller can always assure a free
- # register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
- emit =>
-'
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shld%M %%cl, %S3, %AM
- } else {
- . shld%M %%cl, %S3, %S2
- }
-} else {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shld%M %C, %S3, %AM
- } else {
- . shld%M %C, %S3, %S2
- }
-}
-',
+ reg_req => { in => [ "gp", "gp", "ecx" ],
+ out => [ "in_r1 !in_r2 !in_r3", "flags" ] },
+ ins => [ "val_high", "val_low", "count" ],
+ outs => [ "res", "flags" ],
+ emit => ". shld%M %SB2, %S1, %D0",
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShlD => {
cmp_attr => "return 1;",
+ ins => [ "val_high", "val_low", "count" ],
arity => 3,
},
Shr => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. shr%M %binop',
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
+ emit => '. shr %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
+ latency => 1,
+ modified_flags => $status_flags
+},
+
+ShrMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. shr%M %SB3, %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ latency => 1,
modified_flags => $status_flags
},
-l_Shr => {
+l_ShrDep => {
cmp_attr => "return 1;",
- arity => 2
+ ins => [ "val", "count", "dep" ],
+ arity => 3
},
ShrD => {
irn_flags => "R",
- # Out requirements is: different from all in
- # This is because, out must be different from LowPart and ShiftCount.
- # We could say "!ecx !in_r4" but it can occur, that all values live through
- # this Shift and the only value dying is the ShiftCount. Then there would be a
- # register missing, as result must not be ecx and all other registers are
- # occupied. What we should write is "!in_r4 !in_r5", but this is not supported
- # (and probably never will). So we create artificial interferences of the result
- # with all inputs, so the spiller can always assure a free register.
- reg_req => { in => [ "gp", "gp", "gp", "gp", "ecx", "none" ], out => [ "!in" ] },
- emit => '
-if (get_ia32_immop_type(node) == ia32_ImmNone) {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shrd%M %%cl, %S3, %AM
- } else {
- . shrd%M %%cl, %S3, %S2
- }
-} else {
- if (get_ia32_op_type(node) == ia32_AddrModeD) {
- . shrd%M %C, %S3, %AM
- } else {
- . shrd%M %C, %S3, %S2
- }
-}
-',
+ reg_req => { in => [ "gp", "gp", "ecx" ],
+ out => [ "in_r1 !in_r2 !in_r3", "flags" ] },
+ ins => [ "val_high", "val_low", "count" ],
+ outs => [ "res", "flags" ],
+ emit => ". shrd%M %SB2, %S1, %D0",
latency => 6,
units => [ "GP" ],
mode => $mode_gp,
l_ShrD => {
cmp_attr => "return 1;",
- arity => 3
+ arity => 3,
+ ins => [ "val_high", "val_low", "count" ],
},
Sar => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. sar%M %binop',
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
+ emit => '. sar %SB1, %S0',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
-l_Sar => {
+SarMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. sar%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
+l_SarDep => {
cmp_attr => "return 1;",
- arity => 2
+ ins => [ "val", "count", "dep" ],
+ arity => 3
},
Ror => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. ror%M %binop',
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
+ emit => '. ror %SB1, %S0',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
+RorMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. ror%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Rol => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "ecx", "none" ], out => [ "in_r3 !in_r4" ] },
- emit => '. rol%M %binop',
+ reg_req => { in => [ "gp", "ecx" ],
+ out => [ "in_r1 !in_r2", "flags" ] },
+ ins => [ "val", "count" ],
+ outs => [ "res", "flags" ],
+ emit => '. rol %SB1, %S0',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
+RolMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "ecx" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "count" ],
+ emit => '. rol%M %SB3, %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
# unary operations
Neg => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. neg%M %unop2',
- ins => [ "base", "index", "val", "mem" ],
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ emit => '. neg %S0',
+ ins => [ "val" ],
+ outs => [ "res", "flags" ],
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
modified_flags => $status_flags
},
+NegMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. neg%M %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ modified_flags => $status_flags
+},
+
Minus64Bit => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp" ], out => [ "!in", "!in" ] },
- emit => '
-. movl %S0, %D0
-. movl %S0, %D1
-. subl %S1, %D0
-. sbbl %S2, %D1
-',
+ reg_req => { in => [ "gp", "gp" ], out => [ "in_r1", "in_r2" ] },
outs => [ "low_res", "high_res" ],
units => [ "GP" ],
+ latency => 3,
modified_flags => $status_flags
},
-l_Neg => {
- cmp_attr => "return 1;",
- arity => 1,
-},
-
Inc => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. inc%M %unop2',
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
+ outs => [ "res", "flags" ],
+ emit => '. inc %S0',
units => [ "GP" ],
mode => $mode_gp,
- modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+ latency => 1,
+ modified_flags => $status_flags_wo_cf
+},
+
+IncMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. inc%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ latency => 1,
+ modified_flags => $status_flags_wo_cf
},
Dec => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- emit => '. dec%M %unop2',
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
+ outs => [ "res", "flags" ],
+ emit => '. dec %S0',
units => [ "GP" ],
mode => $mode_gp,
- modified_flags => [ "OF", "SF", "ZF", "AF", "PF" ]
+ latency => 1,
+ modified_flags => $status_flags_wo_cf
+},
+
+DecMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. dec%M %AM',
+ units => [ "GP" ],
+ mode => "mode_M",
+ latency => 1,
+ modified_flags => $status_flags_wo_cf
},
Not => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3" ] },
- ins => [ "base", "index", "val", "mem" ],
- emit => '. not%M %unop2',
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1", "flags" ] },
+ ins => [ "val" ],
+ outs => [ "res", "flags" ],
+ emit => '. not %S0',
units => [ "GP" ],
+ latency => 1,
mode => $mode_gp,
- modified_flags => []
+ # no flags modified
+},
+
+NotMem => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ emit => '. not%M %AM',
+ units => [ "GP" ],
+ latency => 1,
+ mode => "mode_M",
+ # no flags modified
+},
+
+Cmc => {
+ reg_req => { in => [ "flags" ], out => [ "flags" ] },
+ emit => '.cmc',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Stc => {
+ reg_req => { out => [ "flags" ] },
+ emit => '.stc',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags
},
# other operations
-CondJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
- out => [ "none", "none"] },
- ins => [ "base", "index", "left", "right", "mem" ],
- outs => [ "false", "true" ],
- attr => "long pnc",
- init_attr => "attr->pn_code = pnc;",
- latency => 3,
- units => [ "BRANCH" ],
+Cmp => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ],
+ out => [ "flags", "none", "none" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags", "unused", "M" ],
+ am => "source,binary",
+ emit => '. cmp%M %binop',
+ attr => "int ins_permuted, int cmp_unsigned",
+ init_attr => "attr->data.ins_permuted = ins_permuted;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Cmp8Bit => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. cmpb %binop',
+ attr => "int ins_permuted, int cmp_unsigned",
+ init_attr => "attr->data.ins_permuted = ins_permuted;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Test => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. test%M %binop',
+ attr => "int ins_permuted, int cmp_unsigned",
+ init_attr => "attr->data.ins_permuted = ins_permuted;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Test8Bit => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx", "eax ebx ecx edx" ] , out => [ "flags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "eflags" ],
+ am => "source,binary",
+ emit => '. testb %binop',
+ attr => "int ins_permuted, int cmp_unsigned",
+ init_attr => "attr->data.ins_permuted = ins_permuted;\n".
+ "\tattr->data.cmp_unsigned = cmp_unsigned;\n",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
+ modified_flags => $status_flags
+},
+
+Set => {
+ #irn_flags => "R",
+ reg_req => { in => [ "eflags" ], out => [ "eax ebx ecx edx" ] },
+ ins => [ "eflags" ],
+ attr_type => "ia32_condcode_attr_t",
+ attr => "pn_Cmp pnc, int ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n".
+ "\tset_ia32_ls_mode(res, mode_Bu);\n",
+ emit => '. set%CMP0 %DB0',
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_gp,
+},
+
+SetMem => {
+ #irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eflags" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem","eflags" ],
+ attr_type => "ia32_condcode_attr_t",
+ attr => "pn_Cmp pnc, int ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;\n".
+ "\tset_ia32_ls_mode(res, mode_Bu);\n",
+ emit => '. set%CMP3 %AM',
+ latency => 1,
+ units => [ "GP" ],
+ mode => 'mode_M',
+},
+
+CMov => {
+ #irn_flags => "R",
+ # (note: leave the false,true order intact to make it compatible with other
+ # ia32_binary ops)
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "gp", "eflags" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "val_false", "val_true", "eflags" ],
+ am => "source,binary",
+ attr_type => "ia32_condcode_attr_t",
+ attr => "int ins_permuted, pn_Cmp pnc",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_gp,
},
-TestJmp => {
+Jcc => {
state => "pinned",
op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ],
- out => [ "none", "none" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
+ reg_req => { in => [ "eflags" ], out => [ "none", "none" ] },
+ ins => [ "eflags" ],
outs => [ "false", "true" ],
- attr => "long pnc",
- init_attr => "attr->pn_code = pnc;",
- latency => 3,
+ attr_type => "ia32_condcode_attr_t",
+ attr => "pn_Cmp pnc",
+ latency => 2,
units => [ "BRANCH" ],
},
state => "pinned",
op_flags => "L|X|Y",
reg_req => { in => [ "gp" ], out => [ "none" ] },
+ mode => "mode_T",
+ attr_type => "ia32_condcode_attr_t",
+ attr => "long pnc",
latency => 3,
units => [ "BRANCH" ],
- mode => "mode_T",
+ modified_flags => $status_flags,
},
IJmp => {
state => "pinned",
op_flags => "X",
- reg_req => { in => [ "gp", "gp", "gp", "none" ] },
- ins => [ "base", "index", "val", "mem" ],
- emit => '. jmp *%unop2',
+ reg_req => { in => [ "gp", "gp", "none", "gp" ] },
+ ins => [ "base", "index", "mem", "target" ],
+ am => "source,unary",
+ emit => '. jmp *%unop3',
+ latency => 1,
units => [ "BRANCH" ],
mode => "mode_X",
- modified_flags => []
},
Const => {
irn_flags => "R",
reg_req => { out => [ "gp" ] },
units => [ "GP" ],
+ attr => "ir_entity *symconst, int symconst_sign, long offset",
+ attr_type => "ia32_immediate_attr_t",
+ latency => 1,
mode => $mode_gp,
},
+GetEIP => {
+ op_flags => "c",
+ reg_req => { out => [ "gp" ] },
+ units => [ "GP" ],
+ latency => 5,
+ mode => $mode_gp,
+ modified_flags => $status_flags,
+},
+
Unknown_GP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB",
irn_flags => "I",
reg_req => { out => [ "gp_UKNWN" ] },
units => [],
emit => "",
+ latency => 0,
mode => $mode_gp
},
Unknown_VFP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB",
irn_flags => "I",
reg_req => { out => [ "vfp_UKNWN" ] },
units => [],
emit => "",
mode => "mode_E",
+ latency => 0,
attr_type => "ia32_x87_attr_t",
},
Unknown_XMM => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB",
irn_flags => "I",
reg_req => { out => [ "xmm_UKNWN" ] },
units => [],
emit => "",
- mode => "mode_E"
+ latency => 0,
+ mode => $mode_xmm
},
NoReg_GP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB|NI",
irn_flags => "I",
reg_req => { out => [ "gp_NOREG" ] },
units => [],
emit => "",
+ latency => 0,
mode => $mode_gp
},
NoReg_VFP => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB|NI",
irn_flags => "I",
reg_req => { out => [ "vfp_NOREG" ] },
units => [],
emit => "",
mode => "mode_E",
+ latency => 0,
attr_type => "ia32_x87_attr_t",
},
NoReg_XMM => {
state => "pinned",
- op_flags => "c",
+ op_flags => "c|NB|NI",
irn_flags => "I",
reg_req => { out => [ "xmm_NOREG" ] },
units => [],
emit => "",
+ latency => 0,
mode => "mode_E"
},
op_flags => "L|F",
state => "pinned",
reg_req => { in => [ "gp", "gp", "none" ], out => [ "fp_cw" ] },
+ ins => [ "base", "index", "mem" ],
latency => 5,
emit => ". fldcw %AM",
mode => $mode_fpcw,
FnstCW => {
op_flags => "L|F",
state => "pinned",
- reg_req => { in => [ "gp", "gp", "fp_cw", "none" ], out => [ "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "fp_cw" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem", "fpcw" ],
latency => 5,
emit => ". fnstcw %AM",
mode => "mode_M",
units => [ "GP" ],
},
+FnstCWNOP => {
+ op_flags => "L|F",
+ state => "pinned",
+ reg_req => { in => [ "fp_cw" ], out => [ "none" ] },
+ ins => [ "fpcw" ],
+ latency => 0,
+ emit => "",
+ mode => "mode_M",
+},
+
Cltd => {
- # we should not rematrialize this node. It produces 2 results and has
- # very strict constrains
+ # we should not rematrialize this node. It has very strict constraints.
reg_req => { in => [ "eax", "edx" ], out => [ "edx" ] },
- ins => [ "val", "globbered" ],
+ ins => [ "val", "clobbered" ],
emit => '. cltd',
+ latency => 1,
mode => $mode_gp,
units => [ "GP" ],
},
Load => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "gp", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M" ],
+ outs => [ "res", "M", "X_exc" ],
latency => 0,
emit => ". mov%SE%ME%.l %AM, %D0",
units => [ "GP" ],
},
-l_Load => {
- op_flags => "L|F",
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
-l_Store => {
- op_flags => "L|F",
- cmp_attr => "return 1;",
- state => "exc_pinned",
- arity => 3,
- mode => "mode_M",
-},
-
Store => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "none" ] },
- ins => [ "base", "index", "val", "mem" ],
- emit => '. mov%M %binop',
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "none", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
+ emit => '. mov%M %SI3, %AM',
latency => 2,
units => [ "GP" ],
mode => "mode_M",
Store8Bit => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => ["none" ] },
- emit => '. mov%M %binop',
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => ["none", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
+ emit => '. mov%M %SB3, %AM',
latency => 2,
units => [ "GP" ],
mode => "mode_M",
Lea => {
irn_flags => "R",
reg_req => { in => [ "gp", "gp" ], out => [ "gp" ] },
+ ins => [ "base", "index" ],
emit => '. leal %AM, %D0',
latency => 2,
units => [ "GP" ],
mode => $mode_gp,
- modified_flags => [],
+# lea doesn't modify the flags, but setting this seems advantageous since it
+# increases chances that the Lea is transformed back to an Add
+ modified_flags => 1,
},
Push => {
- reg_req => { in => [ "gp", "gp", "gp", "esp", "none" ], out => [ "esp", "none" ] },
- emit => '. push%M %unop2',
- ins => [ "base", "index", "val", "stack", "mem" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp", "esp" ], out => [ "esp", "none" ] },
+ ins => [ "base", "index", "mem", "val", "stack" ],
+ emit => '. push%M %unop3',
outs => [ "stack:I|S", "M" ],
+ am => "source,unary",
latency => 2,
units => [ "GP" ],
- modified_flags => [],
},
Pop => {
- reg_req => { in => [ "gp", "gp", "esp", "none" ], out => [ "esp", "gp", "none" ] },
- emit => '. pop%M %DAM1',
- outs => [ "stack:I|S", "res", "M" ],
- ins => [ "base", "index", "stack", "mem" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "none", "esp" ], out => [ "gp", "none", "none", "esp" ] },
+ ins => [ "mem", "stack" ],
+ outs => [ "res", "M", "unused", "stack:I|S" ],
+ emit => '. pop%M %D0',
+ latency => 3, # Pop is more expensive than Push on Athlon
+ units => [ "GP" ],
+},
+
+PopMem => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "esp" ], out => [ "none", "none", "none", "esp" ] },
+ ins => [ "base", "index", "mem", "stack" ],
+ outs => [ "unused0", "M", "unused1", "stack:I|S" ],
+ emit => '. pop%M %AM',
latency => 3, # Pop is more expensive than Push on Athlon
units => [ "GP" ],
- modified_flags => [],
},
Enter => {
},
Leave => {
- reg_req => { in => [ "esp", "ebp" ], out => [ "ebp", "esp" ] },
+ reg_req => { in => [ "ebp" ], out => [ "ebp", "esp" ] },
emit => '. leave',
outs => [ "frame:I", "stack:I|S" ],
latency => 3,
AddSP => {
irn_flags => "I",
- reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "none" ] },
+ ins => [ "base", "index", "mem", "stack", "size" ],
+ am => "source,binary",
emit => '. addl %binop',
- outs => [ "stack:S", "M" ],
+ latency => 1,
+ outs => [ "stack:I|S", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
SubSP => {
#irn_flags => "I",
- reg_req => { in => [ "gp", "gp", "esp", "gp", "none" ], out => [ "in_r3", "gp", "none" ] },
+ state => "pinned",
+ reg_req => { in => [ "gp", "gp", "none", "esp", "gp" ], out => [ "in_r4", "gp", "none" ] },
+ ins => [ "base", "index", "mem", "stack", "size" ],
+ am => "source,binary",
emit => ". subl %binop\n".
". movl %%esp, %D1",
+ latency => 2,
outs => [ "stack:I|S", "addr", "M" ],
units => [ "GP" ],
modified_flags => $status_flags
},
+RepPrefix => {
+ op_flags => "K",
+ state => "pinned",
+ mode => "mode_M",
+ emit => ". rep",
+ latency => 0,
+},
+
LdTls => {
irn_flags => "R",
reg_req => { out => [ "gp" ] },
units => [ "GP" ],
+ latency => 1,
},
-# the int instruction
-int => {
- reg_req => { in => [ "none" ], out => [ "none" ] },
- mode => "mode_M",
- attr => "tarval *tv",
- init_attr => "\tset_ia32_Immop_tarval(res, tv);",
- emit => '. int %C',
+Bt => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp" ], out => [ "flags" ] },
+ ins => [ "left", "right" ],
+ emit => '. bt%M %S1, %S0',
units => [ "GP" ],
- cmp_attr => "return 1;",
+ latency => 1,
+ mode => $mode_flags,
+ modified_flags => $status_flags # only CF is set, but the other flags are undefined
},
-
#-----------------------------------------------------------------------------#
# _____ _____ ______ __ _ _ _ #
# / ____/ ____| ____| / _| | | | | | #
# |_____/_____/|______| |_| |_|\___/ \__,_|\__| |_| |_|\___/ \__,_|\___||___/ #
#-----------------------------------------------------------------------------#
+# produces a 0/+0.0
+xZero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. xorp%XSD %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+xPzero => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pxor %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# produces all 1 bits
+xAllOnes => {
+ irn_flags => "R",
+ reg_req => { out => [ "xmm" ] },
+ emit => '. pcmpeqb %D0, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, dword
+xPslld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. pslld %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift left, qword
+xPsllq => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psllq %SI1, %D0',
+ latency => 3,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# integer shift right, dword
+xPsrld => {
+ irn_flags => "R",
+ reg_req => { in => [ "xmm", "xmm" ], out => [ "in_r1 !in_r2" ] },
+ emit => '. psrld %SI1, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
+# mov from integer to SSE register
+xMovd => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp" ], out => [ "xmm" ] },
+ emit => '. movd %S0, %D0',
+ latency => 1,
+ units => [ "SSE" ],
+ mode => $mode_xmm
+},
+
# commutative operations
xAdd => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. add%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMul => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. mul%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMax => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. max%XXM %binop',
latency => 2,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xMin => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. min%XXM %binop',
latency => 2,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xAnd => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. andp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xOr => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. orp%XSD %binop',
+ latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xXor => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. xorp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
# not commutative operations
xAndNot => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ am => "source,binary",
emit => '. andnp%XSD %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xSub => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4" ] },
+ ins => [ "base", "index", "mem", "minuend", "subtrahend" ],
+ am => "source,binary",
emit => '. sub%XXM %binop',
latency => 4,
units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_xmm
},
xDiv => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4", "none" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "in_r4 !in_r5", "none" ] },
+ ins => [ "base", "index", "mem", "dividend", "divisor" ],
+ am => "source,binary",
outs => [ "res", "M" ],
emit => '. div%XXM %binop',
latency => 16,
# other operations
-xCmp => {
+Ucomi => {
irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "in_r3 !in_r4" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm", "xmm" ], out => [ "eflags" ] },
+ ins => [ "base", "index", "mem", "left", "right" ],
+ outs => [ "flags" ],
+ am => "source,binary",
+ attr => "int ins_permuted",
+ init_attr => "attr->data.ins_permuted = ins_permuted;",
+ emit => ' .ucomi%XXM %binop',
latency => 3,
units => [ "SSE" ],
- mode => "mode_E",
-},
-
-xCondJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "none", "none" ] },
- ins => [ "base", "index", "left", "right", "mem" ],
- outs => [ "false", "true" ],
- attr => "long pnc",
- init_attr => "attr->pn_code = pnc;",
- latency => 5,
- units => [ "SSE" ],
-},
-
-xConst => {
- op_flags => "c",
- irn_flags => "R",
- reg_req => { out => [ "xmm" ] },
- emit => '. mov%XXM %C, %D0',
- latency => 2,
- units => [ "SSE" ],
- mode => "mode_E",
+ mode => $mode_flags,
+ modified_flags => 1,
},
# Load / Store
xLoad => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "xmm", "none", "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "res", "M", "X_exc" ],
emit => '. mov%XXM %AM, %D0',
- outs => [ "res", "M" ],
- latency => 2,
+ attr => "ir_mode *load_mode",
+ init_attr => "attr->ls_mode = load_mode;",
+ latency => 0,
units => [ "SSE" ],
},
xStore => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
- emit => '. mov%XXM %binop',
- latency => 2,
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "none", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
+ emit => '. mov%XXM %S3, %AM',
+ latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
xStoreSimple => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
- ins => [ "base", "index", "val", "mem" ],
- emit => '. mov%XXM %S2, %AM',
- latency => 2,
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ emit => '. mov%XXM %S3, %AM',
+ latency => 0,
units => [ "SSE" ],
mode => "mode_M",
},
CvtSI2SS => {
op_flags => "L|F",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
- emit => '. cvtsi2ss %D0, %AM',
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
+ emit => '. cvtsi2ss %unop3, %D0',
latency => 2,
units => [ "SSE" ],
mode => $mode_xmm
CvtSI2SD => {
op_flags => "L|F",
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm" ] },
- emit => '. cvtsi2sd %unop2',
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
+ emit => '. cvtsi2sd %unop3, %D0',
latency => 2,
units => [ "SSE" ],
mode => $mode_xmm
},
-l_X87toSSE => {
+l_LLtoFloat => {
op_flags => "L|F",
cmp_attr => "return 1;",
- arity => 3,
+ ins => [ "val_high", "val_low" ],
},
-l_SSEtoX87 => {
+l_FloattoLL => {
op_flags => "L|F",
cmp_attr => "return 1;",
- arity => 3,
+ ins => [ "val" ],
+ outs => [ "res_high", "res_low" ],
},
# CopyB
CopyB => {
- op_flags => "F|H",
- state => "pinned",
- reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
- outs => [ "DST", "SRC", "CNT", "M" ],
- units => [ "GP" ],
- modified_flags => [ "DF" ]
+ op_flags => "F|H",
+ state => "pinned",
+ reg_req => { in => [ "edi", "esi", "ecx", "none" ], out => [ "edi", "esi", "ecx", "none" ] },
+ outs => [ "DST", "SRC", "CNT", "M" ],
+ attr_type => "ia32_copyb_attr_t",
+ attr => "unsigned size",
+ units => [ "GP" ],
+ latency => 3,
+# we don't care about this flag, so no need to mark this node
+# modified_flags => [ "DF" ]
},
CopyB_i => {
- op_flags => "F|H",
- state => "pinned",
- reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
- outs => [ "DST", "SRC", "M" ],
- units => [ "GP" ],
- modified_flags => [ "DF" ]
+ op_flags => "F|H",
+ state => "pinned",
+ reg_req => { in => [ "edi", "esi", "none" ], out => [ "edi", "esi", "none" ] },
+ outs => [ "DST", "SRC", "M" ],
+ attr_type => "ia32_copyb_attr_t",
+ attr => "unsigned size",
+ units => [ "GP" ],
+ latency => 3,
+# we don't care about this flag, so no need to mark this node
+# modified_flags => [ "DF" ]
},
# Conversions
Conv_I2I => {
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "in_r3", "none" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "gp", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
units => [ "GP" ],
- ins => [ "base", "index", "val", "mem" ],
+ latency => 1,
attr => "ir_mode *smaller_mode",
init_attr => "attr->ls_mode = smaller_mode;",
mode => $mode_gp,
- modified_flags => $status_flags
},
Conv_I2I8Bit => {
- reg_req => { in => [ "gp", "gp", "eax ebx ecx edx", "none" ], out => [ "in_r3", "none" ] },
- ins => [ "base", "index", "val", "mem" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "eax ebx ecx edx" ], out => [ "gp", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
units => [ "GP" ],
+ latency => 1,
attr => "ir_mode *smaller_mode",
init_attr => "attr->ls_mode = smaller_mode;",
mode => $mode_gp,
- modified_flags => $status_flags
},
Conv_I2FP => {
- reg_req => { in => [ "gp", "gp", "gp", "none" ], out => [ "xmm", "none" ] },
- latency => 10,
- units => [ "SSE" ],
- mode => "mode_E",
-},
-
-Conv_FP2I => {
- reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "gp", "none" ] },
- latency => 10,
- units => [ "SSE" ],
- mode => $mode_gp,
-},
-
-Conv_FP2FP => {
- reg_req => { in => [ "gp", "gp", "xmm", "none" ], out => [ "xmm", "none" ] },
- latency => 8,
- units => [ "SSE" ],
- mode => "mode_E",
-},
-
-CmpCMov => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
- ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
- attr => "pn_Cmp pn_code",
- init_attr => "attr->pn_code = pn_code;",
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-TestCMov => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none", "gp", "gp" ], out => [ "in_r7" ] },
- ins => [ "base", "index", "cmp_left", "cmp_right", "mem", "val_true", "val_false" ],
- attr => "pn_Cmp pn_code",
- init_attr => "attr->pn_code = pn_code;",
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-xCmpCMov => {
- irn_flags => "R",
- reg_req => { in => [ "xmm", "xmm", "gp", "gp" ], out => [ "in_r4" ] },
- latency => 5,
- units => [ "SSE" ],
- mode => $mode_gp,
-},
-
-vfCmpCMov => {
- irn_flags => "R",
- reg_req => { in => [ "vfp", "vfp", "gp", "gp" ], out => [ "in_r4" ] },
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ], out => [ "xmm", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
latency => 10,
- units => [ "VFP" ],
- mode => $mode_gp,
- attr_type => "ia32_x87_attr_t",
-},
-
-CmpSet => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
- ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
- attr => "pn_Cmp pn_code",
- init_attr => "attr->pn_code = pn_code;",
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-TestSet => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "gp", "gp", "none" ], out => [ "eax ebx ecx edx" ] },
- ins => [ "base", "index", "cmp_left", "cmp_right", "mem" ],
- attr => "pn_Cmp pn_code",
- init_attr => "attr->pn_code = pn_code;",
- latency => 2,
- units => [ "GP" ],
- mode => $mode_gp,
-},
-
-xCmpSet => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "xmm", "xmm", "none" ], out => [ "eax ebx ecx edx" ] },
- latency => 5,
units => [ "SSE" ],
- mode => $mode_gp,
+ mode => $mode_xmm,
},
-vfCmpSet => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none" ], out => [ "eax ebx ecx edx" ] },
+Conv_FP2I => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "gp", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
latency => 10,
- units => [ "VFP" ],
+ units => [ "SSE" ],
mode => $mode_gp,
- attr_type => "ia32_x87_attr_t",
},
-vfCMov => {
- irn_flags => "R",
- reg_req => { in => [ "vfp", "vfp", "vfp", "vfp" ], out => [ "vfp" ] },
- latency => 10,
- units => [ "VFP" ],
- mode => "mode_E",
- attr_type => "ia32_x87_attr_t",
+Conv_FP2FP => {
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ], out => [ "xmm", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ am => "source,unary",
+ latency => 8,
+ units => [ "SSE" ],
+ mode => $mode_xmm,
},
#----------------------------------------------------------#
# |_| |_|\___/ \__,_|\___||___/ #
#----------------------------------------------------------#
+# rematerialisation disabled for all float nodes for now, because the fpcw
+# handler runs before spilling and we might end up with wrong fpcw then
+
vfadd => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
- ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+# irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
+ am => "source,binary",
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
},
vfmul => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
- ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+# irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "left", "right", "fpcw" ],
+ am => "source,binary",
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
attr_type => "ia32_x87_attr_t",
},
-l_vfmul => {
- op_flags => "C",
- cmp_attr => "return 1;",
- arity => 2,
-},
-
vfsub => {
- irn_flags => "R",
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
- ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+# irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "base", "index", "mem", "minuend", "subtrahend", "fpcw" ],
+ am => "source,binary",
latency => 4,
units => [ "VFP" ],
mode => "mode_E",
attr_type => "ia32_x87_attr_t",
},
-l_vfsub => {
- cmp_attr => "return 1;",
- arity => 2,
-},
-
vfdiv => {
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp", "none" ] },
- ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "vfp", "fpcw" ], out => [ "vfp", "none" ] },
+ ins => [ "base", "index", "mem", "dividend", "divisor", "fpcw" ],
+ am => "source,binary",
outs => [ "res", "M" ],
latency => 20,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
-l_vfdiv => {
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
vfprem => {
- reg_req => { in => [ "gp", "gp", "vfp", "vfp", "none", "fpcw" ], out => [ "vfp" ] },
- ins => [ "base", "index", "left", "right", "mem", "fpcw" ],
+ reg_req => { in => [ "vfp", "vfp", "fpcw" ], out => [ "vfp" ] },
+ ins => [ "left", "right", "fpcw" ],
latency => 20,
units => [ "VFP" ],
mode => "mode_E",
attr_type => "ia32_x87_attr_t",
},
-l_vfprem => {
- cmp_attr => "return 1;",
- arity => 2,
-},
-
vfabs => {
irn_flags => "R",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
# virtual Load and Store
vfld => {
+ irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "vfp", "none", "none" ] },
ins => [ "base", "index", "mem" ],
- outs => [ "res", "M" ],
- attr => "ir_mode *store_mode",
- init_attr => "attr->attr.ls_mode = store_mode;",
+ outs => [ "res", "M", "X_exc" ],
+ attr => "ir_mode *load_mode",
+ init_attr => "attr->attr.ls_mode = load_mode;",
latency => 2,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
},
vfst => {
+ irn_flags => "R",
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "vfp", "none" ] },
- ins => [ "base", "index", "val", "mem" ],
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "none", "none" ] },
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "M", "X_exc" ],
attr => "ir_mode *store_mode",
init_attr => "attr->attr.ls_mode = store_mode;",
latency => 2,
attr_type => "ia32_x87_attr_t",
},
-l_vfild => {
- cmp_attr => "return 1;",
- outs => [ "res", "M" ],
- arity => 2,
-},
-
vfist => {
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "vfp", "fpcw", "none" ] },
- ins => [ "base", "index", "val", "fpcw", "mem" ],
+ reg_req => { in => [ "gp", "gp", "none", "vfp", "fpcw" ] },
+ ins => [ "base", "index", "mem", "val", "fpcw" ],
latency => 4,
units => [ "VFP" ],
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
},
-l_vfist => {
- cmp_attr => "return 1;",
+# SSE3 fisttp instruction
+vfisttp => {
state => "exc_pinned",
- arity => 3,
- mode => "mode_M",
+ reg_req => { in => [ "gp", "gp", "none", "vfp" ], out => [ "in_r4", "none" ]},
+ ins => [ "base", "index", "mem", "val" ],
+ outs => [ "res", "M" ],
+ latency => 4,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
},
attr_type => "ia32_x87_attr_t",
},
-vfConst => {
- op_flags => "c",
- irn_flags => "R",
- reg_req => { out => [ "vfp" ] },
+# other
+
+vFucomFnstsw => {
+# we can't allow to rematerialize this node so we don't have
+# accidently produce Phi(Fucom, Fucom(ins_permuted))
+# irn_flags => "R",
+ reg_req => { in => [ "vfp", "vfp" ], out => [ "eax" ] },
+ ins => [ "left", "right" ],
+ outs => [ "flags" ],
+ attr => "int ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
latency => 3,
units => [ "VFP" ],
- mode => "mode_E",
attr_type => "ia32_x87_attr_t",
+ mode => $mode_gp
},
-# other
-
-vfCondJmp => {
- state => "pinned",
- op_flags => "L|X|Y",
- reg_req => { in => [ "vfp", "vfp" ], out => [ "none", "none", "eax" ] },
+vFucomi => {
+ irn_flags => "R",
+ reg_req => { in => [ "vfp", "vfp" ], out => [ "eflags" ] },
ins => [ "left", "right" ],
- outs => [ "false", "true", "temp_reg_eax" ],
- attr => "long pnc",
- init_attr => "attr->attr.pn_code = pnc;",
- latency => 10,
+ outs => [ "flags" ],
+ attr => "int ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
+ latency => 3,
units => [ "VFP" ],
attr_type => "ia32_x87_attr_t",
+ mode => $mode_gp
+},
+
+vFtstFnstsw => {
+# irn_flags => "R",
+ reg_req => { in => [ "vfp" ], out => [ "eax" ] },
+ ins => [ "left" ],
+ outs => [ "flags" ],
+ attr => "int ins_permuted",
+ init_attr => "attr->attr.data.ins_permuted = ins_permuted;",
+ latency => 3,
+ units => [ "VFP" ],
+ attr_type => "ia32_x87_attr_t",
+ mode => $mode_gp
+},
+
+Sahf => {
+ irn_flags => "R",
+ reg_req => { in => [ "eax" ], out => [ "eflags" ] },
+ ins => [ "val" ],
+ outs => [ "flags" ],
+ emit => '. sahf',
+ latency => 1,
+ units => [ "GP" ],
+ mode => $mode_flags,
},
#------------------------------------------------------------------------#
# are swapped, we work this around in the emitter...
fadd => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. fadd%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
faddp => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. faddp%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fmul => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. fmul%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fmulp => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. fmulp%XM %x87_binop',,
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fsub => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. fsub%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fsubp => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
# see note about gas bugs
emit => '. fsubrp%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fsubr => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
irn_flags => "R",
reg_req => { },
emit => '. fsubr%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fsubrp => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
irn_flags => "R",
reg_req => { },
# see note about gas bugs
emit => '. fsubp%XM %x87_binop',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
fprem => {
- op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
emit => '. fprem1',
+ latency => 20,
attr_type => "ia32_x87_attr_t",
},
# this node is just here, to keep the simulator running
# we can omit this when a fprem simulation function exists
fpremp => {
- op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fprem1',
+ emit => '. fprem1\n'.
+ '. fstp %X0',
+ latency => 20,
attr_type => "ia32_x87_attr_t",
},
fdiv => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. fdiv%XM %x87_binop',
+ latency => 20,
attr_type => "ia32_x87_attr_t",
},
fdivp => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
# see note about gas bugs
emit => '. fdivrp%XM %x87_binop',
+ latency => 20,
attr_type => "ia32_x87_attr_t",
},
fdivr => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
emit => '. fdivr%XM %x87_binop',
+ latency => 20,
attr_type => "ia32_x87_attr_t",
},
fdivrp => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
# see note about gas bugs
emit => '. fdivp%XM %x87_binop',
+ latency => 20,
attr_type => "ia32_x87_attr_t",
},
fabs => {
- op_flags => "R",
rd_constructor => "NONE",
reg_req => { },
emit => '. fabs',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
rd_constructor => "NONE",
reg_req => { },
emit => '. fchs',
+ latency => 4,
attr_type => "ia32_x87_attr_t",
},
reg_req => { },
emit => '. fld%XM %AM',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fst => {
emit => '. fst%XM %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fstp => {
emit => '. fstp%XM %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
# Conversions
fild => {
- op_flags => "R",
+ state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fild%XM %AM',
+ emit => '. fild%M %AM',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fist => {
- op_flags => "R",
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fist%XM %AM',
+ emit => '. fist%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fistp => {
- op_flags => "R",
state => "exc_pinned",
rd_constructor => "NONE",
reg_req => { },
- emit => '. fistp%XM %AM',
+ emit => '. fistp%M %AM',
+ mode => "mode_M",
+ attr_type => "ia32_x87_attr_t",
+ latency => 2,
+},
+
+# SSE3 firsttp instruction
+fisttp => {
+ state => "exc_pinned",
+ rd_constructor => "NONE",
+ reg_req => { },
+ emit => '. fisttp%M %AM',
mode => "mode_M",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
# constants
fldz => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldz',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fld1 => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fld1',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fldpi => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldpi',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fldln2 => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldln2',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fldlg2 => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldlg2',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fldl2t => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldll2t',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
fldl2e => {
op_flags => "R|c|K",
- irn_flags => "R",
- reg_req => { },
+ irn_flags => "R",
+ reg_req => { out => [ "vfp" ] },
emit => '. fldl2e',
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
# fxch, fpush, fpop
cmp_attr => "return 1;",
emit => '. fxch %X0',
attr_type => "ia32_x87_attr_t",
+ mode => "mode_ANY",
+ latency => 1,
},
fpush => {
cmp_attr => "return 1;",
emit => '. fld %X0',
attr_type => "ia32_x87_attr_t",
+ mode => "mode_ANY",
+ latency => 1,
},
fpushCopy => {
- op_flags => "R",
reg_req => { in => [ "vfp"], out => [ "vfp" ] },
cmp_attr => "return 1;",
emit => '. fld %X0',
attr_type => "ia32_x87_attr_t",
+ latency => 1,
},
fpop => {
- op_flags => "R|K",
+ op_flags => "K",
reg_req => { },
cmp_attr => "return 1;",
emit => '. fstp %X0',
attr_type => "ia32_x87_attr_t",
+ mode => "mode_ANY",
+ latency => 1,
+},
+
+ffreep => {
+ op_flags => "K",
+ reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. ffreep %X0',
+ attr_type => "ia32_x87_attr_t",
+ mode => "mode_ANY",
+ latency => 1,
+},
+
+emms => {
+ op_flags => "K",
+ reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. emms',
+ attr_type => "ia32_x87_attr_t",
+ mode => "mode_ANY",
+ latency => 3,
+},
+
+femms => {
+ op_flags => "K",
+ reg_req => { },
+ cmp_attr => "return 1;",
+ emit => '. femms',
+ attr_type => "ia32_x87_attr_t",
+ mode => "mode_ANY",
+ latency => 3,
},
# compare
-fcomJmp => {
- op_flags => "L|X|Y",
+FucomFnstsw => {
reg_req => { },
+ emit => ". fucom %X1\n".
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
-fcompJmp => {
- op_flags => "L|X|Y",
+FucompFnstsw => {
reg_req => { },
+ emit => ". fucomp %X1\n".
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
-fcomppJmp => {
- op_flags => "L|X|Y",
+FucomppFnstsw => {
reg_req => { },
+ emit => ". fucompp\n".
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
-fcomrJmp => {
- op_flags => "L|X|Y",
+Fucomi => {
reg_req => { },
+ emit => '. fucomi %X1',
attr_type => "ia32_x87_attr_t",
+ latency => 1,
},
-fcomrpJmp => {
- op_flags => "L|X|Y",
+Fucompi => {
reg_req => { },
+ emit => '. fucompi %X1',
attr_type => "ia32_x87_attr_t",
+ latency => 1,
},
-fcomrppJmp => {
- op_flags => "L|X|Y",
+FtstFnstsw => {
reg_req => { },
+ emit => ". ftst\n".
+ ". fnstsw %%ax",
attr_type => "ia32_x87_attr_t",
+ latency => 2,
},
emit => '. movdqu %D0, %AM',
outs => [ "res", "M" ],
units => [ "SSE" ],
+ latency => 1,
},
xxStore => {
op_flags => "L|F",
state => "exc_pinned",
- reg_req => { in => [ "gp", "gp", "xmm", "none" ] },
+ reg_req => { in => [ "gp", "gp", "none", "xmm" ] },
+ ins => [ "base", "index", "mem", "val" ],
emit => '. movdqu %binop',
units => [ "SSE" ],
+ latency => 1,
mode => "mode_M",
},
warn "couldn't do $my_script_name: $!" unless defined $return;
warn "couldn't run $my_script_name" unless $return;
}
+
+# Transform some attributes
+foreach my $op (keys(%nodes)) {
+ my $node = $nodes{$op};
+ my $op_attr_init = $node->{op_attr_init};
+
+ if(defined($op_attr_init)) {
+ $op_attr_init .= "\n\t";
+ } else {
+ $op_attr_init = "";
+ }
+
+ if(!defined($node->{latency})) {
+ if($op =~ m/^l_/) {
+ $node->{latency} = 0;
+ } else {
+ die("Latency missing for op $op");
+ }
+ }
+ $op_attr_init .= "attr->latency = ".$node->{latency} . ";";
+
+ $node->{op_attr_init} = $op_attr_init;
+}
+
+print "";
projects / libfirm / blobdiff