# ins => { "in1", "in2" } # optional, creates n_op_in1, ... consts
# mode => "mode_Iu" # optional, predefines the mode
# emit => "emit code with templates",
-# attr => "attitional attribute arguments for constructor",
+# attr => "additional attribute arguments for constructor",
# init_attr => "emit attribute initialization template",
# rd_constructor => "c source code which constructs an ir_node",
# hash_func => "name of the hash function for this operation",
S1 => "${arch}_emit_source_register(node, 1);",
S2 => "${arch}_emit_source_register(node, 2);",
S3 => "${arch}_emit_source_register(node, 3);",
+ SB0 => "${arch}_emit_8bit_source_register_or_immediate(node, 0);",
SB1 => "${arch}_emit_8bit_source_register_or_immediate(node, 1);",
SB2 => "${arch}_emit_8bit_source_register_or_immediate(node, 2);",
SB3 => "${arch}_emit_8bit_source_register_or_immediate(node, 3);",
+ SH0 => "${arch}_emit_8bit_high_source_register(node, 0);",
+ SS0 => "${arch}_emit_16bit_source_register_or_immediate(node, 0);",
+ SI0 => "${arch}_emit_source_register_or_immediate(node, 0);",
SI1 => "${arch}_emit_source_register_or_immediate(node, 1);",
SI3 => "${arch}_emit_source_register_or_immediate(node, 3);",
D0 => "${arch}_emit_dest_register(node, 0);",
D1 => "${arch}_emit_dest_register(node, 1);",
+ DS0 => "${arch}_emit_dest_register_size(node, 0);",
DB0 => "${arch}_emit_8bit_dest_register(node, 0);",
X0 => "${arch}_emit_x87_register(node, 0);",
X1 => "${arch}_emit_x87_register(node, 1);",
- SE => "${arch}_emit_extend_suffix(get_ia32_ls_mode(node));",
- ME => "if(get_mode_size_bits(get_ia32_ls_mode(node)) != 32)\n
- ia32_emit_mode_suffix(node);",
+ EX => "${arch}_emit_extend_suffix(node);",
M => "${arch}_emit_mode_suffix(node);",
XM => "${arch}_emit_x87_mode_suffix(node);",
XXM => "${arch}_emit_xmm_mode_suffix(node);",
ia32_x87_attr_t =>
"\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
"\tinit_ia32_x87_attributes(res);",
+ ia32_climbframe_attr_t =>
+ "\tinit_ia32_attributes(res, flags, in_reqs, out_reqs, exec_units, n_res);\n".
+ "\tinit_ia32_climbframe_attributes(res, count);",
);
%compare_attr = (
ia32_asm_attr_t => "ia32_compare_asm_attr",
- ia32_attr_t => "ia32_compare_nodes_attr",
- ia32_call_attr_t => "ia32_compare_call_attr",
- ia32_condcode_attr_t => "ia32_compare_condcode_attr",
- ia32_copyb_attr_t => "ia32_compare_copyb_attr",
- ia32_immediate_attr_t => "ia32_compare_immediate_attr",
- ia32_x87_attr_t => "ia32_compare_x87_attr",
+ ia32_attr_t => "ia32_compare_nodes_attr",
+ ia32_call_attr_t => "ia32_compare_call_attr",
+ ia32_condcode_attr_t => "ia32_compare_condcode_attr",
+ ia32_copyb_attr_t => "ia32_compare_copyb_attr",
+ ia32_immediate_attr_t => "ia32_compare_immediate_attr",
+ ia32_x87_attr_t => "ia32_compare_x87_attr",
+ ia32_climbframe_attr_t => "ia32_compare_climbframe_attr",
);
%operands = (
modified_flags => $status_flags
},
+Xor0 => {
+ op_flags => "c",
+ irn_flags => "R",
+ reg_req => { out => [ "gp", "flags" ] },
+ outs => [ "res", "flags" ],
+ emit => ". xor%M %D0, %D0",
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
XorMem => {
irn_flags => "R",
state => "exc_pinned",
modified_flags => $status_flags
},
+Sbb0 => {
+ irn_flags => "R",
+ reg_req => { in => [ "flags" ], out => [ "gp", "flags" ] },
+ outs => [ "res", "flags" ],
+ emit => ". sbb%M %D0, %D0",
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
l_Sub => {
reg_req => { in => [ "none", "none" ], out => [ "none" ] },
ins => [ "minuend", "subtrahend" ],
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
- emit => '. shl %SB1, %S0',
+ emit => '. shl%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
- emit => '. shr %SB1, %S0',
+ emit => '. shr%M %SB1, %S0',
units => [ "GP" ],
mode => $mode_gp,
latency => 1,
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
- emit => '. sar %SB1, %S0',
+ emit => '. sar%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
- emit => '. ror %SB1, %S0',
+ emit => '. ror%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
out => [ "in_r1 !in_r2", "flags" ] },
ins => [ "val", "count" ],
outs => [ "res", "flags" ],
- emit => '. rol %SB1, %S0',
+ emit => '. rol%M %SB1, %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
irn_flags => "R",
reg_req => { in => [ "gp" ],
out => [ "in_r1", "flags" ] },
- emit => '. neg %S0',
+ emit => '. neg%M %S0',
ins => [ "val" ],
outs => [ "res", "flags" ],
units => [ "GP" ],
out => [ "in_r1", "flags" ] },
ins => [ "val" ],
outs => [ "res", "flags" ],
- emit => '. inc %S0',
+ emit => '. inc%M %S0',
units => [ "GP" ],
mode => $mode_gp,
latency => 1,
out => [ "in_r1", "flags" ] },
ins => [ "val" ],
outs => [ "res", "flags" ],
- emit => '. dec %S0',
+ emit => '. dec%M %S0',
units => [ "GP" ],
mode => $mode_gp,
latency => 1,
out => [ "in_r1", "flags" ] },
ins => [ "val" ],
outs => [ "res", "flags" ],
- emit => '. not %S0',
+ emit => '. not%M %S0',
units => [ "GP" ],
latency => 1,
mode => $mode_gp,
ins => [ "base", "index", "mem" ],
outs => [ "res", "M", "X_exc" ],
latency => 0,
- emit => ". mov%SE%ME%.l %AM, %D0",
+ emit => ". mov%EX%.l %AM, %D0",
units => [ "GP" ],
},
latency => 1,
},
+#
+# BT supports source address mode, but this is unused yet
+#
Bt => {
irn_flags => "R",
state => "exc_pinned",
modified_flags => $status_flags # only CF is set, but the other flags are undefined
},
+Bsf => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "gp", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "operand" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
+ emit => '. bsf%M %unop3, %D0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
+Bsr => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "gp", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "operand" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
+ emit => '. bsr%M %unop3, %D0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
+#
+# SSE4.2 or SSE4a popcnt instruction
+#
+Popcnt => {
+ irn_flags => "R",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none", "gp" ],
+ out => [ "gp", "flags", "none" ] },
+ ins => [ "base", "index", "mem", "operand" ],
+ outs => [ "res", "flags", "M" ],
+ am => "source,binary",
+ emit => '. popcnt%M %unop3, %D0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+ modified_flags => $status_flags
+},
+
Call => {
state => "exc_pinned",
reg_req => {
modified_flags => $status_flags
},
+#
+# a Helper node for frame-climbing, needed for __builtin_(frame|return)_address
+#
+# PS: try gcc __builtin_frame_address(100000) :-)
+#
+ClimbFrame => {
+ reg_req => { in => [ "gp", "gp", "gp"], out => [ "in_r3" ] },
+ ins => [ "frame", "cnt", "tmp" ],
+ outs => [ "res" ],
+ latency => 4, # random number
+ attr_type => "ia32_climbframe_attr_t",
+ attr => "unsigned count",
+ units => [ "GP" ],
+ mode => $mode_gp
+},
+
+#
+# bswap
+#
+Bswap => {
+ irn_flags => "R",
+ reg_req => { in => [ "gp" ],
+ out => [ "in_r1" ] },
+ emit => '. bswap%M %S0',
+ ins => [ "val" ],
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+},
+
+#
+# bswap16, use xchg here
+#
+Bswap16 => {
+ irn_flags => "R",
+ reg_req => { in => [ "eax ebx ecx edx" ],
+ out => [ "in_r1" ] },
+ emit => '. xchg %SB0, %SH0',
+ ins => [ "val" ],
+ units => [ "GP" ],
+ latency => 1,
+ mode => $mode_gp,
+},
+
+#
+# BreakPoint
+#
+Breakpoint => {
+ state => "pinned",
+ reg_req => { in => [ "none" ], out => [ "none" ] },
+ ins => [ "mem" ],
+ latency => 0,
+ emit => ". int3",
+ units => [ "GP" ],
+ mode => mode_M,
+},
+
+#
+# Undefined Instruction on ALL x86 CPU's
+#
+UD2 => {
+ state => "pinned",
+ reg_req => { in => [ "none" ], out => [ "none" ] },
+ ins => [ "mem" ],
+ latency => 0,
+ emit => ". .value 0x0b0f",
+ units => [ "GP" ],
+ mode => mode_M,
+},
+
+#
+# outport
+#
+Outport => {
+ irn_flags => "R",
+ state => "pinned",
+ reg_req => { in => [ "edx", "eax", "none" ], out => [ "none" ] },
+ ins => [ "port", "value", "mem" ],
+ emit => '. out%M %SS0, %SI1',
+ units => [ "GP" ],
+ latency => 1,
+ mode => mode_M,
+ modified_flags => $status_flags
+},
+
+#
+# inport
+#
+Inport => {
+ irn_flags => "R",
+ state => "pinned",
+ reg_req => { in => [ "edx", "none" ], out => [ "eax", "none" ] },
+ ins => [ "port", "mem" ],
+ outs => [ "res", "M" ],
+ emit => '. in%M %DS0, %SS0',
+ units => [ "GP" ],
+ latency => 1,
+ mode => mode_T,
+ modified_flags => $status_flags
+},
+
+#
+# Intel style prefetching
+#
+Prefetch0 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetcht0 %AM",
+ units => [ "GP" ],
+},
+
+Prefetch1 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetcht1 %AM",
+ units => [ "GP" ],
+},
+
+Prefetch2 => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetcht2 %AM",
+ units => [ "GP" ],
+},
+
+PrefetchNTA => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetchnta %AM",
+ units => [ "GP" ],
+},
+
+#
+# 3DNow! prefetch instructions
+#
+Prefetch => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetch %AM",
+ units => [ "GP" ],
+},
+
+PrefetchW => {
+ op_flags => "L|F",
+ state => "exc_pinned",
+ reg_req => { in => [ "gp", "gp", "none" ], out => [ "none" ] },
+ ins => [ "base", "index", "mem" ],
+ outs => [ "M" ],
+ latency => 0,
+ emit => ". prefetchw %AM",
+ units => [ "GP" ],
+},
+
#-----------------------------------------------------------------------------#
# _____ _____ ______ __ _ _ _ #
# / ____/ ____| ____| / _| | | | | | #
projects / libfirm / blobdiff